Computer architecture mcq (2)

1. A central processing unit, fabricated on a single chip of semiconductor is called:
a. Microprocessor
b. RAM
c. ROM
d. None of these
2. Which is the architecture of microprocessor:
a. CISC
b. RISC
c. All of these
d. None of these
3. CISC stands for:
a. Complex Instruction System Computer
b. Complex Instruction Set Car
c. Complex Instruction Set Computer
d. None of these
4. RISC stands for:
a. Reduced Instruction Set Computer
b. Reduced Intergraded Set Computer
c. Resource Instruction Set Computer
d. Resource Instruction System Computer
5. Which is the components of computer:
a. System Bus
b. CPU
c. Memory Unit
d. All of these
6. System Bus Contains:
a. Address Bus
b. Data Bus
c. Control Bus
d. All of these
7. Microprocessor is the _____ of computer:
a. Hand
b. Heart
c. Brain

d. Leg
8. Microprocessor is fabricated on single chip using:
a. MOS
b. ALU
c. CPU
d. All of these
9. Which is the components of microprocessor:
a. Register unit
b. Arithmetic and logical unit
c. Timing and control unit
d. All of these
10. Which is an integral part of any microcomputer system and its primary purpose is to hold program and
data:
a. Memory unit
b. Register unit
c. A and B
d. None of these
11. How many group of memory unit:
a. Four
b. Three
c. Two
d. One
12. Which is the parts of memory unit:
a. Processor memory
b. Main memory
c. Secondary memory
d. All of these
13. MOS stand for:

a. Metal oxide semiconductor
b. Memory oxide semiconductor
c. A and B
d. None of these
14. Which system communicates with the outside word via the I/O devices interfaced to it:
a. Microprocessor
b. Microcomputer
c. Digital computer
d. All of these
15. A computer which has the microprocessor as______ is called as a microcomputer:
a. CPU
b. ALU
c. RU
d. None of these
16. The organization of I/O devices create a difference between _____:
a. Digital computer
b. Micro computer
c. A and B
d. None of these
17. How many generation of microprocessor:
a. Four
b. Five
c. Six
d. Three
18. The___ was very successful in the calculator market at that time:
a. Motorola 6800 and 6809
b. Microprocessor 4004

c. Intel 8085
d. None of these
19. How are the successful microprocessor:
a. 8004
b. 5006
c. 4004
d. All of these
20. How many microprocessor in the market during the same period:
a. 6
b. 8
c. 3
d. 5
21. PMOS stands for:
a. P-channel metal-oxide-semiconductor
b. P-channel memory –oxide-semiconductor
c. Both A and B
d. None of these
22. Which provided the current:
a. Low-cost
b. Slow-cost
c. Low-Output
d. All the above
23. Second Generation_____?
a. 1974-1976
b. 1974-1978
c. 1974-1972
d. None of these
24. The beginning of very efficient____ microprocessor in second generation:
a. 4-bit
b. 8-bit
c. 16-bit
d. 64-bit

25. Which are some of popular processor:
a. Motorola 6800 and 6809
b. Intel 8085
c. Zilog Z80
d. All the above
26. NMOS stands for:
a. N-channel metal-oxide-semiconductor
b. P-channel metal-oxide-semiconductor
c. N-channel memory-oxide-semiconductor
d. All the above
27. _____ Was more common year:
a. CRT
b. TTL
c. Both A and B
d. None of these
28. Which technology speed faster and higher density:
a. PMOS
b. NMOS
c. HMOS
d. All the above
29. What is the period of 3 generation:
a. 1979-1981
b. 1979-1980
c. 1978-1979
d. 1978-1980
30. Third generation microprocessor is dominated by____ microprocessor:
a. 8 bit
b. 4 bit
c. 16 bit
d. 64 bit

31. Intel used HMOS technology to recreate_____:
a. 8084 A
b. 8086 A
c. 8085 A
d. 8088 A
32. HMOS stands for:
a. High performance metal oxide semiconductor
b. High processor metal oxide semiconductor
c. Both A and b
d. None of these
33. What is the period of fourth generation:
a. 1979-1980
b. 1981-1995
c. 1995-2000
d. 1974-1980
34. The fourth generation of microprocessor came really as a soon boon to the_____:
a. Computing environment
b. Processing environment
c. Hot environment
d. All of these
35. How many bit microprocessor in the era marked beginning of fourth generation:
a. 4 bit
b. 8 bit
c. 16 bit
d. 32 bit
36. They were fabricated using a low power version of the HMOS technology called____:
a. HSMOS
b. HCMOS
c. HSSOM
d. None of these

37. Motorola introduced _____ processor:
a. 2 bit-RISC
b. 4 bit-RISC
c. 8 bit-RISC
d. 32 bit-RISC
38. Motorola introduced 32 bit RISC processor called______:
a. MC 88100
b. MC 81100
c. MC 80100
d. MC 81000
39. Period of fifth generation?
a. 1974-1978
b. 1979-1980
c. 1981-1985
d. 1995-till date
40. The growth of vacuum tube technology has been listed as follow:
a. 1946-1957
b. 1958-1964
c. 1985-1999
d. None of these
41. The growth of transistor technology in_____:
a. 1946-1957
b. 1958-1964
c. 1985-1999
d. None of these
42. How are the growth of SSI technology in_____:
a. 1956 on words

b. 1965 on words
c. 1978 on words
d. 1978 on words
43. The growth of medium scale integration in______:
a. Till 1971
b. Till 1970
c. Till 1972
d. Till 1969
44. The growth of SSI up to____:
a. 100 device on a chip
b. 200 device on a chip
c. 300 device on a chip
d. 400 device on a chip
45. The growth of LSI technology on_____:
a. 1994-1995
b. 1971-1977
c. 1972-1978
d. None of these
46. Which is most commonly measured in terms of MIPS previously million instruction per second:
a. Microprocessor
b. Performance of a microprocessor
c. Assembly line
d. None of these
47. The range of this rating for which microprocessor of_____:
a. VLSI
b. Motorola
c. Intel
d. Zilog
48. How can we make computers work faster?

a. The fetch-execute cycle and pipelining
b. The assembly
c. Both A and B
d. None of these
49. Who is the represents the fundamental process in the operation of the CPU:
a. The fetch-execute cycle and pipelining
b. The assembly
c. Both A and B
d. None of these
50. Which process information at a much faster rate than it can retrieve it from memory:
a. ALU
b. Processor
c. Microprocessor
d. CPU
51. _____ memory system which is discussed later can improve matters in this respect:
a. Data memory
b. Cache memory
c. Memory
d. None of these
52. The fetch-execute cycle is to use a system know as:
a. Assembly line
b. Pipelining
c. Cache
d. None of these
53. The time taken for all stages of the assembly line to become active is called the:
a. Flow through time
b. Clock period
c. Throughput

d. All of these
54. The clock period is denoted by:
a. T p
b. T1+T2+T3-------+T n
c. Pt
d. None of these
55. Ti is the time taken for the ith stage and there are n stages in the:
a. Throughput
b. Assembly line
c. Both A and B
d. None of these
56. Who is the determined by the time taken by the stages the requires the most processing time:
a. Clock period
b. Flow through
c. Throughput
d. None of these
57. The ____ of can assembly line to be I/t p:
a. Clock period
b. Pipelining
c. Throughput
d. Flow through
58. Which is the microprocessor launched by Motorola corporation introduced:
a. Mc6800
b. 8080
c. IMP-8
d. RPS-8
59. How many bit MC6800 microprocessor:

a. 4-bit
b. 8-bit
c. 16-bit
d. 32-bit
60. Motorola has declined from having nearly __________ share of the microprocessor market to much
smaller share:
a. 30%
b. 40%
c. 50%
d. 60%
61. Which is the microprocessor launch by Fairchild company:
a. F-6
b. F-8
c. Both A and B
d. None of these
62. How many stages has fetch execute cycle:
a. 3
b. 4
c. 5
d. 6
63. Which is the world’s first microprocessor?
a. Intel 4004
b. Motorola 68020
c. Intel8008
d. None of these
64. MOSFET stands for?
a. Metal-oxide-semiconductor field effect transistor
b. Metal-oxide-semiconductor fan effort transistor
c. Both A and B
d. None of these
65. What is the main problem of Intel 4004 microprocessor:
a. Speed

b. Memory size
c. World width
d. All of these
66. The evolution of the 4 bit microprocessor ended when Intel released in:
a. 4004
b. 8008
c. 40964
d. 4040
67. How many bit microprocessor still survives in low-end application such as microwave ovens and small
control system:
a. 4 bit
b. 16 bit
c. 32 bit
d. 64 bit
68. Calculator are based on______ microprocessor:
a. 4 bit
b. 16 bit
c. 32 bit
d. 64 bit
69. BCD stands for:
a. Binary coded decimal
b. Based coded decimal
c. Both A and B
d. None of these
70. Intel 8008 microprocessor realizing in:
a. 1971
b. 1973
c. 1999
d. 1988

71. Intel 8008 microprocessor’s upgraded version is:
a. 8080
b. 4004
c. Both A and B
d. None of these
72. Intel 8008 microprocessor was introduced in:
a. 1971
b. 1973
c. 1999
d. 1988
73. MC6800 microprocessor was introduced by:
a. Motorola corporation
b. Fairchild
c. Both A and B
d. None of these
74. Which Microprocessor producer continue successfully to create newer and improved version of the
microprocessor:
a. Intel
b. Motorola
c. Both A and B
d. None of these
75. Motorola has declined how many % share of the microprocessor market to a much smaller share:
a. 50%
b. 55%
c. 48%
d. 51%
76. Which year Intel corporation introduced an updated version of the 8080- the 8085:

a. 1965
b. 1976
c. 1977
d. 1985
77. In 1977 which corporation introduced an updated version of the 8080- the 8085:
a. Motorola
b. Intel
c. Rockwell
d. National
78. How many bit microprocessor developed by Intel:
a. 4 bit
b. 8 bit
c. 32 bit
d. 64 bit
79. Which is the main feature of 8085:
a. Internal clock generator
b. Internal system controller
c. Higher clock frequency
d. All of these
80. Which is 16 Bit microprocessor:
a. 8088
b. 8086
c. 8085
d. All of these
81. How many speed of 8088,8085,8086 microprocessor:
a. 2.5 Million instruction per second
b. 1.5 Million instruction per second
c. 3.5 Million instruction per second
d. 1.6 Million instruction per second
82. Which year Intel family ensured:
a. 1965
b. 1978

c. 1981
d. 1999
83. Which corporation decided to use 8088 microprocessor in personal computer:
a. IBM
b. CRT
c. PMN
d. SPS
84. Which processor provided 1 MB memory:
a. 16-bit 8086 and 8088
b. 32-bit 8086 and 8088
c. 64-bit 8086 and 8088
d. 8-bit 8086 and 8088
85. Who was introduce the 80286 microprocessor updated on 8086,in 1983:
a. Intel
b. Motorola
c. Fairchild
d. None of these
86. Which is the microprocessor launched by Intel:
a. Z-8
b. 8080
c. 8000
d. None of these
87. Which is the microprocessor launched by national semiconductor:
a. IMP-4
b. IMP-8
c. IMP-6
d. IMP-7
88. Which is the microprocessor launched by Rockwell international:

a. RPS-4
b. RPS-6
c. RPS-8
d. All of these
89. Which is the microprocessor launched by Zilog:
a. Z-2
b. Z-4
c. Z-6
d. Z-8
90. CAD stands for:
a. Computer aided drafting
b. Compare aided drafting
c. Both A and B
d. None of these
91. GUI stands for:
a. Graphical user interface
b. Graph used Intel
c. Graphical use inter
d. None of these
92. VGA stands for:
a. Visual graph area
b. Visual graphics array
c. Visual graph accept
d. All of these
93. Pentium Pro Processor contains:
a. L1 Cache
b. L2 Cache
c. Both L1 & L2
d. None of these

94. L1 cache memory is places at ______
a. On Processor
b. On Mother Board
c. On Memory
d. All of these
95. L2 cache memory is places at ______
a. On Processor
b. On Mother Board
c. On Memory
d. All of these
96. Pentium Pro can address _____ of memory:
a. 4 GB
b. 128 GB
c. 256 GB
d. 512 GB
97. Which is the professional or Business version of Intel Processors:
a. Pentium II
b. Pentium Pro
c. Pentium MMX
d. Pentium Xeon
98. Pentium III processor is released in the form of:
a. Socket 370 Version
b. Slot 1 Version in Plastic Cartridge
c. Both a and b
d. None of these
99. What is the maximum clock speed of P III processors
a. 1.0 GHz
b. 1.1 GHz
c. 1.2 GHz
d. 1.3 GHz

100. Power PC microprocessor architecture is developed by:
a. Apple
b. IBM
c. Motorola
d. All of these
101. Which is not the main architectural feature of Power PC:
a. It is not based on RISC
b. Superscalar implementation
c. Both 32 & 64 Bit
d. Paged Memory management architecture
102. Alpha AXP is developed by:
a. DEC
b. IBM
c. Motorola
d. Intel
103. Which is not the main feature of DEC Alpha:
a. 64 Bit RISC processor
b. Designed to replace 32 VAX(CISC)
c. Seven stage split integer/floating point pipeline
d. Variable Instruction length
104. Which is not the open-source OS:
a. Debian
b. BSD Unix
c. Gentoo & Red Hat Linux
d. Windows
105. ISA stands for:
a. Instruct set area
b. Instruction set architecture
c. Both a and b
d. None of these
106. RISC stands for:
a. Reduced Instruction set computer
b. Reduced Instruct set compare
c. Reduced instruction stands computer

d. All of these
107. DEC stands for:
a. Digital electronic computer
b. Digital electronic corporation
c. Digital equipment corporation
d. None of these
108. How many architectural paradigms in microprocessor:
a. 2
b. 3
c. 4
d. 6
109. Which are the architectural paradigms in microprocessor:
a. RISC
b. CISC
c. PISC
d. A and B
110. CISC stands for:
a. Complex instruction set computer
b. Camper instruct set of computer
c. Compared instruction set computer
d. None of these
111. PC’s use____ based on this architecture:
a. CPU
b. ALU
c. MU
d. None of these
No: 1 ( Marks: 1 ) - Please choose one For any of the instructions that are a part of the
instruction set of the SRC, there are cerain_________required; which may be used to select the
appropriate function for the ALU to be performed, to select the appropriate registers, or the
appropriate memory location. ►Register ►Control signals (Page 171) ►Memory ►None of
the given Question No: 2 ( Marks: 1 ) - Please choose one FALCON-A processor bus has 16
lines or is 16-bits wide while that of SRC _____wide. ►8-bits ►16-bits ►32-bits (Page 157)
►64-bits Question No: 3 ( Marks: 1 ) - Please choose one What is the instruction length of the
FALCON-A processor? ►8-bits ►16-bits (Page 134) ►32-bits ►64-bits Question No: 4 (

Marks: 1 ) - Please choose one _________control signals enable the input to the PC for
receiving a value that is currently on the internal processor bus. ►LPC (Page 172) ►INC4
►LC ► 2
Question No: 5 ( Marks: 1 ) - Please choose one Which one of the following is a bi-stable
device, capable of storing one bit of information? ►Decoder ►Flip-Flop (Page 76)
►Multiplexer ►Diplexer Question No: 6 ( Marks: 1 ) - Please choose one Which instruction
is used to store register to memory using relative address? ►ld instruction ►ldr instruction ►lar
instruction ►str instruction (Page 48) Question No: 7 ( Marks: 1 ) - Please choose one
Which field of the machine language instruction is the “type of operation” that is to be
performed? ►Op-code (Page 33) ►CPU registers ►Momory cells ►I/O locations Question
No: 8 ( Marks: 1 ) - Please choose one The instruction ___________ will load the register R3
with the contenets of the memory location M [PC+56] ►Add R3, 56 ►lar R3, 56 ►ldr R3, 56
(Page 56) ►str R3, 56 Question No: 9 ( Marks: 1 ) - Please choose one _______ operation is
required to change the processor‟s state to a known, defined value. ►Change ►Reset (Page
194) ►Update ►None of the given Question No: 10 ( Marks: 1 ) - Please choose one which
type of instructions help in changing the flow of the program as and when required?
►Arithmetic ►Control (Page 137) ►Data transfer ►Floating point 3
Question No: 11 ( Marks: 1 ) - Please choose one Which one of the following registers holds
the address of the next instruction to be executed? ►Accumulator ►Address Mask
►Instruction Register ►Program Counter (Page 151) Question No: 12 ( Marks: 1 ) - Please
choose one Which one of the following is the memory organization of EAGLE processor? ►8-
bits (Page 112) ►16-bits ►32-bit ►64-bits Question No: 13 ( Marks: 1 ) - Please choose one
The external interface of FALCON-A consists of a ______address bus and ______a data bus.
►8-bit. 8-bit
►16-bit. 16-bit Click here for detail ►16-bit. 24-bit ►16-bit. 32-bit Question No: 14 ( Marks:
1 ) - Please choose one Type A of SRC has which of the following instructions? A) andi,
instruction b) No operation or nop instruction c) lar instruction d) ldr instruction e) Stop
operation or stop instruction ►& (b) ►(b) & (c) ►& (e) ►(b) & (e) (Page 47)
MIDTERM EXAMINATION Spring 2010 CS501- Advance Computer Architecture
(Session- 5) Question No: 1 ( Marks: 1 ) - Please choose one What is the instruction length
of the SRC processor? ► 8 bits ► 16 bits ► 32 bits (Page 134) ► 64 bits Question No: 2 (
Marks: 1 ) - Please choose one Which one of the following is the memory organization of
FALCON-E processor? ► 28 * 8 bits ► 216 * 8 bits ► 232 * 8 bits (Page 124) ► 264 * 8 bits
Question No: 3 ( Marks: 1 ) - Please choose one “If P = 1, then load the contents of
register R1 into register R2”. This statement can be written in RTL as: ► R1 ¬ R2 ► P:
R1 ¬ R2
► P: R2 ¬ R1 (not confirms) click here for detail ► P: R2 ¬ R1, P: R1 ¬ R2 Question No: 4
( Marks: 1 ) - Please choose one The instruction ---------------will load the register R3 with the
ldr R3,
56 (Page 47) rep Question No: 5 ( Marks: 1 ) - Please choose one ----------are
CPU registers (Page 33)
Question No: 6 ( Marks: 1 ) - Please choose one P: R3 ¬ R5 MAR ¬ IR These two are
instructions written using RTL .If these two operations is to occur simultaneously then which
symbol will we use to separate them so that it becomes a correct statement with the condition
that two operations occur simultaneously? ► Arrow ¬ ► Colon : ► Comma , (Page 69) ►

Parentheses () Question No: 7 ( Marks: 1 ) - Please choose one Prefetching can be considered a
primitive form of------------- Pipelining (Page 42) - -
Question No: 8 ( Marks: 1 ) - Please choose one The processor
must have a way of saving information about its state or context so that it can be restored upon
return from the -------------
► Exception Click here for detail Question
No: 9 ( Marks: 1 ) - Please choose one Which one of the following circuit design levels is
called the gate level? Logic Design Level (Page 22)
Question No: 10 ( Marks: 1 ) - Please choose one __________
enable the input to the PC for receiving a value that is currently on the internal processor bus. ►
LPC (Page 172) rep ► INC4 ► LC ► Cout
6
Question No: 11 ( Marks: 1 ) - Please choose one ________ operation is required to change the
processor‟s state to a known, defined value. ► Change ► Reset (Page 194) rep ► Update ►
None of the given Question No: 12 ( Marks: 1 ) - Please choose one There are _________
types of reset operations in SRC ► Two (Page 195) ► Three ► Four ► Five Question No: 13
( Marks: 1 ) - Please choose one _____________ controller controls the sequence of the flow of
microinstructions. ► Multiplexer ► Microprogram (Page 225) ► ALU ► None of the given
Question No: 14 ( Marks: 1 ) - Please choose one FALCON-A processor bus has 16 lines or is
16-bits wide while that of SRC is __________ wide. ► 8-bits ► 24-bits ► 32-bits (Page 157)
REP ► 64-bits Question No: 15 ( Marks: 1 ) - Please choose one Which of the following
statement(s) is/are correct about Reduced Instruction Set Computer (RISC) architectures.
(i) The typical RISC machine instruction set is small, and is usually a subject of a CISC
instruction set. (ii) No arithmetic or logical instruction can refer to the memory directly. (iii) A
comparatively large number of user registers are available. (iv) Instructions can be easily
decoded through hard-wired control units. ► (i) and (iii) only ► (i), (iii) and (iv) ► (i), (ii) and
(iii) only ► (i),(ii),(iii) and (iv)
7
Question No: 16 ( Marks: 1 ) - Please choose one Which one of the following register holds the
instruction that is being executed? ► Accumulator ► Address Mask ► Instruction Register
(Page 152) ► Program Counter
No: 1 ( Marks: 1 ) - Please choose one _____________all memory systems are dumb, in that
they respond to only two commands: read or write Virtually Computer Systems Design And
Architecture, 2/E Logically Physically None of These Question No: 2 ( Marks: 1 ) - Please
choose one To access an operand in memory, the CPU must first generate an address, which it
then issues to the __________ MEMORY Computer Systems DesignAnd Architecture, 2/E
REGISTER DATA BUS ALL OF ABOVE Question No: 3 ( Marks: 1 ) - Please choose one
___________ or Branch instructions affect the order in which instructions are performed, or
control the flow of the program Control Computer Systems DesignAnd Architecture, 2/E
DATA MOVMENT Arithmetic LOGICAL
MIDTERM EXAMINATION FALL 2006 CS501 - ADVANCE COMPUTER
ARCHITECTURE Question No: 1 ( Marks: 1 ) - Please choose one The code size of 2-
address instruction is ________________. ► 5 bytes ► 7 bytes (Page 36) ► 3 bytes ► 2
bytes Question No: 2 ( Marks: 1 )- Please choose one The data movement instructions
___________ data within the machine and to or from input/output devices. ► Store ► Load

► Move Click here for detail ► None of Above Question No: 3 ( Marks: 1 ) - Please choose
one Register-register instructions use ____________ memory operands out of a total of 3
operands ► 1 ► 3 ► 0 (Page 37) ► 2 Question No: 4 ( Marks: 1 ) - Please choose one
_____________all memory systems are dumb, in that they respond to only two commands: read
or write. ► Virtually Computer Systems DesignAnd Architecture, 2/E Rep ► Logically ►
Physically ► None of Above Question No: 5 ( Marks: 1 ) - Please choose one Flip-flop is a
____________device, capable of storing one bit of Information ► Bi-stable (Page 76) ► Unit-
stable ► Stable ► Storage
Question # 1 of 10 ( Marks: 1 ) - Please choose one In which one of the following addressing
modes, the value to be stored in memory is obtained by directly retrieving it from another
memory location?
►Direct Addressing Mode Click here for detail ►Immediate addressing mode ►Indirect
Addressing Mode ►Register (Direct) Addressing Mode Question # 2 of 10 ( Marks: 1 ) -
Please choose one Execution time of a program with respect to the processor is calculated as:
►Execution Time = IC x CPI x MIPS ►Execution Time = IC x CPI x T (Page 254)
►Execution Time = CPI x T x MFLOPS ►Execution Time = IC x T Question # 3 of 10 (
Marks: 1 ) - Please choose one An “assembler” that runs on one processor and translates an
assembly language program written for another processor into the machine language of the other
processor is called a ---------------- ►compiler ►cross assembler (Page 26) ►debugger
►linker Question # 4 of 10 ( Marks: 1 ) - Please choose one What functionality is performed
by the instruction “lar R3, 36” of SRC? ►It will load the register R3 with the contents of the
memory location M [PC+36] ►It will load the register R3 with the relative address itself
(PC+36). (Page 48) ►It will store the register R3 contents to the memory location M [PC+36]
►No operation Question # 5 of 10 ( Marks: 1 ) - Please choose one Which operator is used to
„name‟ registers, or part of registers, in the Register Transfer Language? Select correct option:
►:= (Page 66) ►& ►% ►©
Question # 6 of 10 ( Marks: 1 ) - Please choose one What is the working of Processor Status
Word (PSW)? ►To hold the current status of the processor. (Page 28) ►To hold the address
of the current process ►To hold the instruction that the computer is currently processing ►To
hold the address of the next instruction in memory that is to be executed Question # 7 of 10 (
Marks: 1 ) - Please choose one Almost every commercial computer has its own particular -------
--- language ►3GL ►English language ►Higher level language ►assembly language (Page
25) Question # 8 of 10 ( Marks: 1 ) - Please choose one In which of the following instructions
the data move between a register in the processor and a memory location (or another register)
and are also called data movement? ►Arithmetic/logic ►Load/store (Page 141) ►Test/branch
►None of the given Question # 9 of 10 ( Marks: 1 ) - Please choose one What functionality is
performed by the instruction “str R8, 34” of SRC? ►It will load the register R8 with the contents
of the memory location M [PC+34] ►It will load the register R8 with the relative address itself
(PC+34). ►It will store the register R8 contents to the memory location M [PC+34] (Page
48) ►No operation Question # 10 of 10 ( Marks: 1 ) - Please choose one What does the
instruction “ldr R3, 58” of SRC do? ►It will load the register R3 with the contents of the
memory location M [PC+58] (Page 47) ►It will load the register R3 with the relative address
itself (PC+58). ►It will store the register R3 contents to the memory location M [PC+58] ►No
operation
Question # 1 of 10 ( Marks: 1 ) - Please choose one Which one of the following is the highest
level of abstraction in digital design in which the computer architect views the system for the

description of system components and their interconnections? ►Processor-Memory-Switch
level (PMS level) (Page 22) ►Instruction Set Level ►Register Transfer Level ►None of the
given Question # 2 of 10 ( Marks: 1 ) - Please choose one Which of the instruction is used to
load register from memory using a relative address? ►ld instruction ►ldr instruction (Page 47)
►lar instruction ►str instruction Question # 3 of 10 ( Marks: 1 ) - Please choose one For the
__________ type instructions, we require a register to hold the data that is to be loaded from the
memory, or stored back to the memory ►Jump ►Control ►load/store (Page 89) ►None of the
given Question # 4 of 10 ( Marks: 1 ) - Please choose one The CPU includes three types of
instructions, which have different operands and will need different representations. Which one of
the instructions requires two source registers? ►Jump and branch format instructions
►Immediate format instructions
►Registerformat instructions Click here for detail
CS501 Advance Computer Architecture Quiz No.2 (May07, 2012) Question # 1
of 10 (Marks: 1) - Please choose one What is the size of the memory space that is available to
FALCON-A processor? ►2^8 bytes ►2^16 bytes (Page 90) ►2^32 bytes ►2^64 bytes
Question # 2 of 10 (Marks: 1) - Please choose one How can we refer to an instruction register
(IR), of 16 bits (numbered 0 to 15) using RTL? ►IR<16..0> ►IR<15..0> (Page 105)
►IR<16..1> ►IR<15..1> Question # 3 of 10 (Marks: 1) - Please choose one Which one of the
following portions of an instruction represents the operation to be performed? ►Address
►Instruction code ►Opcode ►Operand (Page 134) Question # 4 of 10 (Marks: 1) - Please
choose one Identify the opcode, destination register (DR), source registers (SA and SB i/e source
register A and source register B) from the following example. ADD R1, R2, R3 ►Opcode= R1,
DR=ADD, SA=R2, SB=R3 ►Opcode= ADD, DR=R1, SA=R2, SB=R3 (Page 34) ►Opcode=
R2, DR=ADD, SA=R1, SB=R3 ►Opcode= ADD, DR=R3, SA=R2, SB=R1 Question # 5 of 10
(Marks: 1) - Please choose one
What does the word „D‟ in the „D-flip-Flop‟ stands for? ►Data Click here for detail ►Digital
►Dynamic ►Double
Question # 6 of 10 (Marks: 1) - Please choose one Which one of the following is the code size
and the Number of memory bytes respectively for a 2-address instruction? ►4 bytes, 7 bytes ►7
bytes, 16 bytes (Page 36) ►10 bytes, 19 bytes ►13 bytes, 22 bytes Question # 7 of 10 (Marks:
1) - Please choose one Which of the following can be defined as an address of the operand in a
computer type instruction or the target address in a branch type instruction? ►Base address
►Binary address ►Effective address Click here for detail ►All of the given Question # 8 of
10 (Marks: 1) - Please choose one Whic of the following statements is/are true about RISC
processors‟ claimed advantages over CISC processors? (a) Keeping regularly accessed variables
in registers as opposed to keeping them in memory facilitates faster execution. (b) RISC CPUs
outperform CISC CPU‟s in procedural programming environments. (c) Instruction pipelining
has helped RISC CPU‟s to attain a target of 1 cycle per instruction. (d) It is easier to maintain the
“family concept” in RISC CPUs. ► (a), (b) &(c) ► (b), (c) & (e) ► (c), (d) & (e) ► (a), (c) &
(d) Question # 9 of 10 (Marks: 1) - Please choose one Which one of the following is/are the
features of Register Transfer Language? a) It is a symbolic language b) It is describing the
internal organization of digital computers c) It is an elementary operation performed (during one
clock pulse), on the information stored in one or more registers d) It is high level language
► (b) only ► (a) & (b) only Click here for detail ► (a) ,(b) & (d) ► (b),(c) & (d) 14
Question # 10 of 10 (Marks: 1) - Please choose one Motorola MC68000 is an example of ------
---microprocessor. ►CISC (Page 148) ►RISC ►SRC ►FALCON Question # 1 of 10

(Marks: 1) - Please choose one Which one of the following registers holds the instruction that is
being executed? ►Accumulator ►Address Mask ►Instruction Register(Page 152) rep
►Program Counter Question # 2 of 10 (Marks: 1) - Please choose one The external interface
of FALCON-A consists of a ________ data bus. ►8-bit ►16-bit (Page 167) ►24-bit ►32-bit
Question # 3 of 10 (Marks: 1) - Please choose one In which one of the following techniques,
the time a processor spends waiting for instructions to be fetched from memory is minimized?
Select correct option: ►Perfecting Click here for detail ►Pipelining ►Superscalar operation
►Speedup Question # 4 of 10 (Marks: 1) - Please choose one -----------is the ability of
application software to operate on models of equipment newer than the model for which it was
originally developed. Select correct option: ►Backward compatibility ►Data migration
►Reverse engineering ►Upward compatibility
Question # 5 of 10 (Marks: 1) - Please choose one _________ control signal allows the
contents of the Program Counter register to be written onto the internal processor bus. ►INC4
►LPC ►PCout (Page 172) ►LC Question # 6 of 10 (Marks: 1) - Please choose one Which
one of the following registers stores a previously calculated value or a value loaded from the
main memory? ►Accumulator Click here for detail ►Address Mask ►Instruction Register
►Program Counter Question # 7 of 10 (Marks: 1) - Please choose one Computer system
performance is usually measured by the --------------- ►Time to execute a program or
program mix Click here for detail ►The speed with which it executes programs ►Processor‟s
utilization in solving the problems ►Instructions that can be carried out simultaneously
Question # 8 of 10 (Marks: 1) - Please choose one Which one of the following register(s) that
is/are programmer invisible and is/are required to hold an operand or result value while the bus is
busy transmitting some other value? ►Instruction Register ►Memory address register
►Memory Buffer Register ►Registers A and C (Page 152) Question # 9 of 10 (Marks: 1) -
Please choose one -------------- performs the data operations as commanded by the program
instructions. ►Control
►Data path click here for detail ►Structural RTL ►Timing
Question # 10 of 10 (Marks: 1) - Please choose one
Which one of the following register(s) contain(s) the address of the place the CPU wants to work
with in the main memory and is/are directly connected to the RAM chips on the motherboard?
►Instruction Register ►Memory address register Click here for detail ►Memory Buffer
Register ►Registers A an
Set - 1
Question 1:
Where does acomputer add and compare data?
a. Hard disk
b. Floppy disk
c. CPU chip
d. Memory chip
Collection on http://www.cs-mcqs.blogspot.com
Question 2:
Which of the following registers is used to keep track of address of the memory location where the next
instruction is located?
a. Memory Address Register

b. Memory Data Register
c. Instruction Register
d. Program Register
Question 3:
A complete microcomputer system consists of
a. microprocessor
b. memory
c. peripheral equipment
d. all of above
Question 4:
CPU does not perform the operation
a. data transfer
b. logic operation
c. arithmetic operation
d. all of above
Question 5:
Pipelining strategy is called implement
a. instruction execution
b. instruction prefetch
c. instruction decoding
d. instruction manipulation
Question 6:
A stack is
a. an 8-bit register in the microprocessor
b. a 16-bit register in the microprocessor
c. a set of memory locations in R/WM reserved for storing information temporarily during the
execution of computer
d. a 16-bit memory address stored in the program counter
Question 7:
A stack pointer is
a. a 16-bit register in the microprocessor that indicate the beginning of the stack memory.
b. a register that decodes and executes 16-bit arithmetic expression.
c. The first memory location where a subroutine address is stored.
d. a register in which flag bits are stored
Question 8:
The branch logic that provides decision making capabilities in the control unit is known as
a. controlled transfer
b. conditional transfer
c. unconditional transfer
d. none of above

Question 9:
Interrupts which are initiated by an instruction are
a. internal
b. external
c. hardware
d. software
Question 10:
A time sharing system imply
a. more than one processor in the system
b. more than one program in memory
c. more than one memory in the system
d. None of above
Answers:
1. c
2. d
3. d
4. d
5. b
6. c
7. a
8. c
9. d
10. b
SET-2
Question 1:
Processors of all computers, whether micro, mini or mainframe must have
a. ALU
b. Primary Storage
c. Control unit
d. All of above
Question 2:
What is the control unit's function in the CPU?
a. To transfer data to primary storage
b. to store program instruction
c. to perform logic operations
d. to decode program instruction
Question 3:
What is meant by a dedicated computer?
a. which is used by one person only
b. which is assigned to one and only one task
c. which does one kind of software
d. which is meant for application software only

Question 4:
The most common addressing techiniques employed by a CPU is
a. immediate
b. direct
c. indirect
d. register
e. all of the above
Question 5:
Pipeline implement
a. fetch instruction
b. decode instruction
c. fetch operand
d. calculate operand
e. execute instruction
f. all of abve
Question 6:
Which of the following code is used in present day computing was developed by IBM corporation?
a. ASCII
b. Hollerith Code
c. Baudot code
d. EBCDIC code
Question 7:
When a subroutine is called, the address of the instruction following the CALL instructions stored in/on
the
a. stack pointer
b. accumulator
c. program counter
d. stack
Question 8:
A microprogram written as string of 0's and 1's is a
a. symbolic microinstruction
b. binary microinstruction
c. symbolic microprogram
d. binary microprogram
Question 9:
Interrupts which are initiated by an instruction are
a. internal
b. external
c. hardware
d. software
Question 10:
Memory access in RISC architecture is limited to instructions
a. CALL and RET
b. PUSH and POP
c. STA and LDA
d. MOV and JMP

Answers:
1. d 2. d 3. b 4. e 5. f 6. d 7. d 8. d 9. b 10. c
SET-3
Computer Architecture and Organization Set - 3
Question 1:
A collection of 8 bits is called
a. byte
b. word
c. record
Question 2:
The ascending order or a data Hierarchy is
a. bit - bytes - fields - record - file - database
b. bit - bytes - record - field - file - database
c. bytes - bit- field - record - file - database
d. bytes -bit - record - field - file - database
Question 3:
How many address lines are needed to address each memory locations in a 2048 x 4 memory chip?
a. 10
b. 11
c. 8
d. 12
Question 4:
A computer program that converts an entire program into machine language at one time is called a/an
a. interpreter
b. simulator
c. compiler
d. commander
Question 5:
In immediate addressing the operand is placed
a. in the CPU register
b. after OP code in the instruction
c. in memory
d. in stack
Question 6:
Microprocessor 8085 can address location upto
a. 32K
b. 128K
c. 64K
d. 1M

Question 7:
The ALU and control unit of most of the microcomputers are combined and manufacture on a single
silicon chip. What is it called?
a. monochip
b. microprocessor
c. ALU
d. control unit
Question 8:
When the RET instruction at the end of subroutine is executed,
a. the information where the stack is iniatialized is transferred to the stack pointer
b. the memory address of the RET instruction is transferred to the program counter
c. two data bytes stored in the top two locations of the stack are transferred to the program counter
d. two data bytes stored in the top two locations of the stack are transferred to the stack pointer
Question 9:
A microporgram is sequencer perform the operation
a. read
b. write
c. execute
d. read and write
e. read and execute
Question 10:
Interrupts which are initiated by an I/O drive are
a. internal
b. external
c. software
d. all of above
Answers:
1. a 2. a 3. b 4. c 5.b 6.c 7.b 8.c 9.e 10.b
his set of Computer Organization and Architecture Multiple Choice Questions & Answers (MCQs)
focuses on “Addressing Modes”.
1. The instruction, Add #45,R1 does _______
a) Adds the value of 45 to the address of R1 and stores 45 in that address
b) Adds 45 to the value of R1 and stores it in R1
c) Finds the memory location 45 and adds that content to that of R1
d) None of the mentioned
View Answer
Answer: b
Explanation: The instruction is using immediate addressing mode hence the value is stored in the
location 45 is added.

2. In case of, Zero-address instruction method the operands are stored in _____
a) Registers
b) Accumulators
c) Push down stack
d) Cache
View Answer
Answer: c
Explanation: In this case the operands are implicitly loaded onto the ALU.
3. Add #45, when this instruction is executed the following happen/s _______
a) The processor raises an error and requests for one more operand
b) The value stored in memory location 45 is retrieved and one more operand is requested
c) The value 45 gets added to the value on the stack and is pushed onto the stack
View Answer
Answer: b
Explanation: None.
4. The addressing mode which makes use of in-direction pointers is ______
a) Indirect addressing mode
b) Index addressing mode
c) Relative addressing mode
d) Offset addressing mode
View Answer
Answer: a
Explanation: In this addressing mode, the value of the register serves as another memory location
and hence we use pointers to get the data.
5. In the following indexed addressing mode instruction, MOV 5(R1),LOC the effective address is
______
a) EA = 5+R1
b) EA = R1
c) EA = [R1] d) EA = 5+[R1] View Answer
Answer: d
Explanation: This instruction is in Base with offset addressing mode.
6. The addressing mode/s, which uses the PC instead of a general purpose register is ______
a) Indexed with offset
b) Relative
c) direct

d) both Indexed with offset and direct
View Answer
Answer: b
Explanation: In this the contents of the PC are directly incremented.
7. When we use auto increment or auto decrements, which of the following is/are true?
1) In both, the address is used to retrieve the operand and then the address gets altered
2) In auto increment the operand is retrieved first and then the address altered
3) Both of them can be used on general purpose registers as well as memory locations
a) 1, 2, 3
b) 2
c) 1, 3
d) 2, 3
View Answer
Answer: d
Explanation: In case of, auto increment the increment is done afterwards and in auto decrement the
decrement is done first.
8. The addressing mode, where you directly specify the operand value is _______
a) Immediate
b) Direct
c) Definite
d) Relative
View Answer
Answer: a
Explanation: None.
9. The effective address of the following instruction is, MUL 5(R1,R2).
a) 5+R1+R2
b) 5+(R1*R2)
c) 5+[R1]+[R2].
d) 5*([R1]+[R2])
View Answer
Answer: c
Explanation: The addressing mode used is base with offset and index.
10. _____ addressing mode is most suitable to change the normal sequence of execution of
instructions.
a) Relative
b) Indirect

c) Index with Offset
d) Immediate
View Answer
Answer: a
Explanation: The relative addressing mode is used for this since it directly updates the PC.
his set of Computer Organization Questions and Answers for Aptitude test focuses on “Numbers and
Arithmetic Operations”.
1. Which method/s of representation of numbers occupies large amount of memory than others ?
a) Sign-magnitude
b) 1’s compliment
c) 2’s compliment
d) 1’s & 2’s compliment
View Answer
Answer: a
Explanation: It takes more memory as one bit used up to store the sign.
2. Which representation is most efficient to perform arithmetic operations on the numbers ?
a) Sign-magnitude
b) 1’s compliment
c) 2’S compliment
View Answer
Answer: c
Explanation: The two’s compliment form is more suitable to perform arithmetic operations as there is
no need to involve the sign of the number into consideration.
3. Which method of representation has two representations for ‘0’ ?
a) Sign-magnitude
b) 1’s compliment
c) 2’s compliment
View Answer
Answer: a
Explanation: One is positive and one for negative.
4. When we perform subtraction on -7 and 1 the answer in 2’s compliment form is _________
a) 1010
b) 1110
c) 0110

d) 1000
View Answer
Answer: d
Explanation: First the 2’s compliment is found and that is added to the number and the overflow is
ignored.
5. When we perform subtraction on -7 and -5 the answer in 2’s compliment form is ________
a) 11110
b) 1110
c) 1010
d) 0010
View Answer
Answer: b
ignored.
6. When we subtract -3 from 2 , the answer in 2’s compliment form is _________
a) 0001
b) 1101
c) 0101
d) 1001
View Answer
Answer: c
ignored.
7. The processor keeps track of the results of its operations using a flags called ________
a) Conditional code flags
b) Test output flags
c) Type flags
View Answer
Answer: a
Explanation: These flags are used to indicate if there is a overflow or carry or zero result occurrence.
8. The register used to store the flags is called as _________
a) Flag register
b) Status register
c) Test register
d) Log register
View Answer

Answer: b
Explanation: The status register stores the condition codes of the system.
9. The Flag ‘V’ is set to 1 indicates that,
a) The operation is valid
b) The operation is validated
c) The operation as resulted in an overflow
View Answer
Answer: c
Explanation: This is used to check the overflow occurrence in the operation.
10. In some pipelined systems, a different instruction is used to add to numbers which can affect the
flags upon execution. That instruction is _______
a) AddSetCC
b) AddCC
c) Add++
d) SumSetCC
View Answer
Answer: a
Explanation: By using this instruction the condition flags wont be affected at all.
11. The most efficient method followed by computers to multiply two unsigned numbers is _______
a) Booth algorithm
b) Bit pair recording of multipliers
c) Restoring algorithm
d) Non restoring algorithm
View Answer
Answer: b
Explanation: None.
12. For the addition of large integers most of the systems make use of ______
a) Fast adders
b) Full adders
c) Carry look-ahead adders
View Answer
Answer: c
Explanation: In this method the carries for each step are generated first.
13. In a normal n-bit adder, to find out if an overflow as occured we make use of ________
a) And gate

b) Nand gate
c) Nor gate
d) Xor gate
View Answer
Answer: d
Explanation: None.
14. In the implementation of a Multiplier circuit in the system we make use of _______
a) Counter
b) Flip flop
c) Shift register
d) Push down stack
View Answer
Answer: c
Explanation: The shift registers are used to store the multiplied answer.
15. When 1101 is used to divide 100010010 the remainder is ______
a) 101
b) 11
c) 0
d) 1
View Answer
Answer: d
Explanation: None.
This set of Computer Organization and Architecture Multiple Choice Questions & Answers (MCQs)
focuses on “Caches”.
1. The reason for the implementation of the cache memory is ________
a) To increase the internal memory of the system
b) The difference in speeds of operation of the processor and memory
c) To reduce the memory access and cycle time
d) All of the mentioned
View Answer
Answer: b
Explanation: This difference in the speeds of operation of the system caused it to be inefficient.
2. The effectiveness of the cache memory is based on the property of ________
a) Locality of reference
b) Memory localisation
c) Memory size

View Answer
Answer: a
Explanation: This means that the cache depends on the location in the memory that is referenced
often.
3. The temporal aspect of the locality of reference means
a) That the recently executed instruction wont be executed soon
b) That the recently executed instruction is temporarily not referenced
c) That the recently executed instruction will be executed soon again
View Answer
Answer: c
Explanation: None.
4. The spatial aspect of the locality of reference means
a) That the recently executed instruction is executed again next
b) That the recently executed wont be executed again
c) That the instruction executed will be executed at a later time
d) That the instruction in close proximity of the instruction executed will be executed in future
View Answer
Answer: d
Explanation: The spatial aspect of locality of reference tells that the nearby instruction is more likely
to be executed in future.
5. The correspondence between the main memory blocks and those in the cache is given by
_________
a) Hash function
b) Mapping function
c) Locale function
d) Assign function
View Answer
Answer: b
Explanation: The mapping function is used to map the contents of the memory to the cache.
6. The algorithm to remove and place new contents into the cache is called _______
a) Replacement algorithm
b) Renewal algorithm
c) Updation
View Answer

Answer: a
Explanation: As the cache gets full, older contents of the cache are swapped out with newer
contents. This decision is taken by the algorithm.
7. The write-through procedure is used
a) To write onto the memory directly
b) To write and read from memory simultaneously
c) To write directly on the memory and the cache simultaneously
View Answer
Answer: c
Explanation: When write operation is issued then the corresponding operation is performed.
8. The bit used to signify that the cache location is updated is ________
a) Dirty bit
b) Update bit
c) Reference bit
d) Flag bit
View Answer
Answer: a
Explanation: When the cache location is updated in order to signal to the processor this bit is used.
9. The copy-back protocol is used
a) To copy the contents of the memory onto the cache
b) To update the contents of the memory from the cache
c) To remove the contents of the cache and push it on to the memory
View Answer
Answer: b
Explanation: This is another way of performing the write operation,wherein the cache is updated first
and then the memory.
10. The approach where the memory contents are transfered directly to the processor from the
memory is called ______
a) Read-later
b) Read-through
c) Early-start
View Answer
Answer: c
Explanation: None.

s set of Computer Organization and Architecture Multiple Choice Questions & Answers (MCQs)
focuses on “Pipe-lining”.
1. ______ have been developed specifically for pipelined systems.
a) Utility softwares
b) Speed up utilities
c) Optimizing compilers
View Answer
Answer: c
Explanation: The compilers which are designed to remove redundant parts of the code are called as
optimizing compilers.
2. The pipelining process is also called as ______
a) Superscalar operation
b) Assembly line operation
c) Von neumann cycle
View Answer
Answer: b
Explanation: It is called so because it performs its operation at assembly level.
3. The fetch and execution cycles are interleaved with the help of ________
a) Modification in processor architecture
b) Clock
c) Special unit
d) Control unit
View Answer
Answer: b
Explanation: The time cycle of the clock is adjusted to perform the interleaving.
4. Each stage in pipelining should be completed within ____ cycle.
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: a
Explanation: The stages in the pipelining should get completed within one cycle to increase the
speed of performance.

5. In pipelining the task which requires the least time is performed first.
a) True
b) False
View Answer
Answer: b
Explanation: This is done to avoid starvation of the longer task.
6. If a unit completes its task before the allotted time period, then
a) It’ll perform some other task in the remaining time
b) Its time gets reallocated to different task
c) It’ll remain idle for the remaining time
View Answer
Answer: c
Explanation: None.
7. To increase the speed of memory access in pipelining, we make use of _______
a) Special memory locations
b) Special purpose registers
c) Cache
d) Buffers
View Answer
Answer: c
Explanation: By using the cache we can reduce the speed of memory access by a factor of 10.
8. The periods of time when the unit is idle is called as _____
a) Stalls
b) Bubbles
c) Hazards
d) Both Stalls and Bubbles
View Answer
Answer: d
Explanation: The stalls are a type of hazards that affect a pipelined system.
9. The contention for the usage of a hardware device is called as ______
a) Structural hazard
b) Stalk
c) Deadlock
View Answer

Answer: a
Explanation: None.
10. The situation where in the data of operands are not available is called ______
a) Data hazard
b) Stock
c) Deadlock
d) Structural hazard
View Answer
Answer: a
Explanation: Data hazards are generally caused when the data is not ready on the destination side.
This set of Computer Organization and Architecture Multiple Choice Questions & Answers (MCQs)
focuses on “Pipe-lining”.
1. ______ have been developed specifically for pipelined systems.
a) Utility softwares
b) Speed up utilities
c) Optimizing compilers
View Answer
Answer: c
Explanation: The compilers which are designed to remove redundant parts of the code are called as
optimizing compilers.
2. The pipelining process is also called as ______
a) Superscalar operation
b) Assembly line operation
c) Von neumann cycle
View Answer
Answer: b
Explanation: It is called so because it performs its operation at assembly level.
3. The fetch and execution cycles are interleaved with the help of ________
a) Modification in processor architecture
b) Clock
c) Special unit
d) Control unit
View Answer
Answer: b
Explanation: The time cycle of the clock is adjusted to perform the interleaving.

4. Each stage in pipelining should be completed within ____ cycle.
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: a
Explanation: The stages in the pipelining should get completed within one cycle to increase the
speed of performance.
5. In pipelining the task which requires the least time is performed first.
a) True
b) False
View Answer
Answer: b
Explanation: This is done to avoid starvation of the longer task.
6. If a unit completes its task before the allotted time period, then
a) It’ll perform some other task in the remaining time
b) Its time gets reallocated to different task
c) It’ll remain idle for the remaining time
View Answer
Answer: c
Explanation: None.
7. To increase the speed of memory access in pipelining, we make use of _______
a) Special memory locations
b) Special purpose registers
c) Cache
d) Buffers
View Answer
Answer: c
Explanation: By using the cache we can reduce the speed of memory access by a factor of 10.
8. The periods of time when the unit is idle is called as _____
a) Stalls
b) Bubbles
c) Hazards
d) Both Stalls and Bubbles
View Answer

Answer: d
Explanation: The stalls are a type of hazards that affect a pipelined system.
9. The contention for the usage of a hardware device is called as ______
a) Structural hazard
b) Stalk
c) Deadlock
View Answer
Answer: a
Explanation: None.
10. The situation where in the data of operands are not available is called ______
a) Data hazard
b) Stock
c) Deadlock
d) Structural hazard
View Answer
Answer: a
Explanation: Data hazards are generally caused when the data is not ready on the destination side.

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