International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.

1. Trends in VLSI Circuit in 2020
International Journal of VLSI design &
Communication Systems (VLSICS)
ISSN : 0976 - 1357 (Online); 0976 - 1527(print)
http://airccse.org/journal/vlsi/vlsics.html

2. EFFICIENT ABSOLUTE DIFFERENCE CIRCUIT FOR SAD COMPUTATION ON
FPGA
Jaya Koshta, Kavita Khare and M.K Gupta Maulana Azad
National Institute of Technology, Bhopal
ABSTRACT
Video Compression is very essential to meet the technological demands such as low power, less
memory and fast transfer rate for different range of devices and for various multimedia
applications. Video compression is primarily achieved by Motion Estimation (ME) process in
any video encoder which contributes to significant compression gain.Sum of Absolute
Difference (SAD) is used as distortion metric in ME process.In this paper, efficient Absolute
Difference(AD)circuit is proposed which uses Brent Kung Adder(BKA) and a comparator based
on modified 1’s complement principle and conditional sum adder scheme. Results shows that
proposed architecture reduces delay by 15% and number of slice LUTs by 42 % as compared to
conventional architecture. Simulation and synthesis are done on Xilinx ISE 14.2 using Virtex 7
FPGA.
KEYWORDS
HEVC, motion estimation, sum of absolute difference, parallel prefix adders, Brent Kung Adder.
Full Text: http://aircconline.com/vlsics/V10N2/10219vlsi01.pdf
REFERENCES:
[1] G. J. Sullivan, J.-R. Ohm, W.-J. Han, and T. Wiegand, “Overview of the high efficiency
video coding (HEVC)standard,” IEEE Trans. Circuits Syst. Video Technol., vol.22, no. 12, pp.
1649-1668, December 2012.
[2] I. Richardson, “HEVC: An introduction to high efficiency video coding,” 2001,
https://www.vcodex.com/h265.html
[3] N. Purnachand, L. N. Alves, and A. Navarro, “Fast Motion Estimation Algorithm for
HEVC”, IEEE International Conference on Consumer Electronics-Berlin (ICCE-Berlin),
September 2012.
[4] S.Wong, B. Stougie, and S. Cotofana, “Alternatives in FPGA-based SAD Implementations,”
in IEEE International Conference on Field-Programmable Technology (FPT),IEEE, 2002, pp.
449–452.

3. [5] S. Vassiliadis, E. A. Hakkennes, J. S. S. M. Wong, and G.G.Pechanek, “The Sum-
AbsoluteDifference Motion Estimation Accelerator,” in Euromicro Conference, 1998.
Proceedings, 24th. IEEE, 1998, pp. 559–566.
[6] Ahmed Medhat, Ahmed Shalaby, Mohammed S. Sayed, Maha Elsabrouty and Farhad
Mehdipour. “A Highly Parallel SAD Architecture for Motion Estimation in HEVC Encoder”,
Circuits and Systems (APCCAS), IEEE Asia Pacific Conference, 280 - 283, 2014.
[7] Stefania Perri , Paolo Zicari , Pasquale Corsonello, “Efficient Absolute Difference Circuits in
Virtex5 FPGAs”, IEEE, 2010.
[8] Martin Kumm, Marco Kleinlein and Peter Zipf, “Efficient Sum of Absolute Difference
Computation on FPGAs”,26thInternational Conference on Field Programmable Logic and
Applications.
[9] Joaquin Olivares, Ignacio Benavides and et.al., “Minimum Sum of Absolute Differences
implementation in a single FPGA device”, Dept. of Electro-technics and Electronics, University
of Cordoba, Spain.
[10] P.Jayakrishnan and Harish. M. Kittur, “Pipelined Arch.for Motion Estimation in HEVC
Video Coding”, Indian Journal of Science and Tech,August 2016.
[11] D. V Manjunatha, Pradeep Kumar and R. Karthik, “FPGA Implementation of Sum of
Absolute Difference (SAD) for video applications”, ARPN Journal of Engineering and Applied
Sciences, Vol. 12, No. 24, December 2017
[12] Geeta Rani and Sachin Kumar, “Delay analysis of parallel-prefix adders”, International
Journal of Science and Research (IJSR), 3(6):2339-2342, 2014.
[13] Nurdiani Zamhari, Peter Voon, Kuryati Kipli, Kho Lee Chin, Maimun Huja
Husin,“Comparison of Parallel Prefix Adder (PPA)”, Proceedings of the World Congress on
Engineering 2012,Vol II.
[14] R. P Brent & H. T. Kung, “A Regular Layout for Parallel Adders”, IEEE Trans. Computers,
Vol. C31, pp 260-264, 1982.
[15] Shun-Wen Cheng, “A High-Speed Magnitude Comparator with Small Transistor Count”, in
Proceedings of IEEE internationalconference ICECS, 1168 - 1171 Vol.3, Dec 2003.
[16] J.Sklansky, “Conditional-Sum Addition Logic,” IRE Transactions on Electronic Computers,
Vol. EC9, No. 2, pp. 226-231, June,1960
[17] S. Rehman; R. Young;C. Chatwin;P. Birch, “An FPGA Based Generic Framework for High
Speed Sum of Absolute Difference Implementation”, Europ. Jour Scient. Res., vol.33, no.1,
2009.

4. [18] Manjunatha, D. V., and G. Sainarayanan. “Low-Power Sum of Absolute Difference
Architecture for Video Coding”, Emerging Research in Electronics, Computer Science and
Technology. Springer India, 2014. 335-341.
[19] LiYufei，Feng Xiubo and Wang Q in, “A High-Performance Low Cost SAD Architecture
for Video Coding”, IEEE Transactions on Consumer Electronics, pp. 535-541, Vol. 53, No. 2,
May 2007.
[20] Jarno, Vanne, Eero Aho, Timo D. Hamalainen and Kimmo Kuusilinna, “A High-
Performance Sum of Absolute Difference Implementation Motion Estimation”, IEEE
Transactions on Circuits and Systems for Video Technology, pp. 876-883, Vol. 16, No. 7, 2006.
[21] Elhamzi W., Dubois J., Miteran J “An efficient low-cost FPGA implementation of a
configurable motion estimation for H.264 video coding”, Springer Journal of Real-Time
Processing,Vol:9, No:1, pp. 19–30,2014.
[22] Moorthy T., Ye A, “A scalable architecture for variable block size motion estimation on
fieldprogrammable gate arrays” , IEEE Canadian Conference of Electrical and Computer
Engineering (CCECE),Niagara Falls, May, pp.1303–1308,2008.
[23] Davis P., Sangeetha M. ,“Implementation of Motion Estimation Algorithm for
H.265/HEVC”, International Journal of Advanced Research in Electrical, Electronics and
Instrumentation Engineering. Vol:3,No:3, pp. 122–126,2014.

5. FPGA IMPLEMENTATION OF HUANG HILBERT TRANSFORM FOR
CLASSIFICATION OF EPILEPTIC SEIZURES USING ARTIFICIAL NEURAL
NETWORK
G.Deepika1
and K.S.Rao2
1
Research scholar at JNTU,Hyderabad , Asso.Prof at RRS college of Engg,
2
Director & Professor in ECE Dept,Anurag group of Institutions, Hyderabad
ABSTRACT
The most common brain disorders due to abnormal burst of electrical discharges are termed as
Epileptic seizures. This work proposes an efficient approach to extract the features of epileptic
seizures by decomposing EEG into band limited signals termed as IMF’s by empirical
decomposition EMD. Huang Hilbert Transform is applied on these IMF’s for calculating
Instantaneous frequencies and are classified using artificial neural network trained by Back
propagation algorithm. The results indicate an accuracy of 97.87%. The algorithm is
implemented using Verilog HDL on Zynq 7000 family FPGA evaluation board using Xilinx
vivado 2015.2 version.
KEYWORDS
EEG, IMF,EMD
Full Text: http://aircconline.com/vlsics/V10N3/10319vlsi02.pdf
REFERENCES
[1] J. Gotman., “Automatic recognition of epileptic seizures in the EEG,” Clinical
Neurophysiology, vol. 54, pp. 530–540, 1982
[2] J.Gotman., “Automatic seizure detection: improvements and evaluation,” Clinical
Neurophysiology, vol. 76, pp. 317–324, 1990
[3] N.E. Huang, Z. Shen, S.R. Long, M.L. Wu, H.H. Shih,Q. Zheng, N.C. Yen, C.C. Tung, and
H.H. Liu, “TheEmpirical Mode Decomposition and Hilbert Spectrumfor Nonlinear and
Nonstationary Time Series Analysis,” Proc. Roy. Soc., vol. 454, pp. 903 – 995, 1998.
[4] Y.U. Khan, J. Gotman, “Electroencephalogram Wavelet based automatic seizure detection
intra cerebral”, Clinical Neurophysiology, vol. 114, pp. 899-908, 2003
[5] Güler NF, Übeyli ED, Güler.”Recurrent neural networks employing Lyapunov xponents for
EEG signal classification”,Expert Syst Appl. 2005; 29(3):506-14

6. [6] Varun Bajaj, Ram Bilas Pachori “Epileptic Seizure Detection Based on the Instantaneous
Area of Analytic Intrinsic Mode Functions of EEG Signals,” Biomed Eng Lett, vol. 3, pp. 17-21,
2013
[7] EEG time time series (epilepticdata)(2005,Nov.) [Online],
http://www.meb.unibonn.de/epileptologie/science/physik/eegdata.html
[8] Hedi Khammari , Ashraf Anwar, “A Spectral Based Forecasting Tool of Epileptic Seizures ”
IJCSI International.Journal of Computer Science Issues, Vol. 9, Issue 3, No 3, May 2012
[9] Rami J Oweis and Enas W Abdulhay., “Seizure classification in EEG signals utilizing
Hilbert- Huang transform” BioMedical Engineering OnLine 2011, 10:38
[10] lajos losonczi, lászló bakó, sándor-tihamér ,Brassai and lászló-ferenc Márton., “Hilbert-
huang transform used for eeg signal analysis ,” The 6th edition of the Interdisciplinarity in
Engineering International Conference , “Petru Maior” University ofTîrgu Mure, Romania, 2012

7. DUTY CYCLE CORRECTOR USING PULSE WIDTH MODULATION
Meghana Patil1
, Dr. Kiran Bailey2
and Rajanikanth Anuvanahally3
1
Department of Electronics and Communication, BMSCE, Bengaluru, Karnataka,India
2
Department of Electronics and Communication, BMSCE, Bengaluru, Karnataka,India
3
Senior Member IEEE, Bengaluru, Karnataka, India
ABSTRACT
In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is
done with respect to clock signals. It uses the edges of the clock to sample the data. So, it
becomes very much necessary to see to it that the clock signals are properly received specially in
receiver circuits where data sampling is done, mainly in Double data rate(DDR) circuits. Due to
effects such as jitter, skew, interference, device mismatches etc., duty cycle gets affected. We
come up with duty cycle correctors that ensure 50% duty cycle of the clock signals. A duty cycle
corrector (DCC) with analog feedback is proposed and simulated in 45nm process technology
node. The duty cycle corrector operates for MHz frequency range covering the duty cycle from
35%-65%, with +/- 1.5% accuracy. The design is simple and the power consumption is 1.01mW.
KEYWORDS
DCC, Integrator, Control voltage generator, frequency range
Full Text: http://aircconline.com/vlsics/V10N3/10319vlsi01.pdf
REFERENCES
[1] Jayaprakash SR, Sujatha S. Hiremath,(2017) “Dual loop clock duty cycle corrector for high
speed serial interface”, IEEE, pp 935-939.
[2] Immanuel Raja, Gaurab Banerjee, Jacob A Abraham, (2016) “ A 0/1-3.5Ghz duty cycle
measurement and correction technique in 130nm CMOS”, IEEE transaction on VLSI, Vol. 24,
No.5, pp 1975-1983.
[3] Feng Lin, (2011) “All digital duty-cycle correction circuit design and its applications in high
performance DRAM”, IEEE.
[4] Yusong Qiu, Yun Zeng and Feng Zhang, (2014) “1-5Ghz duty-cycle corrector circuit with
wide correction range and high precision”, Electronics letters, Vol. 50, No.11, pp 792-794.
[5] Young Jae Min, Chan Hui Jeong, et.al.,(2012) “A 0.31-1 Ghz Fast corrected duty cycle
corrector with successive approximation register for DDR DRAM applications”, IEEE
transaction on VLSI, Vol. 20, No. 8, pp 1524-1528.

8. [6] Chan hui Jeong, Ammar Abdullah, (2016) “All digital duty cycle corrector with a wide duty
correction range for DRAM applications”, IEEE transaction on VLSI, Vol. 24, No.1, pp 363-
367.
[7] Poki Chen, Shi Wei Chen, Juan-shan Lai, (2007) “Low power wide range duty cycle
corrector based on pulse shrinking/stretching mechanism”, IEEE, pp 935-939.
[8] Behzad Razavi, :Design of analog CMOS integrated circuits”, McGraw Hill International
Edition.
[9] Ravi Mehta, Sumanthra set, et.al., (2012) “A programmable, Multi GHz, Wide range duty
cycle correction circuit in 45nm process”, IEEE, pp 257-260.
[10] Sotirios Tambouris, Texas Instruments Deutschland, (2009) “CMOS integrated circuit for
correction of duty cycle of clock signal”, US Patent 7586349.
[11] Chin – Wei Tsai, Yu – Lung Lo, Chia – Chen Chang, et.al., (2017) “ All digital duty cycle
corrector with synchronous and high accuracy output for double data rate synchronous dynamic
random access memory applications”, The Japan Society of Applied Physics, pp 04CF02-1 –
04CF02-6.
[12] Sharath Patil, S. B. Rudraswamy, (2009) “Duty cycle correction using negative feedback
loop”, MIXDES 16th International Conference on Mixed design of integrated circuits systems,
Poland, pp 424-426.
[13] Ji - Hoon Lim, Jun – Hyun Bae, et.al., (2016) “ A Delay- locked loop with a feedback edge
combiner of duty cycle corrector with 20-80% input duty cycle for SDRAMs”, IEEE transcation
on circuits and systems – II: express briefs, Vol. 63. No/ 2, pp 141-145.
[14] Kanak Agarwal, Robert Montoye, (2006) “ A duty cycle correction circuit for high
frequency clocks”, IEEE : Symposium on VLSI circuit digest of technical papers.

9. DESIGN AND IMPLEMENTATION OF COMBINED PIPELINING AND PARALLEL
PROCESSING ARCHITECTURE FOR FIR AND IIR FILTERS USING VHDL
Jacinta Potsangbam1
and Manoj Kumar2
1
M. Tech VLSI Design, Dept. of ECE, National Institute of Technology, Manipur, India
2
Assistant Professor, Dept. of ECE, National Institute of Technology, Manipur, India
ABSTRACT
Along with the advancement in VLSI (Very Large Scale Integration) technology, the
implementation of Finite impulse response (FIR) filters and Infinite impulse response (IIR)
filters with enhanced speed has become more demanding. This paper aims at designing and
implementing a combined pipelining and parallel processing architecture for FIR and IIR filter
using VHDL (Very High Speed Integrated Circuit Hardware Descriptive Language) to reduce
the power consumption and delay of the filter. The proposed architecture is compared with the
original FIR and IIR filter respectively in terms of speed, area, and power. Also, the proposed
architecture is compared with existing architectures in terms of delay. The implementation is
done by using VHDL codes. FIR and IIR filters structures are implemented at 1200 KHz clock
frequency. Synthesis and simulation have been accomplished on Artix-7 series FPGA, target
device (xc7a200tfbg676) (speed grade -1) using VIVADO 2016.3.
KEYWORDS
DSP, FIR, FPGA, IIR, MIMO.
Full Text: http://aircconline.com/vlsics/V10N4/10419vlsi01.pdf
REFERENCES
[1]. K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. New
York: Wiley, 1999.
[2]. S. M. Rabiul Islam, R. Sarker, S. Saha and A. F. M. Nokib Uddin, “Design of a
Programmable digital IIR filter based on FPGA” 2012 International Conference on Informatics,
Electronics & Vision (ICIEV), Dhaka, pp. 716-72, 2012.
[3]. Suresh Gawande and SnehaBhujbal “High Speed IIR Notch Filter Using Pipelined
Technique” International Journal of Advanced Research in Electrical, Electronics and
Instrumentation Engineering Vol. 6, Issue 2, February 2017.
[4]. Yu-Chi Tsao and Ken Choi“Area-Efficient VLSI Implementation for Parallel Linear- Phase
FIR Digital Filters of Odd Length Based on Fast FIR Algorithm” IEEE Transactions On Circuits
And Systems—ii: Express Briefs, Vol. 59, No. 6, June 2012.

10. [5]. Ravinder Kaur and Ashish Raman “Design and Implementation of High Speed IIR and FIR
Filter using Pipelining”
[6]. B. K. Mohanty and P. K. Meher, "A High-Performance FIR Filter Architecture for Fixed and
Reconfigurable Applications," IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, vol. 24, no. 2, pp. 444-452, Feb. 2016.
[7]. https://en.wikipedia.org/wiki/Infinite_impulse_responsepage was last edited on 17 January
2019, at 20:29 (UTC). International Journal of VLSI design & Communication Systems
(VLSICS) Vol 10, No 4, August 2019 16
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[9]. S. Khorbotly, J. E. Carletta and R. J. Veillette, “A methodology for implementing pipelined
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Tullahoma, TN, 2009, pp. 280-284, 2009.
[10]. Keshab K. Parhi and David G. Messerschmitt, “Pipeline Interleaving and Parallelism in
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[15]. KanuPriya and Rajesh Mehra “Area Efficient Design of Fir Filter using Symmetric
Structure” International Journal of Advanced Research in Computer and Communication
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Vol.7, No.5/6, December 2016.

11. [17]. Saranya R, Pradeep C, Neena Baby and R Radhakrishnan “FPGA Synthesis of
Reconfigurable Modules for FIR Filter” International Journal of Reconfigurable and Embedded
Systems (IJRES) Vol. 4, No. 2, pp. 63-70, 2015.
[18]. Mahesh Kadam, KishorSawarkar and SudhakarMande “Comparative Analysis and
Efficient VLSI Implementation of FIR Filter” International Journal of Advanced Research in
Electrical, Electronics and Instrumentation Engineering, Vol. 3, Issue 7, July 2014.
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12. DESIGN AND ANALYSIS OF A 32-BIT PIPELINED MIPS RISC PROCESSOR
P. Indira1
, M. Kamaraju2
and Ved Vyas Dwivedi3
1,3
Department of Electronics and Communication Engineering, CU Shah University, Wadhwan,
Gujarat, India
2
Department of Electronics and Communication Engineering,Gudlavalleru Engineering College,
JNT University, Kakinada, Andhra Pradesh, India
ABSTRACT
Pipelining is a technique that exploits parallelism, among the instructions in a sequential
instruction stream to get increased throughput, and it lessens the total time to complete the work.
. The major objective of this architecture is to design a low power high performance structure
which fulfils all the requirements of the design. The critical factors like power, frequency, area,
propagation delay are analysed using Spartan 3E XC3E 1600e device with Xilinx tool. In this
paper, the 32-bit MIPS RISC processor is used in 6-stage pipelining to optimize the critical
performance factors. The fundamental functional blocks of the processor include Input/Output
blocks, configurable logic blocks, Block RAM, and Digital clock Manager and each block
permits to connect to multiple sources for the routing. The Auxiliary units enhance the
performance of the processor. The comparative study elevates the designed model in terms of
Area, Power and Frequency. MATLAB2D/3D graphs represents the relationship among various
parameters of this pipelining. In this pipeline model, it consumes very less power (0.129 W),path
delay (11.180 ns) and low LUT utilization (421). Similarly, the proposed model achieves better
frequency increase (285.583 Mhz.), which obtained better results compared to other models.
KEYWORDS
MATLAB, SPARTAN3E, MIPS RISC processor, Xilinx, Digital Clock Manager
Full Text: http://aircconline.com/vlsics/V10N5/10519vlsi01.pdf
REFERENCES
[1] Rashid F. Olanrewaju, Fawwaj E Fajingbesi, S.B. Junaid, Ridzwan Alahudin, Farhat Anwar
& Bisma Rasool Pampori (2017) “Design and Implementation of a Five Stage Pipelining
Architecture Simulator for RiSC-16 Instruction Set”, Indian Journal of Science and Technology,
Vol. 10, No. 3, pp 1-9.
[2] Vijaykumar J, Nagaraju B, Swapna C & Ramanujappa T (2014 April) “Design and
Development of FGPA based Low Power pipelined 64-bit RISC processor with Double
precession Floating point Unit”, International Conference on Communication and Signal
processing.

13. [3] Saranya Krishnamurthy, Ramani Kannan, Erman Azwan Yahya & Kishore Bingi (2017) “
Design of FIR Filter using Novel pipelined Bypass Multiplier”,IEEE 3rd International
Symposium on Robotics and Manufacturing Automation, pp1-6.
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of 32-bit RISC Processor with pipelining. 2nd International Conference on Microelectronics”,
Computing & Communication Systems (MCCS-2017), at Bangalore.
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pipelined processor based on MIPS in Verilog HDL and implementation on FPGA
Virtex7”,International Journal of Applied Information Systems, Vol. 10, No. 9.
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Technique”, International journal of innovative research in Electrical, Electronics,
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Processor Using Low Power Pipelining”,International Conference on Computing,
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MIPS Architecture using Pre-Fetching Accelerator”,International Conference onElectrical
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