SlideShare a Scribd company logo
1 of 3
THATI RAHUL
#106, Room No: 17 Thanishka Mansion,
Ananda Nagar, Marathahalli,Bangalore,
Karnataka, India, 560037. [E]: rahulthati21@gmail.com
DOB: 21-08-1992 [M]: 9036308279
Career Objective:
Seeking a position to utilize my skills and abilities in an esteemed firm that offers professional
growth while being resourceful, innovative and accomplish my goals by achieving company’s
targets and head towards personal growth and development.
Educational Qualifications:
S. Degree Year of Branch University/Board Aggregate
No study
1. Master of 2013-2015 VLSI Design NITK Surathkal 9(CGPA)
Technology
2. Bachelor of 2009-2013 Electronics Osmania University 83.65%
Engineering &Communication
Engineering.
3. Intermediate 2007-2009 M.P.C Board of 96%
Intermediate
4. S.S.C 2006-2007 - SSC 86%
Areas of Interest
Technical: Digital electronics, Analog IC design, Digital IC design and Computer
architecture. Programming languages: Verilog, C, Embedded C, Perl (Basics).
Tools: LT-Spice, NG Spice, Magic, Model Sim.
Work Experience
I. July 2015 – present:
Working as Validation Engineer in Infineon Technologies India Pvt. Ltd, Bangalore
Projects:
 Validation of I2C and MSC modules. 
 Working on randomization framework to automate validation of IP’s. 

II. July 2014 – June 2015 
Worked as an intern at Infineon Technologies India Pvt. Ltd Bangalore.
Paper:
IEEE: “Novel architecture for emulation of sensor protocols for compliance checking using
Generic Timer Module” at “International Conference on Industrial Instrumentation and
Control 2015, Pune”. Paper ID: 10.1109/IIC.2015.7150930.
Projects:
 Methodology for the development of a framework for emulating the Sensor Protocols
(Single Edge Nibble Transmission (SENT), Peripheral Sensor Interface (PSI5) and
Peripheral Sensor Interface with Serial PHY Connection (PSI5-S)) using Generic Timer
Module (GTM) in Automotive Microcontrollers. 

 Apart from the project work, validation of Input Output Module (IOM) using Generic
Timer Module (GTM) is done. 
Academic Projects
I. 32 bit single cycle processor:
Aim of the project is to implement a 32 bit single cycle RISC machine with simple
load/store architecture. Program code is executed using five instruction cycles, they are
instruction fetch (IF), instruction decode (ID), instruction execute (IE), memory access
(MEM) and write back (WB). These five instructions are executed in a single clock cycle.
II. Generation of temperature independent reference voltage:
The objective of the project is to generate the temperature independent voltage from 0
to 125 degree centigrade by using both positive and negative temperature coefficient
devices. It is implemented in LT-Spice.
III. Floating point ALU:
A floating-point unit is a part of a computer system specially designed to carry out
operation on floating point number by which dynamic range is increased. It is
implemented in Verilog. Typical operations are addition, subtraction, multiplication,
division, square root, bit shifting.
IV. 8 bit ripple carry adder:
Objective of the project is to design the layout of adder circuit that has minimum delay.
It is designed in Magic tool and simulated in NG Spice and IR-Sim. For this
implementation, we designed our own standard cells and used them to design the
complete circuit.
V. LEE’S Algorithm:
Lee’s algorithm is one of the solutions for maze routing. It gives the detailed routing of
the channels on the grid from source to target with minimum wire length and minimum
number of vias. It is implemented using PERL.
VI. Digital Signal Processing of Professional Audio Effects:
The main aim of this project is to produce different audio effects, by using mat lab
software. In this we implement delay based effects, modulator based effects, filtering
based effects.
VII. Unmanned Railway Gate:
A microcontroller based project, it is used to control a railway gate without any human
involvement. Sensors are used to sense the train, light emitting diodes are used as traffic
light indicators and motors to open and close the gate.
Co-Curricular Activities:
I. Received “Best Intern” award in Post Silicon Validation department during internship at
Infineon Technologies India Pvt. Ltd.
II. Presented a poster on “Design of VSAT based systems for High Bandwidth Applications”
at Osmania University.
Extra-Curricular Activities:
I. Organized an event “ROBOTICS” in Acumen 2013 a National Level Technical Symposium at
Vasavi College of Engineering.
II. Volunteered an event “ROBOTICS” in Acumen 2012 a National Level Technical Symposium
at Vasavi College of Engineering
III. Volunteered for Euphoria a cultural fest held in Vasavi college of Engineering.
IV. Worked in a team as a volunteer for an NGO called BHUMI.
V. Participated in a Cricket tournament conducted by Vasavi College of Engineering.
VI. Won gold medals in sports conducted during school days.
Declaration
I hereby declare that the above mentioned information is correct to the best of my
knowledge.
Place: Bangalore
Thati Rahul

More Related Content

What's hot (20)

abhi
abhiabhi
abhi
 
dinesh_5
dinesh_5dinesh_5
dinesh_5
 
venkat re (1) (1)
venkat re (1) (1)venkat re (1) (1)
venkat re (1) (1)
 
new resume
new resumenew resume
new resume
 
GOUTTHAM
GOUTTHAMGOUTTHAM
GOUTTHAM
 
Suraj Resume
Suraj ResumeSuraj Resume
Suraj Resume
 
MasterCV
MasterCVMasterCV
MasterCV
 
AhmedYaqout C.V
AhmedYaqout C.V AhmedYaqout C.V
AhmedYaqout C.V
 
Abhishek_cv
Abhishek_cvAbhishek_cv
Abhishek_cv
 
My curriculum vitae
My curriculum vitaeMy curriculum vitae
My curriculum vitae
 
Maintenance . Abdullatif Mahmoud Hegazy . CV
Maintenance . Abdullatif Mahmoud Hegazy . CVMaintenance . Abdullatif Mahmoud Hegazy . CV
Maintenance . Abdullatif Mahmoud Hegazy . CV
 
Mecatronic
MecatronicMecatronic
Mecatronic
 
CURRICULUM VITAE
CURRICULUM VITAECURRICULUM VITAE
CURRICULUM VITAE
 
Rizwan Jamil_Resume_MechatronicsEngineer_UET_Lahore
Rizwan Jamil_Resume_MechatronicsEngineer_UET_LahoreRizwan Jamil_Resume_MechatronicsEngineer_UET_Lahore
Rizwan Jamil_Resume_MechatronicsEngineer_UET_Lahore
 
Soumen resume
Soumen resumeSoumen resume
Soumen resume
 
Jayesh_Electronics_Hardware_Tester...
Jayesh_Electronics_Hardware_Tester...Jayesh_Electronics_Hardware_Tester...
Jayesh_Electronics_Hardware_Tester...
 
jayesh_cv
jayesh_cvjayesh_cv
jayesh_cv
 
Resume- Akshit Jain
Resume- Akshit JainResume- Akshit Jain
Resume- Akshit Jain
 
Resume ankit lohiya_2014_fresher_ece
Resume ankit lohiya_2014_fresher_eceResume ankit lohiya_2014_fresher_ece
Resume ankit lohiya_2014_fresher_ece
 
2 Page CV
2 Page CV2 Page CV
2 Page CV
 

Viewers also liked

Manutenoindustrial 140520120534-phpapp01
Manutenoindustrial 140520120534-phpapp01Manutenoindustrial 140520120534-phpapp01
Manutenoindustrial 140520120534-phpapp01Jeferson S. Souza
 
jComply grc_platform_v1.0
jComply grc_platform_v1.0jComply grc_platform_v1.0
jComply grc_platform_v1.0jComply
 
Behavior Driven Development (BDD)
Behavior Driven Development (BDD)Behavior Driven Development (BDD)
Behavior Driven Development (BDD)Ajay Danait
 
Introduction to DataStax Enterprise Advanced Replication with Apache Cassandra
Introduction to DataStax Enterprise Advanced Replication with Apache CassandraIntroduction to DataStax Enterprise Advanced Replication with Apache Cassandra
Introduction to DataStax Enterprise Advanced Replication with Apache CassandraDataStax Academy
 
Introduction to DataStax Enterprise Graph Database
Introduction to DataStax Enterprise Graph DatabaseIntroduction to DataStax Enterprise Graph Database
Introduction to DataStax Enterprise Graph DatabaseDataStax Academy
 
PENTAKSIRAN MATEMATIK YANG DILAKSANAKAN DI SEKOLAH. ( PBS , PT3 , DAN KBAT )
 PENTAKSIRAN MATEMATIK YANG DILAKSANAKAN DI SEKOLAH. ( PBS , PT3 , DAN KBAT ) PENTAKSIRAN MATEMATIK YANG DILAKSANAKAN DI SEKOLAH. ( PBS , PT3 , DAN KBAT )
PENTAKSIRAN MATEMATIK YANG DILAKSANAKAN DI SEKOLAH. ( PBS , PT3 , DAN KBAT )Ameer Chann
 

Viewers also liked (15)

Be like water
Be like waterBe like water
Be like water
 
Manutenoindustrial 140520120534-phpapp01
Manutenoindustrial 140520120534-phpapp01Manutenoindustrial 140520120534-phpapp01
Manutenoindustrial 140520120534-phpapp01
 
FAMILY MEMORIES
FAMILY MEMORIESFAMILY MEMORIES
FAMILY MEMORIES
 
jComply grc_platform_v1.0
jComply grc_platform_v1.0jComply grc_platform_v1.0
jComply grc_platform_v1.0
 
Jose ramirez trabajo_individual
Jose ramirez trabajo_individualJose ramirez trabajo_individual
Jose ramirez trabajo_individual
 
Session 18 Søren Troels Berg
Session 18 Søren Troels BergSession 18 Søren Troels Berg
Session 18 Søren Troels Berg
 
Ibm vs Microsoft
Ibm vs MicrosoftIbm vs Microsoft
Ibm vs Microsoft
 
Behavior Driven Development (BDD)
Behavior Driven Development (BDD)Behavior Driven Development (BDD)
Behavior Driven Development (BDD)
 
Toolbox fuzzy logic
Toolbox fuzzy logicToolbox fuzzy logic
Toolbox fuzzy logic
 
Introduction to DataStax Enterprise Advanced Replication with Apache Cassandra
Introduction to DataStax Enterprise Advanced Replication with Apache CassandraIntroduction to DataStax Enterprise Advanced Replication with Apache Cassandra
Introduction to DataStax Enterprise Advanced Replication with Apache Cassandra
 
Introduction to DataStax Enterprise Graph Database
Introduction to DataStax Enterprise Graph DatabaseIntroduction to DataStax Enterprise Graph Database
Introduction to DataStax Enterprise Graph Database
 
KUALITI GURU
KUALITI GURUKUALITI GURU
KUALITI GURU
 
Practica 3
Practica   3Practica   3
Practica 3
 
Practica 3
Practica   3Practica   3
Practica 3
 
PENTAKSIRAN MATEMATIK YANG DILAKSANAKAN DI SEKOLAH. ( PBS , PT3 , DAN KBAT )
 PENTAKSIRAN MATEMATIK YANG DILAKSANAKAN DI SEKOLAH. ( PBS , PT3 , DAN KBAT ) PENTAKSIRAN MATEMATIK YANG DILAKSANAKAN DI SEKOLAH. ( PBS , PT3 , DAN KBAT )
PENTAKSIRAN MATEMATIK YANG DILAKSANAKAN DI SEKOLAH. ( PBS , PT3 , DAN KBAT )
 

Similar to Rahul_Thati (20)

resume
resumeresume
resume
 
KAMESHPRABU M_Resume
KAMESHPRABU M_ResumeKAMESHPRABU M_Resume
KAMESHPRABU M_Resume
 
Shantanu telharkar july 2015
Shantanu telharkar  july 2015Shantanu telharkar  july 2015
Shantanu telharkar july 2015
 
New resume 2years exp
New resume 2years expNew resume 2years exp
New resume 2years exp
 
VINOD_KAMALAPUR_RESUME (1)
VINOD_KAMALAPUR_RESUME (1)VINOD_KAMALAPUR_RESUME (1)
VINOD_KAMALAPUR_RESUME (1)
 
ResumeLinkedIn
ResumeLinkedInResumeLinkedIn
ResumeLinkedIn
 
Resume
ResumeResume
Resume
 
Updated resume
Updated resumeUpdated resume
Updated resume
 
curriculum-vitae_sampath_kumar_2
curriculum-vitae_sampath_kumar_2curriculum-vitae_sampath_kumar_2
curriculum-vitae_sampath_kumar_2
 
Fresher_IIT Kgp-CV
Fresher_IIT Kgp-CVFresher_IIT Kgp-CV
Fresher_IIT Kgp-CV
 
Resume_MS1
Resume_MS1Resume_MS1
Resume_MS1
 
GP_Kashyap_Resume
GP_Kashyap_ResumeGP_Kashyap_Resume
GP_Kashyap_Resume
 
JitendraResume_22022016
JitendraResume_22022016JitendraResume_22022016
JitendraResume_22022016
 
Rachit_HMI_Development_resume
Rachit_HMI_Development_resumeRachit_HMI_Development_resume
Rachit_HMI_Development_resume
 
Deepak Kumar Gautam
Deepak Kumar GautamDeepak Kumar Gautam
Deepak Kumar Gautam
 
Resume_Apple1
Resume_Apple1Resume_Apple1
Resume_Apple1
 
Chetan portfolio
Chetan portfolioChetan portfolio
Chetan portfolio
 
Chaithra
ChaithraChaithra
Chaithra
 
Balashankar
BalashankarBalashankar
Balashankar
 
Dipak_Desai_Resume
Dipak_Desai_ResumeDipak_Desai_Resume
Dipak_Desai_Resume
 

Rahul_Thati

  • 1. THATI RAHUL #106, Room No: 17 Thanishka Mansion, Ananda Nagar, Marathahalli,Bangalore, Karnataka, India, 560037. [E]: rahulthati21@gmail.com DOB: 21-08-1992 [M]: 9036308279 Career Objective: Seeking a position to utilize my skills and abilities in an esteemed firm that offers professional growth while being resourceful, innovative and accomplish my goals by achieving company’s targets and head towards personal growth and development. Educational Qualifications: S. Degree Year of Branch University/Board Aggregate No study 1. Master of 2013-2015 VLSI Design NITK Surathkal 9(CGPA) Technology 2. Bachelor of 2009-2013 Electronics Osmania University 83.65% Engineering &Communication Engineering. 3. Intermediate 2007-2009 M.P.C Board of 96% Intermediate 4. S.S.C 2006-2007 - SSC 86% Areas of Interest Technical: Digital electronics, Analog IC design, Digital IC design and Computer architecture. Programming languages: Verilog, C, Embedded C, Perl (Basics). Tools: LT-Spice, NG Spice, Magic, Model Sim. Work Experience I. July 2015 – present: Working as Validation Engineer in Infineon Technologies India Pvt. Ltd, Bangalore Projects:  Validation of I2C and MSC modules.   Working on randomization framework to automate validation of IP’s.   II. July 2014 – June 2015  Worked as an intern at Infineon Technologies India Pvt. Ltd Bangalore. Paper: IEEE: “Novel architecture for emulation of sensor protocols for compliance checking using Generic Timer Module” at “International Conference on Industrial Instrumentation and Control 2015, Pune”. Paper ID: 10.1109/IIC.2015.7150930.
  • 2. Projects:  Methodology for the development of a framework for emulating the Sensor Protocols (Single Edge Nibble Transmission (SENT), Peripheral Sensor Interface (PSI5) and Peripheral Sensor Interface with Serial PHY Connection (PSI5-S)) using Generic Timer Module (GTM) in Automotive Microcontrollers.    Apart from the project work, validation of Input Output Module (IOM) using Generic Timer Module (GTM) is done.  Academic Projects I. 32 bit single cycle processor: Aim of the project is to implement a 32 bit single cycle RISC machine with simple load/store architecture. Program code is executed using five instruction cycles, they are instruction fetch (IF), instruction decode (ID), instruction execute (IE), memory access (MEM) and write back (WB). These five instructions are executed in a single clock cycle. II. Generation of temperature independent reference voltage: The objective of the project is to generate the temperature independent voltage from 0 to 125 degree centigrade by using both positive and negative temperature coefficient devices. It is implemented in LT-Spice. III. Floating point ALU: A floating-point unit is a part of a computer system specially designed to carry out operation on floating point number by which dynamic range is increased. It is implemented in Verilog. Typical operations are addition, subtraction, multiplication, division, square root, bit shifting. IV. 8 bit ripple carry adder: Objective of the project is to design the layout of adder circuit that has minimum delay. It is designed in Magic tool and simulated in NG Spice and IR-Sim. For this implementation, we designed our own standard cells and used them to design the complete circuit. V. LEE’S Algorithm: Lee’s algorithm is one of the solutions for maze routing. It gives the detailed routing of the channels on the grid from source to target with minimum wire length and minimum number of vias. It is implemented using PERL. VI. Digital Signal Processing of Professional Audio Effects: The main aim of this project is to produce different audio effects, by using mat lab software. In this we implement delay based effects, modulator based effects, filtering based effects. VII. Unmanned Railway Gate: A microcontroller based project, it is used to control a railway gate without any human involvement. Sensors are used to sense the train, light emitting diodes are used as traffic light indicators and motors to open and close the gate.
  • 3. Co-Curricular Activities: I. Received “Best Intern” award in Post Silicon Validation department during internship at Infineon Technologies India Pvt. Ltd. II. Presented a poster on “Design of VSAT based systems for High Bandwidth Applications” at Osmania University. Extra-Curricular Activities: I. Organized an event “ROBOTICS” in Acumen 2013 a National Level Technical Symposium at Vasavi College of Engineering. II. Volunteered an event “ROBOTICS” in Acumen 2012 a National Level Technical Symposium at Vasavi College of Engineering III. Volunteered for Euphoria a cultural fest held in Vasavi college of Engineering. IV. Worked in a team as a volunteer for an NGO called BHUMI. V. Participated in a Cricket tournament conducted by Vasavi College of Engineering. VI. Won gold medals in sports conducted during school days. Declaration I hereby declare that the above mentioned information is correct to the best of my knowledge. Place: Bangalore Thati Rahul