INTERNAL Structure of 8086 , MICROPROCESSOR AND ITS TWO UNITS

1. TOPIC
The Internal Architecture Of 8086 And Its
Two Units.

2. GROUP MEMBER
NAME ID
MD. HASNAT SHOHEB 152-15-5813
AWOLAD HOSSEN 152-15-5597
MD. MAHADI HASAN MOZUMDER 152-15-5797
MD. ROBEL MIA 152-15-5538
ROKYBUL RAYHAN CHODHURY 152-15-5597

3. MD. HASNAT SHOHEB
152-15-5813

4. INTRODUCTION
• The 8086 ("eighty eighty-six", also called
iAPX 86) is a 16-bitmicroprocessor chip
designed by Intel between early 1976
and mid-1978, when it was released.
• Predecessor : (Intel 8080)
• Successor : 80186 and 80286 (both
of which were introduced in early
1982)

5. INTERNAL ARCHITECTURE
• 8086 has two blocks BIU and
EU.
• BIU contains Instruction
queue, Segment registers,
Instruction pointer, Address
adder, the Address Summing
block (Σ)
• EU contains Control circuitry,
Instruction decoder, ALU,
Pointer and Index register,
Flag register.

6. Bus Interface Unit (BIU)
• The bus control logic of the BIU
generates all the bus control signals
such as read and write signals for
memory and I/O.
• This unit handles all transfer of data
and addresses on the buses for the
EU(execution unit).

7. Bus Interface Unit (BIU)
The function of BIU is to :
• Fetch the instruction or data from memory.
• Write the data to memory.
• Write the data to the port.
• Read data from the port.

8. Execution Unit (EU)
• Execution Unit also called a
functional unit
• An execution unit is a part of the
central processing unit (CPU) that
performs the operations and
calculations as instructed by the
computer program

9. Execution Unit (EU)
The functions of execution unit are :
• To tell BIU where to fetch the instructions or
data from.
• To decode the instructions.
• To execute the instructions.

10. Features of 8086 Microprocessor
• It was the first 16-bit microprocessor.
• This microprocessor had major improvement over the execution
speed of 8085.
• It is available as 40-pin Dual-Inline-Package (DIP).
• It is available in three versions:
– 8086 (5 MHz)
– 8086-2 (8 MHz)
– 8086-1 (10 MHz)
• It consists of 29,000 transistors.

11. Features of 8086 Microprocessor
• 8086 is designed to operate in two modes, Minimum and Maximum.
• It can pre-fetches up to 6 instruction bytes from memory and queues them
in order to speed up instruction execution.
• It requires +5V power supply.
• A 40 pin dual in line package.
• Address ranges from 00000H to FFFFFH

12. AWOLAD HOSSAN
152-15-5597

13. What is general purpose registers
• We have discussed general purpose registers as
being discrete memory locations within the CPU
used to hold temporary data and instructions.
However there are also special purpose
registers. A special purpose register is one that
has a specific control or data handling task to
carry out.

14. Type Of General Purpose
Registers
• AX - the accumulator register
Arithmetic, logic and data transfer
Multiplication & Division
Input & Output
• BX - the base address register
BX register is an address register.
It usually contain a data pointer used for based, based indexed

15. Type Of General Purpose Registers
• CX - the count register
Iterative code segments using the LOOP instruction
Repetitive operations on strings with the REP command
• DX - the data register
Data register can be used as a port number in I/O operations. It
is also used in multiplication and division.

16. Pointers and index registers
The pointers contain within the particular segments. The pointers
IP, BP, SP usually contain offsets within the code, data and stack
segments respectively
• SI - source index register
• DI - destination index register
• BP – base pointer:
• SP - stack pointer:

17. Pointer And Index Registers
• Used to keep offset addresses.
• Used in various forms of memory addressing.
• In the case of SP and BP the default reference to form a physical
address is the Stack Segment (SS-will be discussed under the
BIU)
• The index registers (SI & DI) and the BX generally default to the
Data segment register (DS).

18. MD.MAHADI HASAN
MAZUMDER
ID:152-15-5797

19. Segment registers
• In 8086/88 the processors have 4 segments registers
• Code Segment register (CS), Data Segment register (DS), Extra
Segment register (ES) and Stack Segment (SS) register.
• All are 16 bit registers.
• Each of the Segment registers store the upper 16 bit address of
the starting address of the corresponding segments

20. Segmented Memory
• The memory in an 8086/88 based system is
organized as segmented memory.
• The CPU 8086 is able to address 1Mbyte of
memory.
• The Complete physically available memory may
be divided into a number of logical segments.
Physical Memory
1MB
00000
FFFFF

22. Function of segment register
• CS - points at the segment containing the
current program.
• DS - generally points at segment where
variables are defined.
• ES - extra segment register, it's up to a coder
to define its usage.
• SS - points at the segment containing the
stack.

23. Advantages of Segmented Memory Scheme
• Allows the memory capacity to be 1Mb
• Allows the placing of code,data and stack portions of the same
program in different parts
• Permits a program to be put into different area

24. Special purpose register
• IP - the instruction pointer:
1. Always points to next instruction to be executed
2. Offset address relative to CS
• IP register always works together with CS
segment register and it points to currently
executing instruction

26. MD. ROBEL MIA
ID: 152-15-5538

27. FLAG REGISTER
The Flags register is the status register in Intel 8086 microprocessor that contains the
current state of the processor. They are modified automatically by CPU after mathematical
operations, this allows to determine the type of the result, and to determine conditional to
transfer control to other parts of the program.
In EU the 8086 contains 16 bit Flag register. 9 of the 16 are active Flags and remaining 7 are
undefined.
=> 6 Flags indicates some conditions – Status or Conditional Flags
=> 3 Flags – Control Flags
 Category of FLAGS Registers: There are 2 types of FLAGS register
=> Status Flags or Conditional Flags
=> Control Flags

28. Conditional Flags: The conditional flags represent the result of last arithmetic or
logical instruction executed. Conditional flags are as follows —
=> Carry Flag (CF)
=> Parity Flag (PF)
=> Auxiliary Flag (AF)
=> Sign Flag (SF)
=> Overflow Flag (OF)
=> Zero Flag (ZF)
Control Flags: Control flags are set or reset deliberately to control the operations of
the execution unit. Control flags are as follows ---
=> Trap Flag (TP)
=> Interrupt Flag (IF)
=> Direction Flag (DF)

30.  Carry Flag: 1
AX = 1111 1111 1111 1111
BX = 1111 1111 1111 1111
------------------------------------------
1 1111 1111 1111 1110 = 1FFFEh
CF=1; there is a carry out of the MSB on addition
Parity Flag:
AL = 7F = 0111 1111
+1
---------------------------
1000 0000 = 80h
PF=1; all the low bits in the result are 0

31.  Auxiliary Flag:
1
AL = 7F = 0111 1111
+1
-------------------------------
1000 0000 = 80h
AF=1; there is a carry out of bit 3 into bit 4
Sign Flag:
AL = 7F = 0111 1111
+1
--------------------
1000 0000 = 80h
SF=1; bit seven is one (MSB is 1)

32. Overflow Flag:
AL = 7F = 0111 1111
+1
----------------------
1000 0000 = 80h
OF=1; the sign bit has changed
 Zero Flag:
AL = 7F = 0111 1111
+1
--------------------
1000 0000 = 80h
ZF=0; the result is not zero

33. Example: If register AL=7Fh and the instruction ADD AL, 1 is
executed then the following happen ---
AL = 7F = 0111 1111
+1
--------------------------------
1000 0000 = 80h
CF=0; there is no carry out of bit 7
PF=1; all the low bits in the result are 0
AF=1; there is a carry out of bit 3 into bit 4
SF=1; bit seven is one (MSB is 1)
OF=1; the sign bit has changed
ZF=0; the result is not zero

34. Trap Flag: Enables the trapping through an on-chip debugging
feature. If TF=1, the CPU automatically generates an internal interrupt
after each instruction, allowing a program to be inspected as it executes
instruction by instruction.
 Interrupt Flag: Controls the operation of the INTR (interrupt
request). If IF=1, the CPU will recognize external interrupt request.
That means INTR pin disabled. If IF=0, then INTR pin enabled. IF has
no effect on either non-maskable external or internally generated
interrupt.
 Direction Flag: This bit is specially for string instructions. If DF=1,
the string instruction will automatically decrement the pointer. If DF=0,
the string instruction will automatically increment the pointer.

35. ID:152-15-5597
ROKYBUL RAYHAN CHODHURY

36. PINS AND SIGNALS
• AD0-AD15 (Bidirectional)
• Address/Data bus
• Low order address bus; these are multiplexed with data.
• When AD lines are used to transmit memory address the
symbol A is used instead of AD, for example A0-A15.
• When data are transmitted over AD lines the symbol D is
used in place of AD, for example D0-D7, D8-D15 or D0-D15

37. MINIMUM / MAXIMUM
• MN/ MX -Pin 33 (Input)
• 8086 works in two modes:
– Minimum Mode
– Maximum Mode
• If MN/MX is high, it works in minimum
mode.
• If MN/MX is low, it works in maximum
mode.

38. RD (READ) (ACTIVE LOW)
• The signal is used for read
operation.
• It is an output signal.
• It is active when low.

39. TEST
• TEST input is tested by the ‘WAIT’ instruction.
• 8086 will enter a wait state after execution of the WAIT
instruction and will resume execution only when the TEST is
made low by an active hardware.
• This is used to synchronize an external activity to the
processor internal operation.
-Pin 23 (Input)

40. READY
-Pin 22 (Input)
• This is the acknowledgement from the slow device or
memory that they have completed the data transfer.
• The signal made available by the devices is
synchronized by the 8284A clock generator to provide
ready input to the 8086.
• The signal is active high.