Digital Electronics and Computer Language

Digital Electronics
• Number systems (Decimal, Binary, Octal and
Hexadecimal)
• One’s and two’s complements
• Binary codes (weighted and non-weighted codes)
• Boolean algebraic theorems
• Simplification of Boolean expressions
• Logic gates
• Implementation of Boolean expressions using logic gates
• Standard and canonical forms of Boolean expression,
POS and SOP forms
• Simplification of Boolean expressions using K-map
• Basics of Flip-flops and its applications.

• “There are 10 types of people in this
world, one who believe in God and
another who don’t.”

Introduction
• 4 types of signals
• 1—continuous time-continuous amplitude
signal
• 2 -- continuous time-discrete amplitude
signal(digital signal—binary signals)
• 3--- Discrete time-continuous amplitude
signal
• 4--- Discrete time-Discrete amplitude signal
•

Storey: Electrical & Electronic Systems © Pearson Education Limited 2004 OHT 9.‹#›
Difference between analogue and
Digital signals
• Analog signal more prone to noise
• Analog signal has complete information
• Digital signal can produce approximate
information.
• Processing tool for digital signal are available.
• Mathematical operations become simple

Number Systems and Binary
Arithmetic
• Most number systems are order dependent
• Decimal
123410 = (1  103) + (2  102) + (3  101) + (4  100)
• Binary
11012 = (1  23) + (1  22) + (0  21) + (1  20)
• Octal
1238 = (1  82) + (2  81) + (3  80)
• Hexadecimal
12316 = (1  162) + (2  161) + (3  160)
here we need 16 characters – 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F

Number conversion
– conversion Binary to decimal
• add up decimal equivalent of individual digits
Example –
Convert 110102 to decimal
110102 = (1  24) + (1  23) + (0  22) + (1  21) + (0  20)
= 16 + 8 + 0 + 2 + 0
= 2610

Decimal to Binary
• repeatedly divide by the base and remember the remainder
Example –
Convert 2610 to binary
Number Remainder
Starting point 26
 2 13 0
 2 6 1
 2 3 0
 2 1 1
 2 0 1
read number from this end
=11010

Other number system to Decimal
• Any number an-1an-2....a2a1a0 at base r may be
represented in decimal number system as
• (an-1an-2....a2a1a0 )r=
(an-1Xrn-1+an-2Xrn-2+...+ a2 Xr2+a1r1+a0Xr0)10

Decimal to other number system
• Any decimal number can be represented in other
number system by successively dividing the
decimal number by the base of the new number
system till quotient becomes zero. Remember the
remainder after each division and write them in
reverse order.
• Decimal number is represented using ten symbols-
--0,1,2,....9.
• Hexadecimal---0,1,2,....,9,A,B,C,D,E,F.
• Octal---0,1,2,...,6,7.

Among Octal, Hexadecimal and Binary
• 3 bit of binary are used to represent 1 Octal
symbol. (make triplets starting from right most
side)
• 4 bit of binary are used to represent 1
Hexadecimal symbol. (make quadruples
starting from right most side)
• OctalBinary Hexadecimal

Exercise
• (47)10=(?)2, (2351) 10=(?)16, (612) 10=(?)7
• (1101010) 2 =(?) 7, (101110) 2 =(?) 16,
(10011010) 2 =(?) 10
• (147) 7 =(?) 10, (278) 7 =(?) 16, (109) 7 =(?) 2
• (ABC) 16 =(?) 10, (1A0) 16 =(?) 2, (2F1) 16 =(?) 7

Number Representation: Negative
Numbers
1. Signed and Magnitude Representation
2. Signed 1’s Complement Representation
3. Signed 2’s Complement Representation
Sign Magnitude
1 negative number, 0 positive number

1’s complement
• 10 and 01
• That is
• 1’s complement of x=11001 (25) is calculated as—
• 11111
• -11001
• ------------
• 00110
• Or in other word replace 0 by 1 and 1 by 0.

1’s complement
• Or in other words
• 1’s complement of x is 2n-1-x;
• That is for 5 bit number on previous slide 1’s
complement is 25-1-25=6(00110).
• 1’s complement of a positive number is same
as binary number

2’s complement
• Add 1 to 1’s complement
• Or start from LSB and upto 1st one (1) dont flip
then after that flit the bits.
• E. G. 010010 to converted to 2’s complement
• Start from LSB and upto 10 no flipping, after that
flip (0100) hence we get 1011(10). As 2’s
complement.
• 2’s complement of a positive number is same as
binary number

Arithematic with 1’s complement
To perform subtraction
• y-x = y+(2n-1-x)-2n +1
• That is add y with 1’s complement of x and
bring carry (-2n) back to the result (+1)
• E.g. 1101(13)-0110(6)=0111(7)
• Take 1’s complement of 0110=>1001
• Add to Augend 1101+1001=(1 carry)0110
• The result is in 1’s complement form

Arithmetic Operations: 1’s Complement
Input: two positive integers x & y,
1. We represent the operands in one’s complement.
2. We sum up the two operands.
3. We delete 2n-1 if there is carry out at left.
4. The result is the solution in one’s complement.
Arithmetic 1’s complement
x + y x + y
x - y x + (2n -1- y) = 2n-1+(x-y)
x – y(y>x) (2n -1-y) + x =2n-1-(y-x)=2n-1-z=1’s comp no
carry
-x - y (2n -1-x) + (2n -1-y) = 2n-1+(2n-1-(x+y))

18
Arithmetic Operations: Example: 4 – 3 = 1
0100 (4 in decimal )
+ 1100 (12 in decimal or 15-3 )
1,0000 (16 in decimal or 15+1 )
0001(after deleting 2n-1)
410 = 01002
310 = 00112 -310 11002 in one’s complement
We discard the extra 1 at the left which is 2n and add one
at the first bit.

19
Arithmetic Operations: Example: -4 +3 = -1
1011 ( 11 in decimal or 15-4 )
+ 0011 ( 3 in decimal )
1110 ( 14 in decimal or 15-1 )
410 = 01002 -410  Using one’s comp. 10112
(Invert bits)310 = 00112
If the left-most bit is 1, it means that we have a negative
number.

20
Example: – 4 – 3 = – 7
4 in binary = 0100.
Flipping the bits, you get –4 (1011) in binary.
3 in binary = 0011.
Flipping the bits, you get –3 (1100) in binary.
1011 (11 in decimal, or 15-4)
+ 1100 (12 in decimal, or 15-3)
-----------------------------------------
1,0111 (23 in decimal (15+15-7))
So now take the extra 1 and remove it from the 5th spot and add it
to the remainder
0111
+ 1
------------------------------------------
1000 (-7 in 1’s comp)
One’s Complement

Arithmetic in 2’s complement
When both nos. Positive
4+3=7
4=0100
3=0011
0100
+0011
---------
0111
--------

When first > second
4-3=1
4=0100
3=0011
-3=1101
Hence
0100
+1101
---------
1)0001
Discard carry

When first < second
-4+3=-1
+4=0100
-4=1100
3=0011
Hence
1100
+0011
---------
1111
1st bit is 1 negative no. (in 2’s complement form)
Take 2’s complement again to get the magnitude

When both nos. negative
-4-3=-7
+4=0100
-4=1100
+3=0011
-3=1101
Hence
1100
+1101
---------
1)1001(2’s complement of 7) discard carry
1st bit is 1 negative no. (in 2’s complement form)
Take 2’s complement again to get the magnitude

Over flow detection in 1’s and
2’s complement
•If the sum of two positive numbers yields a negative result,
the sum has overflowed.
•If the sum of two negative numbers yields a positive result,
the sum has overflowed.
•Otherwise, the sum has not overflowed.
•Is there a carry into sign bit position?
•Is there a carry out of sign bit position?
•If step 2 and step 3 results are not equal then the overflow
condition is detected.

-7-7
01111001(2’s compl)
Hence
1001
+1001
--------
1)0010 (carry into sign
bit =0 and out of it=1)
Example
-7-7
01111000(1’s compl)
Hence
1000
+1000
--------
1)0000 (carry into sign
bit =0 and out of it=1)

Signed Magnitude
•Two representations
of zero
inefficiency and
confusion
•+ve and –ve
numbers need to be
processed separately

1’s complement
•Two representations
of zero
inefficiency and
confusion
•+ve and –ve
numbers need to be
processed separately

Signed 2’s complement

Comparison
Parameter Signed magnitude Signed 1’s
complement
Signed 2’s
complement
Representation Only sign bit is kept
different for +ve
and –ve no.
-ve no is obtained
by flipping the bit in
magnitude part
Is obtained by
adding 1 to 1’s
complement
Range(total n bits) -(2n-1-1) to +(2n-1-1) -(2n-1-1) to +(2n-1-1) -2n-1 to +(2n-1-1)
Representation of
Zero
Two different
representations
Two different
representations
Only one
representation
Processing of +ve
and –ve nos.
Different Different Same
Arithmetic Complex Complex Simple
Overflow detection From carry into sign
bit
From carry into and
out of carry bit
From carry into and
out of carry bit

31
1's Compliment
Let f(x) = 2n -1 -x
Theorem: f(f(x)) = x
Proof: f (f(x))
= f (2n - 1 - x)
= 2n - 1 - (2n -1 - x)
= x
Recovery of the Numbers
2's Compliment
Let g(x) = 2n - x
Theorem: g(g(x)) = x
Proof: g(g(x))
= g(2n - x)
= 2n - (2n - x)
= x

Numeric and Alphanumeric Codes
• Binary code
– by far the most
common way of
representing numeric
information
– has advantages of
simplicity and efficiency
of storage
BinaryDecimal
0
1
10
11
100
101
110
111
1000
1001
1010
1011
1100
etc.
0
1
2
3
4
5
6
7
8
9
10
11
12
etc.

Binary Coded Decimal (BCD code)
• Each digit is represented by 4 bit binary code
• 23 is represented as
• 0010 0011
• 67 is represented as
• 0110 0111
• Some bit are unused
• Easy for human understanding

Numeric and Alphabetic Codes
 Binary-coded decimal code
 formed by converting each
digit of a decimal number
individually into binary
 requires more digits than
conventional binary
 has advantage of very easy
conversion to/from decimal
 used where input and output
are in decimal form
BinaryDecimal
0
1
10
11
100
101
110
111
1000
1001
10000
10001
10010
etc.
0
1
2
3
4
5
6
7
8
9
10
11
12
etc.

• ASCII code
– American Standard Code for Information Interchange
– an alphanumeric code
– each character represented by a 7-bit code
• gives 128 possible characters
• codes defined for upper and lower-case alphabetic
characters,
digits 0 – 9, punctuation marks and various non-printing
control characters (such as carriage-return and backspace)

• Error detecting and correcting codes
– adding redundant information into codes allows
the detection of transmission errors
• examples include the use of parity bits and checksums
– adding additional redundancy allows errors to be
not only detected but also corrected
• such techniques are used in CDs, mobile phones and
computer disks

Excess -3 code
• Obtained by adding 3 in the
number
• Excess-3 code is also known
as self complimenting code
or reflective code, as 1′s
compliment of any number
(0-9) is available within these
10 numbers.
Decimal
Number
Excess-3
Equivalent
0 0011
1 0100
2 0101
3 0110
4 0111
5 1000
6 1001
7 1010
8 1011
9 1100

Binary Quantities and Variables
• A binary quantity is one that can take only 2
states
A simple binary arrangement
S L
OPEN OFF
CLOSED ON
S L
0 0
1 1
A truth table

• A binary arrangement with two switches in
series
L = S1 AND S2

• A binary arrangement with two switches in
parallel
L = S1 OR S2

• Three switches in series
L = S1 AND S2 AND S3

• Three switches in parallel
L = S1 OR S2 OR S3

• A series/parallel arrangement
L = S1 AND (S2 OR S3)

• Representing an unknown network

Logic Gates
• The building blocks used to create digital circuits
are logic gates
• There are three elementary logic gates and a
range of other simple gates
• Each gate has its own logic symbol which allows
complex functions to be represented by a logic
diagram
• The function of each gate can be represented by a
truth table or using Boolean notation

• The NOT gate (or inverter)

• The NOR gate

• The Exclusive OR gate

• The Exclusive NOR gate

Gray code
• Only one bit differs for consecutive number
representation
• Easy to transmit data
• Lesser no. of bits required
• Error detection and correction easier
• a3a2a1a0a3(a3 XOR a2) (a2 XOR a1)(a1 XOR a0)
• 11011(1 XOR 1)(1 XOR 0)(0 XOR 1)
–1011

Gray codes
Decimal Binary Gray
0 0000 0000
1 0001 0001
2 0010 0011
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1100
9 1001 1101
10 1010 1111
11 1011 1110
12 1100 1010
13 1101 1011
14 1110 1001
15 1111 1000

Boolean Algebra
• Boolean Constants
– these are ‘0’ (false) and ‘1’ (true)
• Boolean Variables
– variables that can only take the vales ‘0’ or ‘1’
• Boolean Functions
– each of the logic functions (such as AND, OR and NOT)
are represented by symbols as described above
• Boolean Theorems
– a set of identities and laws.

• Boolean identities
AND Function OR Function NOT function
00=0 0+0=0
01=0 0+1=1
10=0 1+0=1
11=1 1+1=1
A0=0 A+0=A
0A=0 0+A=A
A1=A A+1=1
1A=A 1+A=1
AA=A A+A=A
0 AA 1 AA
10 
01 
AA 

Commutative law Absorption law
Distributive law De Morgan’s law
Associative law Note also
• Boolean laws
ABBA
BAAB


))((
)(
CABABCA
BCABCBA


CBACBA
CABBCA


)()(
)()(
ABAA
AABA


)(
BABA
BABA


ABBAA
BABAA


)(

DeMorgan’s Theorem
BABA
BABA


.
.)(

Combinational Logic
• Digital systems may be divided into two broad
categories:
– combinational logic
• where the outputs are determined solely by the current
states of the inputs
– sequential logic
• where the outputs are determined not only by the
current inputs but also by the sequence of inputs that
led to the current state

• Implementing a function from a Boolean
expression
Example –
Implement the function
CBAX 

• Implementing a function from a Boolean
expression
Example –
Implement the function
DCBAY 

• Generating a Boolean expression from a logic
diagram

Example (continued)
– work progressively from the inputs to the output
adding logic expressions to the output of each gate
turn

• Implementing a logic function from a description
Example –
The operation of the Exclusive OR gate can be stated as:
“The output should be true if either of its inputs are true,
but not if both inputs are true.”
This can be rephrased as:
“The output is true if A OR B is true,
AND if A AND B is NOT true.”
We can write this in Boolean notation as )()( ABBAX 

Example (continued)
The logic function
can then be implemented as before
)()( ABBAX 

• Implementing a logic function from a truth table
Example –
Implement the function of the following truth table
A B C X
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
– first write down a Boolean
expression for the output
– then implement as before
– in this case
– By looking at when X=1
CBACBACBAX 

Example (continued)
The logic function
can then be implemented as before
CBACBACBAX 

• In some cases it is possible to simplify logic
expressions using the rules of Boolean algebra
Example –
can be simplified to
hence the following circuits are equivalent
CAACBCAABCX 
ABCX 

Boolean expression simplefication
• Prove that x+yz=(x+y)(x+z)
• RHS=(x+y)(x+z)
• =x.x+x.z+y.x+y.z; using distributive property
• =x+x.z+x+y.x+y.z; x+x=x
• =x(1+z)+x(1+y)+y.z; taking common
• =x+x+y.z; as 1+x=x
• =x+y.z
• proved

Contd...
• Prove that x(x’+y)=xy
• LHS=x(x’+y)
• =x.x’+x.y
• =x.y; as x.x’=0.
• proved

Contd...
• Simplify f(x,y,z)=x’y’z+ x’yz+ xy’
• x’y’z+ x’yz+ xy’
• =x’z(y’+y)+xy’
• =x’z+xy’; As y+y’=1
• Answer

Contd...
• Simplify f(x,y,z)=xy+x’z+yz
• xy+x’z+yz
• = xy+x’z+yz(x+x’)
• = xy+x’z+yzx+yzx’
• =xy(1+z)+x’z(1+y)
• =xy+x’z; as 1+z=1
• Answer

Contd...
• Prove that (x+y)(x’+z)(y+z)=(x+y)(x’+z)
• LHS=(x+y)(x’+z)(y+z)=(xx’+xz+yx’+yz)(y+z)
• =xyz+yx’+yz+xz+x’yz+yz; as xx’=0, xx=x
• =xx’+xyz+yz+xyz+xz+yx’+x’yz+yz; adding xx’=0
and xyz
• =xx’+yz(1+x)+xz(1+y)+yx’+yz(1+x’)
• =xx’+yz+xz+yx’+yz;
• =xx’+yz+xz+yx’; removing extra yz
• =(x+y)(x’+z)

Exercise...
• Simplify...
• 1. x’y’+xy+x’y
• 2. (x+y)(x+y’)
• 3. x’y+xy’+xy+x’y’
• 4. x’+xy+xz’+xy’z’
• 5. xy’+y’z’+x’z’
• 6. x’yz+xz
• 7. (x+y)’(x’+y’)

Key Points
• It is common to represent the two states of a binary variable by
‘0’ and ‘1’
• Logic circuits are usually implemented using logic gates
• Circuits in which the output is determined solely by the current
inputs are termed combinational logic circuits
• Logic functions can be described by truth tables or using
Boolean algebraic notation
• Binary digits may be combined to form digital words
• Digital words can be processed using binary arithmetic
• Several codes can be used to represent different forms of
information

Minterms
• Variables x, y
• x.y, x’.y, x.y’, x’.y’ 4 possible combinations
• Called minterms
• For n variables 2n minterms
• Each minterm is obtained from AND of n-
variables
• Minterm for 010 binary variable value is x’.y.z’.
• Primed variable for 0 and un-primed for 1.

Maxterms
• Variables x, y
• X+y, x’+y,x+y’, x’+y’ possible combinations
• Called maxterms
• For n variables 2n maxterms
• Each maxterm is obtained from OR of n-variables
• Maxterm for 010 binary variable value is x+y’+z.
• Primed variable for 1 and un-primed for 0.
• Maxterm and minterms are primed of each other

Function in terms of minterms and maxterms
+equivalent to ORing
.equivalent to ANDing

• Any Boolean function can be written as sum of
minterms
• f1’ is sum of minterms corresponding to 0
value of f1.
If we take complement of it again

Canonical Form
• Hence any Boolean function can be written as sum
of minterms.
• Any Boolean function can be written as product of
maxterms.
• Form a maxterm for each combination of the
variables that produces a 0 in the function and
then form AND of those terms
• Boolean function expressed as sum of minterms
or product of maxterms are said to be in canonical
form.

Examples...
• Express F=A+B’C in a sum of minterms.
• F=A+B’C (function must contain all variables)
• =A(B+B’)(C+C’)+B’C(A+A’)
• =ABC+ABC’+AB’C+AB’C’+AB’C+A’B’C
• = ABC+ABC’+AB’C+AB’C’+A’B’C
• =m7+m6+m5+m4+m1
• =m1+m4+m5+m6+m7
• F(A,B,C)=Σ(1,4,5,6,7)
• ANSWER

Examples...
• Express Boolean function F=xy+x’z in a
product of maxterms.
• Using distributive property {A+BC=(A+B)(A+C)}

Removing repeated terms we get
Or, conveniently we express it as

Examples
1.

2.
3.

Conversion between canonical
forms (minterms & Maxterms)
• Consider
Its complement can be expressed as

Standard forms (SOP & POS)
• Need not have all literals(variables)
• Has two forms Sum of Products (SOP) and
Product of Sums (POS)
• SOP
• POS 
• Neither POS nor SOP non standard

Map Method of simplification
• Karnaugh Map Method:
• n-variable 2n squares
• Each square  minterm

Simplification...
• 3-variable K-map

Simplification using K-map
• Make suitable K-map2X 2 squares for 2 variable,
4X4 square for 3 variables
• Mark literal value of each square in the corners
• If minterms are given mark 1’s in the given literal
value position in the map
• If maxterms are given  mark 0’s in the given literal
value
• Try to make quadruples by taking Neighbours

Simplification using K-map
• If some positions are left make pairs of Neighbours
• Make singleton of leftovers
• For each quadruples move horizontally and vertically
and write literal that remains unchanged in require form
(minterm or maxterm)
• If quadruple is verticle or horizontal only (covering a
column or row) both variables in the line will disappear.
• For each pair move horizontally or vertically and write
literal that remains unchanged in required form (minterm
or maxterm)

Examples...
• Simplify the following function in (a) sum of
products (b) product of sums

0 1 3 2
4 5 7 6
12 13 15 14
8 9 11 10
10 11
3
12
4
15
7 6
12 13 15 14
18 19
11
110
AB
Hence
F=A’D’+B’D’+A’BC’
CD 00
00
01
01
11
11 10
10
A’D’
B’D’
A’BC’

Multiple solutions
10
1
13 12
4
15 17
6
12
113 115
14
18 19 111 110
AB
CD 00
00
01
01
11
11 10
10
B’D’
AB
BD
F=B’D’+CD’+BD+AB
CD’

Multiple solutions
10
1
13 12
4
15 17
6
12
113 115
14
18 19 111 110
AB
CD 00
00
01
01
11
11 10
10
B’D’
AD’
BD
F=B’D’+CD’+BD+AD’
CD’

Don’t care conditions
10
1
13 12
4
15 d7
6
d12 113 d15
14
18 19 111 110
AB
CD 00
00
01
01
11
11 10
10
B’D’
AD’
BD
F=B’D’+CD’+BD+AD’
CD’
F=Σ(0,2,3,5,8,9,10,
11,13)+d(7,12,15)

NAND and NOR Implementations:
• NAND and NOR Gates
– Universal Gates: Any digital circuit can be
implemented with NAND or NOR gates alone
• Most appropriate Boolean function
implementation:
• Two-level Implementations using NAND or NOR gates:
Less propagation delay and simple structure.

NAND Gate As Universal Gate:
X
X
F = (X•X)’
= X’+X’
= X’
X
Y
Y
F = ((X•Y)’)’
= (X’+Y’)’
= X’’•Y’’
= X•Y
F = (X’•Y’)’
= X’’+Y’’
= X+Y
X
X
F = X’
X
Y
Y
F
X•Y
F =
X+Y

NAND Circuits
• To easily derive a NAND implementation of a
Boolean function:
– Find a simplified SOP
– SOP is an AND-OR circuit
– Change AND-OR circuit to a NAND circuit
– Use the alternative symbols below: Bubbled ORNAND

AND-OR (SOP) Two-level implementations
Using NANDs
G=WXY+YZ
a) Original SOP: AND-OR
b) Implementation with NANDs

AND-OR (SOP) Two-level implementations
Using NANDs
Verify:
(a) G = WXY + YZ
(b) G = ( (WXY)’ • (YZ)’ )’
= (WXY)’’ + (YZ)’’ = WXY + YZ

Two-Level NAND Gate Implementation
- Example
F (X,Y,Z) = m(0,6)
1. Express F in SOP form using K-Map:
F = X’Y’Z’ + XYZ’
2. Obtain the AND-OR implementation for F.
3. Add bubbles and inverters to transform AND-
OR to NAND-NAND gates.

Example (cont.)
Two-level implementation with NANDs
F = X’Y’Z’ + XYZ’

NOR Gate
• Also a “universal” gate because ANY digital
circuit can be implemented with NOR gates
alone.
• This can be similarly proven as with the NAND
gate.

NOR Circuits
• To easily derive a NOR implementation of a Boolean
function:
– Find a simplified POS
– POS is an OR-AND circuit
– Change OR-AND circuit to a NOR circuit
– Use the alternative symbols below: Bubbled ANDNOR

Two-Level NOR Gate Implementation -
Example
F(X,Y,Z) = m(0,6)
1. Express F in POS form using K-Map:
F= (X'+Y)(X+Y')Z'
2. Obtain the OR-AND implementation for F.
3. Add bubbles and inverters to transform OR-AND
implementation to NOR-NOR implementation.
Practice some example to express a function in SOP or POS for
using K-map
Hint- when 0’s are considered we write maxterms and get POS
form of function
-when 1’s are considered we write minterms and get SOP form
of function

Example (cont.)
Two-level implementation with NORs
F = (F’)' = (X'+Y)(X+Y')Z'

Practice Problems:
• Assuming that normal and complement inputs
are available, implement following Boolean
function using minimum number of gates
mentioned---
F=AB’+ABD+ABD’+A’C’D’+A’BC’---NAND Gates
only
F=BD+BCD’AB’Ç’D’—NOR gates only
F=(A+D)(A’+B’)(A’+C’)—NAND Gates only

Summary: Two level implementation
of Boolean Function
Form of Function Basic Implementation Equivalent universal logic
implementation
SOP AND-OR NAND-NAND
POS OR-AND NOR-NOR

STORAGE ELEMENTS:
• Maintain a binary state indefinitely as long as
power is delivered to the circuit
• Latches: Binary state changes with signal
levels: Level Triggered
• Flip-flops: Binary state changes with signal
transitions: Edge Triggered

Core of a Flip-Flop:
The set–reset or SR Latch
• Acts as a simple memory with two stable states at
the two output when S = R = 0
– Q1 and Q2 are the outputs of the S-R latch.
– When Q1 is known as Q and Q2 is also called Q’ or
(spoken as Q bar), meaning that its value is not Q or the
opposite of Q.
Q

Working of NAND gate...

Working...
Qt S R Qt+1 Q’t+1 Comment
0 0 0 0 1 No change
0 0 1 0 1 Reset
0 1 0 1 0 Set
0 1 1 1 1 Invalid
1 0 0 1 0 No change
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 1 1 Invalid
0
0
1
1
1
0
1
0
Q(t+1)=(Q’(t). S’)’=Q(t)+S
Q’(t+1)=(Q(t). R’)’=Q’(t)+R
Q(t) Present state (value)
Q(t+1) Next state (value)

S-R Latch
•The latch
-holds (stores) when S = R = 0
-is set (to 1) by bringing S = 1 with R = 0
-is reset (to 0) or cleared by bringing R = 1 with S = 0
•The condition S = R = 1 must be avoided because it leads to an
indeterminate condition, where the output can not be predicted
at any one point in time. This can cause a race condition to
occur when the inputs change to S = R = 0.

SR Latch with Enable
•The S and R inputs only effect the output states when the
enable input C is high.
– This controls when the latch responds to its inputs.
•The latch holds (retains previous state) its value while the
enable input is low — latches it!
•Any changes in the inputs during the time when enable is high
will affect the output immediately: the circuit is said to be
transparent.
•This circuit still has a major problem: the stored value is
indeterminate if S = R = 1 when the clock goes low
0
1
1
Q
Q’
Q’
Q

Logic Table
SR Latch
S R Q
0 0 Last Q
0 1 0
1 0 1
1 1 ??
SR Latch with Enable
S R E Q
0 0 1 Last Q
0 1 1 0
1 0 1 1
1 1 1 ???
X X 0 Last Q

Race condition
Circuit Boolean Logic
• Q1(t+1)=(S’.Q2(t))’
• =S+Q’2(t)
• Q2(t+1)=(R’.Q1(t))’
• =R+Q’1(t)
• When S=R=0; with Q1=Q2=1
• Q1(t+1)=Q’2(t)
• Q2(t+1)=Q’1(t)
• Keep on toggling
01010.... racing

Timing Diagram

Timing Diagram
No Initial Condition
Propagation Delay Time
Indeterminate Condition, Q = Q’
Followed by a Race Condition

Working of NOR gates...

Latches: SR Latch with NOR gates
The SR latch is a circuit with two cross-coupled NOR gates or
two cross-coupled NAND gates. It has two inputs labeled S
for set and R for reset.

SR Latch with NAND Gates

Graphic Symbols for Latches
126
A latch is designated by a rectangular block with inputs on
the left and outputs on the right. One output designates the
normal output, and the other designates the complement
output.
NOR Latch: Active High Inputs NAND Latch: Active Low Inputs

SR Latch with Control (Enable) Input
The operation of the basic SR latch can be modified by
providing an additional control input that determines when
the state of the latch can be changed. It consists of the basic
SR latch and two additional NAND gates.

Symbol:
128

D-Latch and Symbol:
129

Flip-Flops
The state of a latch or flip-flop is switched by a change in
the control input. This momentary change is called a trigger
and the transition it cause is said to trigger the flip-flop. The
D latch with pulses in its control input is essentially a flip-flop
that is triggered every time the pulse goes to the logic 1
level. As long as the pulse input remains in the level, any
changes in the data input will change the output and the
state of the latch.

Clock Response in Latch
In Fig (a) a positive level response in the control input
allows changes, in the output when the D input changes
while the clock pulse stays at logic 1.

Clock Response in Flip-Flop

Latches and Flip Flops

Edge-Triggered D Flip-Flop
The first latch is called the master and the second the
slave. The circuit samples the D input and changes its output
Q only at the negative-edge of the controlling clock.
CLK 1 0 1 0 1 0
D 1 1 0 0 1 1 …
Y 1 1 0 0 1 1 …
Q ? 1 1 0 0 1 ….

Graphic Symbol for Edge-Triggered D Flip-Flop

JK Flip-Flop
There are four operations that can be performed with a flip-
flop: set it to 1, reset it to 0, no change, complement its
output. The JK flip-flop performs all four operations. The
circuit diagram of a JK flip-flop constructed with a D flip-
flop and gates.
Q=J.Q’+K’.Q

Operation...
Q=J.Q’+K’.Q

JK Flip-Flop
The J input sets the flip-flop to 1, the K input resets it to 0, and
when both inputs are enabled, the output is complemented.
This can be verified by investigating the circuit applied to the
D input:
D = J Q` + K` Q

T (Toggle) Flip-Flop
The T flip-flop is a complementing flip-flop and can be
obtained from a JK flip-flop when inputs J and K are tied
together.

T Flip-Flop
140
The T flip-flop can be constructed with a D flip-flop and an
exclusive-OR gates as shown in Fig. (b). The expression
for the D input is D = T Q = TQ` + T`Q

Flip-Flop Characteristic
Equations
D flip-flop Characteristic Equations
Q(t + 1) = D
JK flip-flop Characteristic Equations
T flip-flop Characteristic Equations
Q(t + 1) = JQ` + K`Q
Q(t + 1) = T Q = TQ` + T`Q

Comparison:
142
Flip Flop SR D JK T
No of
Inputs
2 1 2 1
No of
Operations
3 2 4 2
Invalid
State?
Yes No No No
Toggle
State?
No No Yes Yes
Applicatio
n
Set-Reset
Circuit
Controlled
Data
Transfer,
Registers
Counters Counters

Lecture Review Questions
1. What is the fundamental difference between combinational and
sequential logic?
2. What inputs should you put on a SR flip-flop to set it (to 1)?
3. Why must S = R = 1 be avoided?
4. Why do sequential logic circuits need a clock?
5. What is meant by the term edge-triggered flip-flop?
6. Describe the operation of a type D flip-flop. For what are they used?
Describe the operation of a JK flip-flop with J = K = 1.
7. Why do some flip-flops have control inputs? In what ways do they differ
from the normal inputs, such as J and K?
8. What is the propagation delay? Why is it important?

Digital Electronics and Computer Language

Recommended

Recommended

More Related Content

What's hot

What's hot (20)

Similar to Digital Electronics and Computer Language

Similar to Digital Electronics and Computer Language (20)

More from Manthan Chavda

More from Manthan Chavda (20)

Recently uploaded

Recently uploaded (20)

Digital Electronics and Computer Language

Editor's Notes