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SAW KAH CHIAT
Bachelor in Electrical and Electronics (Hons.) Engineering
Universiti Tenaga Nasional
Graduate in April 2011
(rev. Sept 2014)
Career Objectives:
A fresh Electrical and Electronics graduate seeking for initial placement in electronic design
involved with research, development, testing, and evaluation with a company committed to
continuous improvement and on-time delivery of products or services. Management is my long-
term objective.
Personal Details
IC Number: 881213-09-5019
Address: 19, Taman Pengkalan Assam, 01000 Kangar, Perlis.
Contact Number: +6012-4979148 / +(886) 978 641 734
Email Address: chiat88@gmail.com
Pass Experience
Career Position: Silicon Design Engineer
Company: Intel Microelectronics (M) Sdn Bhd | Penang, Malaysia
Duration: May 2011 – July 2014
Specialized: IC Design, SOC:
Broadwell Project – FUB owner
1. Owner of Functional Unit Blocks (FUB). In this ‘tick’ project, we have to
migrate Haswell designs into newer process technology.
2. From RTL codes, schematics and layouts are produced meeting timing,
quality, power and layout criteria, while maintaining the design equivalence.
Broadwell Project – FCIC IC designer
1. Connects signals that propagates across multiple sections.
2. Planning the topology and metal layer to be used, doing repeater insertion
to meet timing and slope requirements, while maintaining the overall power
consumption.
Broadwell Project – Repeater Bay Cleanup
1. Layout is not fully clean against Design Rule Checker (DRC) errors.
Manual work has to be done to meet the layout requirements.
Carbon Canyon Project And Broxton Project – Formal Equivalence
Verification Expert User
1. Working as horizontal group that supports multiple partitions and units
across CRC and BXT projects.
2. Troubleshooting tool and flow issues and work around with Design
Automation team for solutions.
3. Detecting and root causing the differences detected between RTL codes
and produced netlist.
Education Background
University: Universiti Tenaga Nasional (UNITEN)
Current Course: Bachelor in Electrical and Electronics (Hons.) Engineering
Latest CGPA: 3.81
Completion Date: April 1st, 2011
Final Year Project
Title Development of UNITEN Standard Cell Library for Digital Logic Design
Details A standard cell is a group of transistors and interconnecting structures that
provides a Boolean logic function. Using Silterra 0.18 micron technology,
the project requirements are:
1. Design basic logic gates including NOT, NAND and NOR at both
transistor and layout levels;
2. Design CMOS logic gates covering AND, OR at transistor level and
layout level;
3. Design complex logic gates including EXOR, EXNOR, AND-OR,
INVERTED-AND-OR, OR-AND, and INVERTED-OR-AND at
transistor level and layout level;
4. Perform RC extraction analysis for each design;
5. Perform Power Analysis for each design.
EDA Tools related 1. Design Architect – IC (DA-IC) from Mentor Graphics
2. IC Station from Mentor Graphics
Awards Received:
1. Tan Sri Dato’ Alex Lee Excellence Award 2006
Co-curricular Activities:
1. Columnist in “Youth Section” of Sinchew Jit Poh Nortern Edition from September until
November 2004
2. 18th Sinchew Jit Poh school reporter
3. Program Group Committee member for Chinese New Year Night 2007
4. Involved in 7th Chinese Cultural Society workshop
5. Vice head of documentation section of UNITEN Chinese Debate Team
Practical Experience
Company Name: Tanjong Kling Power Station (TPKS), Powertek Berhad.
Position: Trainee
Duration: 12 weeks (April 5th, 2010 until June 25th, 2010)
Attributes:
1. Able to travel when needed
2. Able to adapt in new environment
3. Fluent in English, Malay and Chinese Languages
Skills Learnt:
EDA Tools:
1. Intel Built-in Layout Design Tool
2. Synopsys SOC Structural Design (SD)-related Tools
3. Design Architect – IC from Mentor Graphics
4. IC Station from Mentor Graphics
Office-related software:
1. Microsoft Word, Excel and Power Point
Computing languages-related software:
1. MikroC from MikroElektronika
2. Xilinx ISE and EDK 10.1
3. MATLAB 2014
4. Unity 5
5. Hadoop and cloud-computing-related
Programming Languages:
C, C++, PERL, TCL, CSH
Refereces:
1. Azrul bin Ghazali (Final year project supervisor)
Lecturer in Unversiti Tenaga Nasional
Bachelor of Engineering in Electrical Engineering, Vanderbilt University, USA, 1998
Master of Science (Microelectronics), UKM 2003
Contact Number: 03-8921 2219
Email: azrulg@uniten.edu.my
2. Yasmin Hanum Md Thayoob, Dr. (Academic Advisor)
Senior Lecturer in Universiti Tenaga Nasional
Ph.D in Electrical Engineering (UNITEN), 2008
M. Sc. in Electrical Engineering (Univ. of Southampton, UK), 1990
B. Sc. in Electrical Engineering (Univ. of Miami, USA), 1987
Contact Number: 03-8922 1588
Email: yasmin@uniten.edu.my

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KC Latest Resume 2014

  • 1. SAW KAH CHIAT Bachelor in Electrical and Electronics (Hons.) Engineering Universiti Tenaga Nasional Graduate in April 2011 (rev. Sept 2014) Career Objectives: A fresh Electrical and Electronics graduate seeking for initial placement in electronic design involved with research, development, testing, and evaluation with a company committed to continuous improvement and on-time delivery of products or services. Management is my long- term objective. Personal Details IC Number: 881213-09-5019 Address: 19, Taman Pengkalan Assam, 01000 Kangar, Perlis. Contact Number: +6012-4979148 / +(886) 978 641 734 Email Address: chiat88@gmail.com Pass Experience Career Position: Silicon Design Engineer Company: Intel Microelectronics (M) Sdn Bhd | Penang, Malaysia Duration: May 2011 – July 2014 Specialized: IC Design, SOC: Broadwell Project – FUB owner 1. Owner of Functional Unit Blocks (FUB). In this ‘tick’ project, we have to migrate Haswell designs into newer process technology. 2. From RTL codes, schematics and layouts are produced meeting timing, quality, power and layout criteria, while maintaining the design equivalence. Broadwell Project – FCIC IC designer 1. Connects signals that propagates across multiple sections. 2. Planning the topology and metal layer to be used, doing repeater insertion to meet timing and slope requirements, while maintaining the overall power consumption.
  • 2. Broadwell Project – Repeater Bay Cleanup 1. Layout is not fully clean against Design Rule Checker (DRC) errors. Manual work has to be done to meet the layout requirements. Carbon Canyon Project And Broxton Project – Formal Equivalence Verification Expert User 1. Working as horizontal group that supports multiple partitions and units across CRC and BXT projects. 2. Troubleshooting tool and flow issues and work around with Design Automation team for solutions. 3. Detecting and root causing the differences detected between RTL codes and produced netlist. Education Background University: Universiti Tenaga Nasional (UNITEN) Current Course: Bachelor in Electrical and Electronics (Hons.) Engineering Latest CGPA: 3.81 Completion Date: April 1st, 2011 Final Year Project Title Development of UNITEN Standard Cell Library for Digital Logic Design Details A standard cell is a group of transistors and interconnecting structures that provides a Boolean logic function. Using Silterra 0.18 micron technology, the project requirements are: 1. Design basic logic gates including NOT, NAND and NOR at both transistor and layout levels; 2. Design CMOS logic gates covering AND, OR at transistor level and layout level; 3. Design complex logic gates including EXOR, EXNOR, AND-OR, INVERTED-AND-OR, OR-AND, and INVERTED-OR-AND at transistor level and layout level; 4. Perform RC extraction analysis for each design; 5. Perform Power Analysis for each design. EDA Tools related 1. Design Architect – IC (DA-IC) from Mentor Graphics 2. IC Station from Mentor Graphics Awards Received: 1. Tan Sri Dato’ Alex Lee Excellence Award 2006
  • 3. Co-curricular Activities: 1. Columnist in “Youth Section” of Sinchew Jit Poh Nortern Edition from September until November 2004 2. 18th Sinchew Jit Poh school reporter 3. Program Group Committee member for Chinese New Year Night 2007 4. Involved in 7th Chinese Cultural Society workshop 5. Vice head of documentation section of UNITEN Chinese Debate Team Practical Experience Company Name: Tanjong Kling Power Station (TPKS), Powertek Berhad. Position: Trainee Duration: 12 weeks (April 5th, 2010 until June 25th, 2010) Attributes: 1. Able to travel when needed 2. Able to adapt in new environment 3. Fluent in English, Malay and Chinese Languages Skills Learnt: EDA Tools: 1. Intel Built-in Layout Design Tool 2. Synopsys SOC Structural Design (SD)-related Tools 3. Design Architect – IC from Mentor Graphics 4. IC Station from Mentor Graphics Office-related software: 1. Microsoft Word, Excel and Power Point Computing languages-related software: 1. MikroC from MikroElektronika 2. Xilinx ISE and EDK 10.1 3. MATLAB 2014 4. Unity 5 5. Hadoop and cloud-computing-related Programming Languages: C, C++, PERL, TCL, CSH
  • 4. Refereces: 1. Azrul bin Ghazali (Final year project supervisor) Lecturer in Unversiti Tenaga Nasional Bachelor of Engineering in Electrical Engineering, Vanderbilt University, USA, 1998 Master of Science (Microelectronics), UKM 2003 Contact Number: 03-8921 2219 Email: azrulg@uniten.edu.my 2. Yasmin Hanum Md Thayoob, Dr. (Academic Advisor) Senior Lecturer in Universiti Tenaga Nasional Ph.D in Electrical Engineering (UNITEN), 2008 M. Sc. in Electrical Engineering (Univ. of Southampton, UK), 1990 B. Sc. in Electrical Engineering (Univ. of Miami, USA), 1987 Contact Number: 03-8922 1588 Email: yasmin@uniten.edu.my