Low power electronic design

Intelligent Systems and Advanced Computing (iSaac)
15
LOW POWER ELECTRONIC
DESIGN
VLSI Power Architecture
Mahesh Dananjaya

LOW POWER
ELECTRONIC DESIGN
VLSI POWER ARCHITECTURE
ISAAC
Intelligent Systems and Advanced Computing
W A T Mahesh Dananjaya
(dananjayamahesh@gmail.com)
Department of Electronic and Telecommunication Engineering
University of Moratuwa
Sri Lanka

Content
1. Semiconductor Engineering
1.1. Semiconductors
1.1.1.Extrinsic Semiconductors
1.2. Transistors
1.2.1.Bipolar Junction Transistors (BJT)
1.2.2.Field Effect Transistors (FET)
1.2.2.1. Junction Field Effect Transistors (JFET)
1.2.2.2. Metal Oxide Semiconductor Field Effect Transistors (MOSFET)
1.2.2.2.1. MOS Capacitance
1.2.2.2.2. Basic MOSFET Operation
1.2.2.2.3. Enhancement Mode & Depletion Mode
1.2.2.2.4. P Channel MOSFET
1.2.2.2.5. N Channel MOSFET
1.3. Basic Logic Cells
2. Power Estimation
2.1. Dynamic Power
2.1.1.Switching Power
2.1.2.Internal Power
2.2. Static Power
2.2.1.Leakage Power
2.2.1.1. Threshold Leakage
2.2.1.2. Sub-threshold Conduction
2.2.1.3. Transistor Leakage Mechanisms
2.2.1.3.1. Drain Leakage Current/Sub threshold Leakage Current
2.2.1.3.1 Reverse Biased Current
2.2.1.3.1 Sub Threshold Drain Current
2.2.1.3.1 Gate Induced Drain Leakage
2.2.1.3.2. Gate Leakage Current
2.2.1.3.1 Gate Tunneling
2.2.1.3.2.1.1. Fowler-Nordheim Tunneling

2.2.1.3.2.1.2. Direct Tunneling
2.2.1.3.1 Hot Carrier Injection
2.3. Technology Scaling & Power Estimation
2.3.1.CMOS Device Scaling
2.3.1.1. Gate Oxide Thickness Scaling
2.3.1.2. Channel Miniaturization
2.3.1.3. Supply Voltage and Threshold Voltage Scaling
2.3.1.4. Doping Concentration
2.3.1.5. Source Drain Punchthrough
2.4. Miscellaneous Power Consumption and Estimation
2.4.1.Meta-stability
2.4.1.1. Hold Time
2.4.1.2. Set Up Time
2.4.2.Glitches
2.4.3.Latch-ups
2.5. Electronic Design Automation (EDA) Power Estimation Techniques
3. Power Reduction
3.1. Dynamic Power Reduction
3.1.1.Clock Gating
3.1.1.1. Local Clock gating
3.1.1.1.1. Latch Based Clock gating
3.1.1.1.2. Latch Free Clock Gating
3.1.1.2. Multi-Level Boolean Logic
3.1.1.2.1 Satisfiability Don’t Care (SDC)
3.1.1.2.1 Observability Don’t Care (ODC)
3.1.1.3. Advanced Clock Gating
3.1.1.3.1 Stability Condition (STC)
3.1.1.4. Enable Strengthening and Clock Gating Efficiency

3.1.1.4.1. Strong STC
3.1.1.4.2. Strong ODC
3.1.1.5. Memory Power Reduction
3.1.1.5.1. Redundant Read Removal
3.1.1.5.2. Redundant Write Removal
3.1.1.5.3. Memory As Steering Point for Register Power Reduction
3.1.1.5.4. Light Sleep Power Reduction
3.2. Static Power Reduction
3.2.1.Comparison with Dynamic Power
3.2.2.Power Gating
3.2.2.1. Sleep Transistors/Switches
3.2.2.1.1. Switch Types
3.2.2.1.2. Switch Sizing
3.2.2.1.3. Switch Placing Architecture
3.2.2.2. Power Gating Modes
3.2.2.2.1. Fine Grain Power Gating
3.2.2.2.2. Coarse Grain Power Gating
3.2.2.3. Power Gating Factors
3.2.2.4. Synchronous and Asynchronous Power Gating
3.2.2.5. Power Gating/Controlling Mechanisms
3.2.2.5.1. Non-State Preserving Power Gating
3.2.2.5.2. State Preserving Power Gating
3.2.2.5.2.1.1. State retention Techniques
3.2.2.5.2.1.1.1. Retention Registers
3.2.2.6. Compiler Based and Hardware Based Power Gating
4. Power Verification
5. Power Fix

Short Contents with Page Numbers
1 Semiconductor Engineering..................................................................................................................8
1.1 Semiconductors ............................................................................................................................8
1.1.1 Extrinsic Semiconductors......................................................................................................8
1.2 Transistors 9
1.2.1 Bipolar Junction Transistors (BJT) .........................................................................................9
1.2.2 FET (Field Effect Transistor) ................................................................................................11
2 Power Estimation................................................................................................................................22
2.1 Dynamic Power...........................................................................................................................22
2.1.1 Switching Power..................................................................................................................23
2.1.2 Internal Power.....................................................................................................................25
2.2 Static Power ................................................................................................................................26
2.2.1 Leakage Power....................................................................................................................27
2.3 Technology Scaling and Power Estimation Revolutions .............................................................32
2.3.1 CMOS Device Scaling...........................................................................................................32
2.4 Miscellaneous Sources of Power Consumption..........................................................................34
2.4.1 Metastability.......................................................................................................................35
2.4.2 Glitches................................................................................................................................35
2.4.3 LatchUps..............................................................................................................................35
2.5 Power Estimation Techniques in Electronic Design Automation (EDA)......................................36
3 Power Reduction.................................................................................................................................38
3.1 Dynamic Power Reduction..........................................................................................................38
3.1.1 Clock Gating ........................................................................................................................39
3.2 Static Power Reduction...............................................................................................................51
3.2.1 Power Gating.......................................................................................................................54
4 Power Verification ..............................................................................................................................64
4.1 Verification of Power Monitors ..................................................................................................64
5 Power Fix.............................................................................................................................................66

Introduction to VLSI Power
Electronics
Electronic has been emerging its counterpart ever since the semiconductor was born. Now
it has been developed throughout few decades and changed world into upside down. Electronic has
evolved from vacuumed tubes to highly complex electronics designs passing through many more
intermediate technology revolutions such as diodes, transistors, microcontrollers, microprocessors, ASIC,
DSP, FPGA, SOC, SOPC, MPSOCs. Integrated Circuit designs have dramatically changed to very low level
designs to Very Large Scale Integrated Circuit (VLSI) designs. These technology systems consist of internal
technology nodes such as logic cells, Gates, adders, Flip-flops, counters, registers, multiplexers etc.
Electronic systems became the caliber behind every nook and corner of the technology and provide
solutions to every field such as computing, robotics, biomedical engineering, IOT, embedded system
designing ,Telecommunication and information processing, networking and security etc. Nowadays
technologies serve in a system level and advancing the inherent strength of the electronic fields to
optimize and improve the system performances.
Electronic Systems
Electronic system is set of interacting and independent electronic components including active as well
as passive components. System design can be identified in different levels. Component/Device level
consists of electronic components and semiconductor components such as transistors and diodes. In
medium level abstraction these designs can be identified as circuit level such as logic level. In high level
abstraction electronic designs can be identified as a System level where Main system is consist of such
sub systems which integrated together. Therefore the overall system performances are depending on the
optimizations of each and every sub system and integrating them in the optimized way.
VLSI Power
VLSI power is the main area that all the future electronic designs and developments looking forward to,
because of its essence to core performances and values. System power estimation and reduction is the
major focus of most of the design engineers today. Therefore throughout this paper I am trying to give
overall perception and a core impression about system power. Because all the electronic designs are

focused on novel power reducing techniques which can save IC power by a large percentage. Clock gating,
Power gating are some of basic techniques used to reduce integrated circuit power. Electronic engineers
are working on all these layers to reduce power such as device level, circuit level and high level abstraction
levels.
VLSI Power Estimation, Reduction, Fix and
Verification
1 Semiconductor Engineering
1.1 Semiconductors
Material that has both conduction and insulation properties are called a semiconductor. As the name
implies the semiconductors are materials of having conductivity between insulators and pure conductors.
Operation of semiconductors is based on the quantum physics and energy band theories. Materials such
as Silicon, Germanium are well known semiconductors.
1.1.1 Extrinsic Semiconductors
Base Semiconductor is doped with P-type impurities such as Boron (B), Aluminum (Al) and N-type
impurity materials such as Phosphorus (P) and Arsenic (As).

1.2 Transistors
Transistors are the semiconductor devices which can be used as an electronic switches, amplifiers and
power sources. There are two types of transistors, Bipolar Junction Transistors (BJT) and Field Effect
Transistors (FET).
1.2.1 Bipolar Junction Transistors (BJT)
Bipolar Junction Transistors are relies on the contact and combining of two types of semiconductor for
its operation. BJT can be used as amplifier, switches and oscillators. Operation of BJT involves both
electrons and holes. Uniquely in semiconductors these two type s are originated with the two different
doping of impurities in to base material. Current flow is due to diffusion of charge carriers across the
junction between two regions of different charge concentrations. Electrons are majority charge carriers
in n-type semiconductors, whereas holes are majority charge carriers in p-type semiconductors.

Basically BJTs are consisting of 3 lead called Base, Collector and Emitter. Therefore we can use
characteristics equations and graphs to identify the operation of the BJT.
By controlling the electric field across Base-Emitter junction thus depletion layer we can control the
charged carriers flows between collector and emitter. Above figure shows the operation of NPN transistor.
Characteristics graph of the BJTs are shown here. This will illustrate the operation of NPN transistor. PNP
transistor also works in a similar way.
Transistors are used in three different configurations, common Base, common Collector and common
collector. We are not discussed them here and our aim is to illustrate power of those semiconductor
materials later.

Unipolar Transistors
1.2.2 FET (Field Effect Transistor)
Field Effect Transistor (FET) is one of unipolar transistors that use an electric field to control the shape
and hence the conductivity of a channel of one type of charge carrier in a semiconductor material and
involve single carrier operation. FET are single charged carrier device and FET is consist of an active
channel through which charge carriers, electrons and holes, flow from the source to drain. Source and
drain terminal conducts are connected to the semiconductor through Ohmic contacts. More important
characteristic of this device is that the conductivity of the channel is a function of the potential applied
across the gate and source terminals. There are three leads for FET, gate, source and drain.
Field Effect Transistor (FET) operates as a conducting semiconductor channel with two Ohmic
contacts between semiconductor and metal, the source and the drain, where the amount of charged
carriers the channel is controlled by the third contact, the gate. In the vertical direction the gate channel
and the substrate structure (gate junction) can be regarded as an orthogonal two terminal device, which
is either a MOS structure or a reverse biased rectifying device that controls the mobile charge across the
channel by capacitive coupling (Filed Effect).
Metal Oxide Semiconductor FET (MOSFET), junction gate FET (JFET), Metal Semiconductor
(MESFET), Heterostructure FET (HFET), are types of FETs.
1.2.2.1 JFET or JUGFET (Junction Gate Field Effect Transistors)
JFET is a type of FET and simplest type of field effect transistors. JFETs are used as electronically
controlled switches, amplifiers or voltage controlled resistors. According to the channel formed by the
source and drain there are two types. N type and P type. This JFET has large input impedance.
The JFET is a long channel of semiconductor material, doped to contain an abundance of positive charged
carriers or holes (p-type), or of negative carriers or electrons (n-type).Ohmic contact at each end form the

source (S) and drain (D).A PN Junctions formed on one or both sides of the channel, or surrounding it,
using a region with doping opposite to that of the channel, and biased using an ohmic gate contact (G).
JFET is known as a depletion mode device.
Flow of electric charge through a JFET is controlled by constricting the current-carrying channel. The
current also depends on the electric field between source and drain (analogous to the difference in
pressure on either end of the hose). Constriction of the conducting channel is accomplished using the field
effect. Voltage between the gate and source is applied to reverse bias the gate-source PN-junction.
Therefore drain to source current is controlled by the electric field between gate to source. Characteristic
diagram of the JFET is shown below.

1.2.2.2 MOSFET (Metal Oxide Semiconductor)
The most important FET is the MOSFET. In a silicon MOSFET, the gate contact is separated from
the channel by an insulating silicon dioxide layer. The charge carrier of the conducting channel constitute
an inversion charge, that is, electrons in the case of a P-type substrate in n channel device and holes in
the case of a n-type substrate in P channel devices, induced in the semiconductor at the silicon insulator
interface by the voltage applied across the gate electrodes. The electrons enter and exit the channel at n+
source and drain contacts regarding the N channel MOSFET and at p+ regarding the P channel MOSFET.

1.2.2.2.1 MOS Capacitance
MOSFET is different from the JFET operation because rather than having a reverse biased
rectifying features MOS structure has a MOS capacitor which make a bridge between gate and the
substrate layer. MOS capacitance is the vital part of MOSFET which constitutes the important gate-
channel-substrate structure of the MOSFET. MOS capacitor is a two terminal semiconductor device of
practical interest in its own right. As shown in the below figure it consist of a metal contact separate from
the
semiconductor by a dielectric insulator. An additional Ohmic contact is provided at the semiconductor
substrate. Most of the time MOS structure use doped silicon as the substrate and its native oxide, silicon
oxide as the insulator part.
Because of the insulator it creates an infinite input impedance, preventing any charged carrier transport
across the dielectric layer when a bias voltage is applied between the metal and the semiconductor.

Instead, the applied voltage will induce charge and counter charges and counter charges in the metal and
in the interface layer of the semiconductor, similar to what we expect in the metal plates of a conventional
parallel plate capacitor. However in the MOS capacitor we may use the applied voltage to control the type
of interface charge we induce in the semiconductor, majority carriers, minority carriers and depletion
charge.
1.2.2.2.2 Basic MOSFET Operation
In the MOSFET an inversion layer at the semiconductor oxide interface acts as a conducting
channel. For example in an n channel MOSFET, the substrate is a p-type silicon and the inversion charge
consist of electrons that form a conducting channel between the n+ ohmic source and the drain contacts.
At DC condition, the depletion region and the neutral substrate provide isolation between devices and
fabricated on the same substrate.
In MOS capacitor, inversion charge can be induced in the channel by applying a suitable gate voltage
relative to other terminals. The onset of strong inversion is defined in terms of a threshold voltage Vt
being applied to the gate electrode relative to the other terminals. In order to assure that the induced
inversion channel extends all the way from source to drain, it is essential that the MOSFET gate structure

either overlaps slightly or align with the edges of these contacts. Self-alignment is preferable since it
minimize the parasitic gate-source and gate-drain capacitances.
1.2.2.2.3 MOSFET- Depletion Mode and Enhancement Mode
So far we have discussed about the paramount importance of the MOSFET to the VLSI technology
and without MOSFETs contribution modern electronic systems consist of VLSI technology and large scale
integration is impossible. MOSFETs are usually capable of voltage gain and signal power gain. In this
section we will try to get some understanding about the MOSFET modes and operations which are very
deeply contribute to the VLSI power architectural analysis. N channel and P channel MOSFETs are the two
basic types of MOSFETs. In n channel MOSFET current is due to the flow of electrons in inversion layer and
in p channel current is due to the flow of holes. There are two modes of MOSFET based on their design
architecture, Depletion mode and Enhancement mode. Due to various reasons such as performance,
power and efficiency enhancement mode is widely used in VLSI designs.
1.2.2.2.4 1.2.2.2.4 P Channel MOSFET
MOSFET which deploy p channel region between source and drain is called p-channel MOSFET. Usually
it’s a four terminal device gate, source, drain and substrate or body. Mostly substrate lead is connected
with source lead. Drain and the source are heavily doped with p type impurities thus called p+ regions and
MOSFET
Enhancement
Mode
N Channel P Channel
Depletion
Mode
N Channel P Channel

substrate is a doped n-type region. Current flow due to flow of positively charged holes that’s why it’s
called p channel MOSFET.
Depletion Mode: There is a p-type region beneath the oxide layer thus already has a current flowing path
and already form a junction between n-type substrate materials. Therefore it’s really effects the
characteristic MOSFET.
Enhancement Mode: There is no p-type region beneath the insulation part and thus threshold voltage is
higher than the depletion mode type. Weak inversion layer is established by the holes extracted by the
p+ regions such as source and drain and minority carriers of the n type substrate.
When applying negative gate voltage, the electrons present beneath the oxide layer, experiences
repulsive force and they are pushed downwards into the substrate, the depletion region is populated by

the bound positive charges which are associated with the donor atoms. Provided that negative voltage to
the gate attracts holes from p+ source and drain region in to the channel region. Thus the channel is
formed with the holes. Now if we apply a voltage difference between the source and the drain, current is
flowing through the channel. The gate voltage controls the Hole concentration of the channel. Only
different in the enhancement mode and depletion mode is that depletion mode MOSFET already contain
a conduction channel (path) and has inversion layer, but enhancement mode do not have a inversion layer
and thus form a weak inversion layer when negative voltage is supplied to the gate by extracting p (holes)
from p+ regions. Thus compose a conduction channel and when gate to source voltage exceeds the
threshold, conduction happens from source to drain if we provide a drain to source voltage.
Characteristic curves of P channel MOSFET
P channel Enhancement Mode Operation

P Channel Depletion Mode
1.2.2.2.5 1.2.2.2.5 N Channel MOSFET
MOSFET having an n-channel region between source and drain is known as n-channel MOSFET. N
channel MOSFET is also consist with four terminals, source, drain, gate and substrate or body. The drain
and source are heavily doped n+ and the substrate is p-type. The current flows due to flow of the
negatively charged electrons. Thus it is called an n-channel MOSFET.
Depletion Mode: There is a n-type region beneath the oxide layer thus already has a current
flowing path and already form a junction between p-type substrate materials. Therefore it’s really effects
the characteristic MOSFET.

Enhancement Mode: There is no n-type region or channel beneath the insulation part and thus
threshold voltage is higher than the depletion mode type. There is no inversion layer and the weak
inversion layer is established by the holes extracted by the n+ regions such as source and drain and
minority carriers of the p type substrate.
Comparison Curves
JFET MOSFET-Depletion
MOSFET-Enhancement

NMOS, PMOS, CMOS
MOS logic is built upon the MOSFET and especially CMOS which is widely used in VLSI designs.
NMOS is N type MOSFET and PMOS is a P type MOSFET. CMOS is the combination of p-type and n-type
which is widely used in VLSI power designs.
CMOS is the combining PMOS and NMOS MOSFETs to design MOS logic. CMOS Inverter is shown below.
Basic Logic Cell
CMOS Inverter

Threshold Voltage Sub Threshold Leakage and Sub-threshold Current
2 Power Estimation
Integrated circuit design has evolved through some technology clicks and nowadays designers
are capable of VLSI (Very Large Scale ICs) with billions of transistors. Therefore there may be hundreds of
ways for power consuming processes inside the integrated circuits. But we can organize them into three
major categories and some few exceptional cases. Switching power, internal power and leakage power
are the major ways of power consumption. These three can be classified into two Types according to their
nature, Dynamic power and Static power. Dynamic power consists of switching and internal power
components and Static power is compromised with a Leakage power. Power hierarchy is illustrated below.
2.1 Dynamic Power
Dynamic power is dissipated due to toggling effects or state change of the signals. Due to
assertion and desertion of the signal on the signal output capacitance of the output pin will charge and
discharge, thus generating a dynamic power. There are two major components that contribute for the
dynamic power. They are Switching power and Internal Power.
System
Power
Dynamic
Power
Switching
Power
Internal
Power
Static
Power
Leakage
Power

𝐷𝑦𝑛𝑎𝑚𝑖𝑐 𝑃𝑜𝑤𝑒𝑟 = 𝑆𝑤𝑖𝑡𝑐ℎ𝑖𝑛𝑔 𝑃𝑜𝑤𝑒𝑟 + 𝐼𝑛𝑡𝑒𝑟𝑛𝑎𝑙 𝑃𝑜𝑤𝑒𝑟
𝑃 𝐷 = 𝑃𝑆 + 𝑃𝐼 𝑤ℎ𝑒𝑟𝑒 ,
𝑃 𝐷 = 𝐷𝑦𝑛𝑎𝑚𝑖𝑐 𝑃𝑜𝑤𝑒𝑟
𝑃 𝐷 = 𝐷𝑦𝑛𝑎𝑚𝑖𝑐 𝑃𝑜𝑤𝑒𝑟
𝑃𝑆 = 𝑆𝑤𝑖𝑡𝑐ℎ𝑖𝑛𝑔 𝑃𝑜𝑤𝑒𝑟
𝑃𝐼 = 𝐼𝑛𝑡𝑒𝑟𝑛𝑎𝑙 𝑃𝑜𝑤𝑒𝑟
2.1.1 Switching Power
Switching power is generated because of the state changes and toggling of the output signal, thus
charging and discharging the capacitance of the output net. Switching power is based on the load
capacitance. Main factors which effects the switching power intensity id illustrated below,
o Clock frequency
o Activity switching frequency
Clock frequency is that frequency that your system clock run and it may be injected into every
flop of the design. Therefore clock is very important parameter to calculate switching power.
Activity switching frequency is the other important parameter and it is depends on our operations
and may change to instance by instance. Activity data is very important parameter to modern EDA
tool which will be capable of power estimation and reductions. Mostly these activity data is
extracted from the simulation files.

Switching power calculation is based on the following principle and factors.
o C -Size of the total load capacitance
Higher capacitance means more charge (more power) it requires to pull the line to correct
voltage.
o 𝑽 −Driving Voltage
Higher voltage means we need more and more charge (Q)
o 𝒇 − 𝐒𝐰𝐢𝐭𝐜𝐡𝐢𝐧𝐠 𝐅𝐫𝐞𝐪𝐮𝐞𝐧𝐜𝐲
When the switching frequency is high more charge-discharge cycles are happening. Thus more
power is released.
𝑷 𝑺 = 𝑪 ∗ 𝑽 𝟐
∗ 𝒇

2.1.2 Internal Power
Power dissipated the gate when the inputs are charging is an internal power. Internal
power is based on the input capacitance and internal power is also belongs to the dynamic power
category. This is the short circuit stage of power and ground at the transition stage, where both
NMOS and PMOS conducting for a short period of time. Thus generating a short circuit current.
As a brief internal power is the consuming power due to temporary short circuit paths and
internal capacitance
Factors that affect the internal power is,
o Input edge time
o Slew Rate
o Internal Capacitance
o Load Capacitance
Calculation of the internal power depends on the two factors.
o 𝑉 – 𝐷𝑟𝑖𝑣𝑖𝑛𝑔 𝑉𝑜𝑙𝑡𝑎𝑔𝑒
o 𝐼𝑆𝐶 − 𝑆ℎ𝑜𝑟𝑡 𝐶𝑖𝑟𝑐𝑢𝑖𝑡 𝐶𝑢𝑟𝑟𝑒𝑛𝑡
𝑷 𝑰 = 𝑽 ∗ 𝑰 𝑺𝑪

Therefore Dynamic power can be calculated as the sum of switching power and internal power.
And we can optimized the result
𝑷 𝑫 = 𝑷 𝑺 + 𝑷 𝑰
𝑷 𝑫 = 𝑪 ∗ 𝑽 𝟐
∗ 𝒇 + 𝑷 𝑰
𝑷 𝑫 = 𝑪 ∗ 𝑽 𝟐
∗ 𝒇 + 𝑽 ∗ 𝑰 𝑺𝑪
𝑷 𝑫 ⩭ 𝑪 𝒆𝒇𝒇 ∗ 𝑽 𝟐
∗ 𝒇 𝒔𝒘𝒊𝒕𝒄𝒉
2.2 Static Power
Static power is dissipated due to non-ideal characteristic of the transistor and totally the leakage
power. But there is a true potential of reducing unwanted and unnecessary power consumptions via other
power reduction techniques based on the static power.
We consider Static Power dissipated when the device is sitting ideal and it’s totally a leakage
power. At this state the semiconductor devices are powered on but switched off. Therefore it will leads
to a leakage of the devices. Although devices are expected to be on ideal, according to the quantum
physics and Firmy-Dirac equation there may be leakage through the channel of the semiconductor. Static
power is considerably lower than the dynamic power. But due to some important reasons static power is

becoming more and more important part of the VLSI power estimation. Static power is there because of
the non-ideal characteristic of the device where it act as a large resistor allowing a small current to flow
through the device.
𝑆𝑡𝑎𝑡𝑖𝑐 𝑃𝑜𝑤𝑒𝑟 = 𝐿𝑒𝑎𝑘𝑎𝑔𝑒 𝑃𝑜𝑤𝑒𝑟
𝑷 𝑺 = 𝑽 ∗ 𝑰𝒍𝒆𝒂𝒌
2.2.1 Leakage Power
Power dissipated when the semiconductor device is powered on. This is also known as a sub-
threshold leakage most of the time. But leakage is not only consisting with sub-threshold leakage, but also
another components. Some factors affect the leakage power consumption is illustrated below.
2.2.1.1 Threshold Leakage and Threshold Voltage
𝑽𝒕𝒉 − Threshold Voltage
Threshold Voltage of Field Effect Transistor (FET) is the minimum gate to source voltage (𝑉𝑔𝑠)
difference that is needed to create a conducting path between source and drain terminals. This concept
is widely used in MOSFET in enhancement mode and depletion mode. We already analyzed that depletion
mode MOSFET have lower 𝑽 𝒕𝒉 than enhancement mode MOSFET.
At gate to source voltage above he threshold voltage (𝑉𝑔𝑠 > 𝑉𝑡ℎ), but still below saturation, the
transistor is in linear region. This stage also known as Ohmic region where it act like a voltage controlled
variable resistor.
When reffering to the junction field transistor (JFET), the threshold voltage is often called “Pinch-
Off Voltage” instead.
2.2.1.2 Sub threshold Conduction
Subthreshold Conduction, subthreshold leakage or subthreshold drain current is the current
between the source and drain of a MOSFET when the transistor is in subthreshold region or weak inversion
region. Thus the gate to source voltage below the threshold voltage. Most of the time this subthreshold
conduction is considered as the parasitic leakage in a state ythat would ideally have no current. On the
other hand weak inversion region is an efficient operating region and sub threshold is a useful transistor
mode around which circuit functions are designed. But with the rapid technology revolutions leakage
power consumption and subthreshold leakage are becoming vital to VLSI architecture.

2.2.1.3 Transistor Leakage Mechanisms
With the rapid increase in the transistor density, exponential growth of the number of on chip
active devices, the continuous decrease of the 𝑉𝑡ℎ − 𝑡ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 and reduction of the 𝑇𝑜𝑥 gate
oxide thickness result in a significant amount of leakage power consumption in a VLSI design architecture
in deep sub-micron technologies. Totally static power is consumption is generated by leakage current
which flows when the device is not ideal. Leakage power is becoming a critical and vital concern for the
designers particularly for circuits that have low-duty cycles, bursty operation and rely on batteries for long
period of time. Therefore potential of having a leakage in MOS devices is paramount important to VLSI
power architecture. Leakage current is not just a sub-threshold leakage, but consist of several parasitic
components. Basically the leakage can be categorized into two categories.
 𝐼 𝑂𝐹𝐹 − 𝐷𝑟𝑎𝑖𝑛 𝐿𝑒𝑎𝑘𝑎𝑔𝑒 𝐶𝑢𝑟𝑟𝑒𝑛𝑡 – 𝑆𝑢𝑏 − 𝑡ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 𝐿𝑒𝑎𝑘𝑎𝑔𝑒 𝐶𝑢𝑟𝑟𝑒𝑛𝑡
(𝑓𝑙𝑜𝑤𝑠 𝑓𝑟𝑜𝑚 𝑑𝑟𝑎𝑖𝑛 𝑡𝑜 𝑠𝑜𝑢𝑟𝑐𝑒 𝑜𝑟 𝑏𝑜𝑑𝑦)
o 𝐼 𝐷,𝑤𝑒𝑎𝑘 − 𝑆𝑢𝑏 − 𝑡ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 𝐷𝑟𝑎𝑖𝑛 𝐶𝑢𝑟𝑟𝑒𝑛𝑡
o 𝐼𝑖𝑛𝑣 − 𝑅𝑒𝑣𝑒𝑟𝑠𝑒 𝐵𝑖𝑎𝑠𝑒𝑑 𝐶𝑢𝑟𝑟𝑒𝑛𝑡
o 𝐼 𝐺𝐼𝐷𝐿 − 𝐺𝑎𝑡𝑒 𝐼𝑛𝑑𝑢𝑐𝑒𝑑 𝐷𝑟𝑎𝑖𝑛 𝐿𝑒𝑎𝑘𝑎𝑔𝑒
 𝐼 𝐺𝐴𝑇𝐸 − 𝐺𝑎𝑡𝑒 𝐿𝑒𝑎𝑘𝑎𝑔𝑒 𝐶𝑢𝑟𝑟𝑒𝑛𝑡
(𝐿𝑒𝑎𝑘𝑎𝑔𝑒 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑡ℎ𝑎𝑡 𝑑𝑟𝑖𝑏𝑏𝑙𝑒 𝑡ℎ𝑟𝑜𝑢𝑔ℎ 𝑡ℎ𝑒 𝑔𝑎𝑡𝑒𝑠 𝑜𝑓 𝑡ℎ𝑒 𝑡𝑟𝑎𝑛𝑠𝑖𝑠𝑡𝑜𝑟)
o 𝐼 𝑇𝑈𝑁𝑁𝐸𝐿 − 𝐺𝑎𝑡𝑒 𝑇𝑢𝑛𝑛𝑒𝑙𝑖𝑛𝑔
o 𝐼 𝐻𝐶 − 𝐻𝑜𝑡 𝐶𝑎𝑟𝑟𝑖𝑒𝑟 𝐼𝑛𝑗𝑒𝑐𝑡𝑖𝑜𝑛

2.2.1.3.1 Sub-threshold Leakage Current (𝑰 𝑶𝑭𝑭)
The sub-threshold leakage current of a transistor, 𝐼 𝑂𝐹𝐹, is defined as the drain current when |𝑉𝑔| −
|𝑉𝑠| = 0 and 𝑉𝐷 ≥ 0. 𝐼 𝑂𝐹𝐹 is dependent on the various factors such as,
 𝑉𝐷𝐷 − 𝑆𝑢𝑝𝑝𝑙𝑦 𝑉𝑜𝑙𝑡𝑎𝑔𝑒
 𝑉𝑡ℎ − 𝑇ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 𝑉𝑜𝑙𝑡𝑎𝑔𝑒
 Doping Concentration
 𝑇𝑂𝑋 − 𝐺𝑎𝑡𝑒 𝑂𝑥𝑖𝑑𝑒 𝑇ℎ𝑖𝑛𝑒𝑠𝑠
As we mentioned earlier 𝑰 𝑶𝑭𝑭 is consist of 3 sub leakage components.
o 𝐼 𝐷,𝑤𝑒𝑎𝑘 − 𝑆𝑢𝑏 − 𝑡ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 𝐷𝑟𝑎𝑖𝑛 𝐶𝑢𝑟𝑟𝑒𝑛𝑡
o 𝐼𝑖𝑛𝑣 − 𝑅𝑒𝑣𝑒𝑟𝑠𝑒 𝐵𝑖𝑎𝑠𝑒𝑑 𝐶𝑢𝑟𝑟𝑒𝑛𝑡
𝑰 𝑶𝑭𝑭 = 𝐼𝑖𝑛𝑣 + 𝐼 𝐷,𝑤𝑒𝑎𝑘 + 𝐼 𝐺𝐼𝐷𝐿

2.2.1.3.1.1 𝑰𝒊𝒏𝒗 − 𝑹𝒆𝒗𝒆𝒓𝒔𝒆 𝑩𝒊𝒂𝒔𝒆𝒅 𝑪𝒖𝒓𝒓𝒆𝒏𝒕
𝑰𝒊𝒏𝒗 is the current that flows through the reverse biased diode between the drain and the p region
of the transistor, and it is dependent on the junction area between the Source/Drain terminal and the
body and exponentially dependent to the temperature.
Leakage current for the inverse biased diode can be modelled as follows where,
o 𝑈 𝑇 − 𝑇ℎ𝑒𝑟𝑚𝑎𝑙 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 (𝑃𝑎𝑟𝑎𝑚𝑒𝑡𝑤𝑟 𝑙𝑖𝑛𝑒𝑎𝑟𝑙𝑦 𝑑𝑒𝑝𝑒𝑛𝑑𝑒𝑛𝑡 𝑜𝑛 𝑡ℎ𝑒 𝑣𝑜𝑙𝑡𝑎𝑔𝑒)
o 𝐼𝑆 − 𝑅𝑒𝑣𝑒𝑟𝑠𝑒 𝑆𝑎𝑡𝑢𝑟𝑎𝑡𝑖𝑜𝑛 𝐶𝑢𝑟𝑟𝑒𝑛𝑡 (𝐼𝑛𝑡𝑟𝑖𝑛𝑠𝑖𝑐 𝑃𝑎𝑟𝑎𝑚𝑒𝑡𝑒𝑟 𝑓𝑜𝑟 𝑡ℎ𝑒 𝑑𝑒𝑣𝑖𝑐𝑒)
o 𝑉𝐷 − 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝑏𝑒𝑡𝑤𝑒𝑒𝑛 𝐷𝑟𝑎𝑖𝑛 𝑎𝑛𝑑 𝑡ℎ𝑒 𝐵𝑜𝑑𝑦𝑜𝑓 𝑡ℎ𝑒 𝑡𝑟𝑎𝑛𝑠𝑖𝑠𝑡𝑜𝑟
o 𝐽𝐼𝑁𝑉 − 𝑆𝑎𝑡𝑢𝑟𝑎𝑡𝑜𝑖𝑛 𝐶𝑢𝑟𝑟𝑒𝑛𝑡 𝐷𝑒𝑛𝑠𝑖𝑡𝑦
o 𝐴 𝐷 − 𝐷𝑖𝑓𝑓𝑢𝑠𝑖𝑜𝑛 𝐴𝑟𝑒𝑎
Then,
𝑰 𝑰𝑵𝑽 = 𝑰 𝑺(𝒆(𝑽 𝑫 𝑼 𝑻⁄ )
− 𝟏)
𝑰 𝑰𝑵𝑽 = 𝑨 𝑫 ∗ 𝑱 𝑰𝑵𝑽

2.2.1.3.1.2 𝑰 𝑫,𝒘𝒆𝒂𝒌 − Sub-Threshold Drain Current
When,𝑉𝑔 < 𝑉𝑡ℎ, |𝑉𝑑| ≥ 0.1 𝑎𝑛𝑑 𝑉𝑠 = 𝑉𝑏 = 0, transistor forms a weak inversion layer.
Transistor in a weak inversion has a constant voltage across the semiconductor channel and the
longitudinal electric field across the channel is null. Thus there is no drift current generating inside. Instead
the leakage current 𝑰 𝑫,𝒘𝒆𝒂𝒌 is generated by the diffusion of majority carriers across the channel. We can
mathematically model this sub-threshold drain leakage 𝑰 𝑫,𝒘𝒆𝒂𝒌 with the following factors.
o 𝑈 𝑇 − 𝑇ℎ𝑒𝑟𝑚𝑎𝑙 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 (𝑃𝑎𝑟𝑎𝑚𝑒𝑡𝑤𝑟 𝑙𝑖𝑛𝑒𝑎𝑟𝑙𝑦 𝑑𝑒𝑝𝑒𝑛𝑑𝑒𝑛𝑡 𝑜𝑛 𝑡ℎ𝑒 𝑣𝑜𝑙𝑡𝑎𝑔𝑒)
o 𝑰 𝟎 − 𝐼𝑛𝑖𝑡𝑖𝑎𝑙 𝐷𝐶 𝑜𝑓𝑓𝑠𝑒𝑡 𝑑𝑟𝑎𝑖𝑛 𝑐𝑢𝑟𝑟𝑒𝑛𝑡
It is paramount important to look at the exponential dependency of 𝑰 𝑫,𝒘𝒆𝒂𝒌 on 𝑉𝑔𝑠 as well as the linear
offset based on 𝑉𝐷𝑆
𝑰 𝑫,𝒘𝒆𝒂𝒌 =
𝑾
𝑳
× 𝑰 𝟎 × 𝒆(𝑽 𝒈𝒔− 𝑽 𝒕𝒉)(𝒎 𝑼 𝑻 )−𝟏
× (𝟏 − 𝒆−𝑽 𝑫𝑺 ×𝒎×𝑼 𝑻
−𝟏
)
2.2.1.3.1.3 𝑰 𝑮𝑰𝑫𝑳 − Gate Induced Drain Leakage
Gate-induced drain leakage is generated when a large enough gate to drain 𝑉𝑔𝑑voltage is applied
to produce a band to band electron tunneling near the interface between the gate oxide and the
semiconductor of the drain.
2.2.1.3.2 𝑰 𝑮𝑨𝑻𝑬 − Gate Leakage
The gate leakage current is dribbling across the gate to and from the channel, substrate, and diffusion
terminal. This current avoid the treatment of the gate of a device as an ideally insulated electrode. This
gate leakage is basically composed of two leakage components.
o 𝐼 𝑇𝑈𝑁𝑁𝐸𝐿 − 𝐺𝑎𝑡𝑒 𝑇𝑢𝑛𝑛𝑒𝑙𝑖𝑛𝑔
o 𝐼 𝐻𝐶 − 𝐻𝑜𝑡 𝐶𝑎𝑟𝑟𝑖𝑒𝑟 𝐼𝑛𝑗𝑒𝑐𝑡𝑖𝑜𝑛

2.2.1.3.2.1 𝑰 𝑻𝑼𝑵𝑵𝑬𝑳 − Gate Tunneling
This leakage current is generated due to carriers tunneling through the gate of the transistor. There are
two major different way of carrier tunneling.
 Fowler-Nordheim Tunneling
Tunneling into the conduction band of the dielectric. It manifest itself as electron emission caused
by the intense high electric field.
 Direct Tunneling
Tunneling to or from the gate through the forbidden band gap of the dielectric
2.2.1.3.2.2 𝑰 𝑯𝑪 − Hot Carrier Injection
This current is known as Hot Carrier Leakage which is origin whenever a carrier gains
enough kinetic energy and overcome the gate potential barrier. This is more often happen to
electrons since the voltage barrier and effective mass of an electron is less than the one for holes.
2.3 Technology Scaling and Power Estimation Revolutions
2.3.1 CMOS Device Scaling
Although the rate is slowing device scaling is slowing down and deviating from the actual moor’s
law, technology sand device scaling is happening so rapidly. Tehgrefore designers have potential of
inexpensive doubling the number of transistors every two years, which is possible thank to the
miniaturization of devices and the reduction of the cost of computer power due to sales volume. Therfore
desifners have to be careful about the stuff because in near future the transistor miniaturization reaches
atomic level. Some challenges still remain for the visionars.
 Photolithography
 Manufacturing Cost
 Increased power density
 𝐼 𝑜𝑛 𝐼𝐿𝑒𝑎𝑘𝑎𝑔𝑒⁄ current ratio
When we take the leakage current perspective there are positive as well as negative effects. But more
oftenly the compact perspective is negative. That means it will increase the power consumption. With this
device scaling according to the device physics, some leakage currents such as 𝑰𝒊𝒏𝒗 are to shrink, some

leakages such as 𝑰 𝑻𝑼𝑵𝑵𝑬𝑳 , 𝑰 𝑫,𝒘𝒆𝒂𝒌 are to be reduced. Device miniaturization and their impact on leakage
is very important in the near future.
2.3.1.1 Gate Oxide Thickness (𝑻 𝑶𝑿) Scaling
As long as semiconductor device is taking place, the gate oxide thickness and effective channel
length is getting reduced. This thicknes is one of the important parameter to FEt and MOS devices where
it is directly enguaging with the MOS capacitance and all that. Accordign to some papaers the relationship
of the 𝑻 𝑶𝑿 scaling can be illustrated as ,
𝐿 𝑒𝑓𝑓 = 45 × 𝑇𝑂𝑋
Where,
𝐿 𝑒𝑓𝑓 − 𝐸𝑓𝑓𝑒𝑐𝑡𝑖𝑣𝑒 𝐶ℎ𝑎𝑛𝑛𝑒𝑙 𝐿𝑒𝑛𝑔𝑡ℎ
This relationship is usually leds to good 𝑉𝑔 − 𝐼 𝑑transfer behavior. With this device scaling and other
restrictions, Gate Oxide Thickness is limited to some typical level and create a barrier. There are two
leakage components which are affected by the 𝑻 𝑶𝑿 scaling,
o 𝐼 𝑇𝑈𝑁𝑁𝐸𝐿 − 𝐺𝑎𝑡𝑒 𝐷𝑖𝑟𝑒𝑐𝑡 𝑇𝑢𝑛𝑛𝑒𝑙𝑖𝑛𝑔
𝐼 𝐺𝐼𝐷𝐿 current is increase, since the voltage required to generate electron tunneling decreases as gate oxide
thicknes shrinks. Although the 𝐼 𝐺𝐼𝐷𝐿 could impose a limit on scling the 𝑻 𝑶𝑿 , its effect is expected to be
less relevant for digital applications such as the voltage reduces below the energy band gap of the silicon.
Direct tunneling and hot carrier injection is expected to increase significantly as the thin oxide layer
become smaller and smaller. Instead of deployment of Silica as a insulating materials, usage of other
dielectric will reduce the gate oxide thickness massively in the near future.
2.3.1.2 Channel Miniaturization
As long as technology scalig happens the effective channel is reducing and short-channel effects
are expected to worsen when channel length is reduced.
DIBL – Drain Induced Barrier Lowering is one such effect.

In DIBL scenario whwre depletion region of the source or drain extends into the channel of a
MOSFET device, effectively reducing the channel length. This reduction in depletion layer lowers the
potential barrier for electrons, which results in an observable lowering of 𝑉𝑡ℎ, and hence in an increase
on the 𝑰 𝑫,𝒘𝒆𝒂𝒌 current. And also channel miniaturization reduces the junction area netween the
substrate and the Source or Drain, effectively reducing the 𝑰𝒊𝒏𝒗. Channel miniaturization is also closely
related to scalling of the 𝑻 𝑶𝑿 and optimization is paramount importance for the best power performances.
2.3.1.3 Supply Voltage and Threshold Voltage (𝑽 𝒅𝒅 & 𝑽 𝒕𝒉 ) Scaling
𝑽 𝒅𝒅 and 𝑽𝒕𝒉 are two vital transistor characteristics. Design engibeers typically scale the supply
voltage 𝑽 𝒅𝒅 to control dynamic power consumption and power density. In the same time reduction of
𝑽 𝒅𝒅 forces a dramatic reduction in Threshold voltage ( 𝑽𝒕𝒉) inorder to raise the performance gains.
This reduction in 𝑽𝒕𝒉 typically causes a relatively large increase in 𝑰 𝑶𝑭𝑭, while the reduction of 𝑽 𝒅𝒅
reduces the leakage current substantially.
2.3.1.4 Doping Concentration
Electric field at a p-n junction strongly depends on the junction doping. As long as technology and
device scaling continue, the doping concentration is rising, incrementing the overall 𝑰𝒊𝒏𝒗 and 𝑰 𝑻𝑼𝑵𝑵𝑬𝑳.
Device engineers smart enough buil a smart doping profiles for the channel and the transistor terminals
to maximize active current driving through the channel while minimizing the idle current.
2.3.1.5 Source Drain Punchthrough
Punchthrough happens when the depletion regions from the source and the drain join in the
absence of a depletion region induced by gate. Punchthrough happens when voltages between the source
and the body are above then nominal range of 𝑉𝑑𝑑, since this is not the common case for digital circuits.
Therefore model punchthough is very important to ASIC designers.
2.4 Miscellaneous Sources of Power Consumption
Meta stability: output of the flops are becoming undefined
Glitches : Unwanted state changes in nets
Latch Ups : Creating short circuit paths due to misuse

2.4.1 Metastability
Output of the flops are stucked on the undefined states which s caused by the violation of setup
time and hold time.
2.4.1.1 Set Up Time
Amount of time that the input signal needs to be stable before clocking the flop
2.4.1.2 Hold Time
Amount of time that input signal wants to be stable after clocking the flop
Violating tehse time constraints cause the output od the flop to become unknown and variable for short
period of time. After this short time period the output of the flop will fall to 1 to or 0 state regardless of
the desired output.
2.4.2 Glitches
Glitches are unwanted or undesired changes in signals which are resilient (self correcting). Glitches are
caused by delays in lines and propagation delays of cells. Glitches mean more state changes in the
signal,thus more switching, internal and leakage power dissipations. Unfortuantely glitches can be
propagated through combinational logics cells until being terminated at a flop edge. Therefore whole
system will put into error disabled state. Therfore identifying glitch sections and avoid them is paramount
important.
2.4.3 LatchUps
LatchUps is a short circuit path between supply and the ground. Large amount of power can be
dissipated due to latchups.

2.5 Power Estimation Techniques in Electronic Design Automation (EDA)
Electronic Design AutomationEDA Power Estimation Methodologies
 Mostly based on the tech libraries
 Based on two major calculations
 Activity
 The number of toggles per clock cycle on the signal, averaged over many cycles
 Probability
n
OUT
IN
ppnn
p

 Percentage of the time that the signal will be high

3 Power Reduction
VLSI power is becoming paramount important to the electronic world because of its emerged significant
in both design and consuming stages. With the rapid technology evolution of last couple of decades,
increases in transistor density and speeding clock frequency have emerged inherent strength of power
architecture of VLSI designs. And also seeking trends of consumers appetites in high performances,
portability and embedded applications are clamoring for new power architecture of VLSI designs.
We can classified them into three main categories based on that.
 Device Engineering
 Circuit Engineering
 System Engineering
Device Engineering
This refers to techniques that are implemented on the underlying transistor that form digital
circuitry. This is mostly involved with the transistor level components.
Circuit Engineering
These refer to techniques that are applied to gate/logic level, which are clusters of transistors that
perform a small computation like NAND, NOR etc.
System Engineering
These are referring to techniques that can be applied to macro-blocks that are part of a big data
path or micro-chip.
3.1 Dynamic Power Reduction
Dynamic power is very important and most contributing power factor for total power
consumption. Reduction of dynamic power have already researched and implemented in lots of ways.
Thus rather than a radical solutions, improvements and incremental developments are taking place all
around the world to mitigate dynamic power. But most of the time dynamic power reduction techniques
can be deployed in synchronous electronic circuits which are synchronized with the system clocks. But we
know that there is a great potential for them to be used in asynchronous circuit also since switching and

internal power dissipations are happening in asynchronous circuits. Dynamic power reduction techniques
such as clock gating has emerged its counterpart as advanced dynamic power reduction technique.
3.1.1 Clock Gating
Each time a flop is toggling, immersive switching power and internal power are dissipating
out of the semiconductor devices. When we consider millions and billions of such gate level devices large
amount of power is wasting due to unwanted usage of toggling and flops. Thus provide a state changes in
the intermediate combinational clouds and dissipate more dynamic power. Dynamic power is generated
due to unwanted clock toggles, thus charging and discharging internal and load capacitance in internal
and switching power dissipation respectively. Changes in the combinational logic is happens only when
flop changes its state, thus preventing flop to be toggled , when no state changes are happening is not
really effect the switching power of the combinational clouds. Changes of signal state of the combinational
clouds are happening only when flop change its state.
Local clock gating is creating enable and allow clock to make a change/toggle in flop only where
it is necessary. Therefore we stop providing the clock to flop by making an enable. But how we can we
really decide enable signal, because it’s not in the real design. Therefore we need to compose a signal
with other signals. Having an independent and individual enable is good for simple designs, but highly
complex designs compromising with millions of transistors are not sustainable to such implementations.
Therefore composing an enable and strengthening them is bit challenge in the high level designs.

3.1.1.1 Local Clock Gating
Local clock gating is making enable, and gated it with an actual system clock and, gated clock will
be fed as the clock to flop. Thus prevent unwanted toggling of the flop. But local clock gating has no mean
unless we have a better algorithm to decide new enable. General implementation of clock gating is as
follows.
There are two types of local clock gating.
o Latch Based Clock Gating
o Latch Free Clock Gating
AND
FLOP
D Q
Enable
Clock
Data IN Data Out

3.1.1.1.1 Latch Based Clock Gating
But this will cause to unwanted glitches in the design. Therefore special clock gating mechanism
is used.
3.1.1.1.2 Latch Free Clock Gating
Dynamic power reduction is very important because,
 Clock tree consume more than 50% of dynamic power consumption.
o Power consumed by combinational logic whose values are changing on each clock edge
o Power consumed by flops
o Power consumed by the clock buffer tree
AND
FLOP
D Q
Enable
Clock
Data IN
Data Out
Gated CLK
AND
FLOP
D Q
Enable
Clock
CLK
Data Out
Data
D Q
FLOP
Gated CLK

 Asynchronous Logic Circuits which is not driven by the global clock, is also changing de to state
changes in the flops.
For the further explanations, sometimes the flop with a clock gating cell can be compressed as
integrated into the flop as follows,
3.1.1.2 Advanced Clock Gating Techniques
3.1.1.2.1 .1 Multi-Level Boolean Logic
Multi-Level Boolean Minimizations
3.1.1.2.1.1 Satisfiability Don’t Care (SDC)
Design spots where certain input/ input combination to a circuit can never occur. There may be
possible causes for the SDC conditions.
o We can represent node using primary inputs and intermediate variables (𝐵 𝑛+𝑚
)
o The intermediate values depends on the primary input
o Therefore, not all the min-terms of the 𝐵 𝑛+𝑚
can occur
As a example,
𝑦 = 𝑎 + 𝑏 , 𝑡ℎ𝑒𝑛 {𝑦 = 0, 𝑎 = 1, 𝑏 = ~}𝑤𝑖𝑙𝑙 𝑛𝑒𝑣𝑒𝑟 𝑜𝑐𝑐𝑢𝑟 (𝑆𝐷𝐶)
SDC is one of widely used techniques in multi level Boolean minimization.
FF
D Q
Enable
Clock
Data IN Data OutEN
CLK

3.1.1.2.1.2 Observability Don’t Care (ODC)
Design spots where local changes cannot be observed at the primary outputs. Observability don’t
care situations will be created when,
 Signals at pre-specified observation points (primary outputs) are outputs from some intermediate
gates
 Changes of some inputs to the intermediate gates may not change the output
 Therefore these changes are not observable
As a example,
𝒚 = 𝒂 + 𝒃, 𝒘𝒉𝒆𝒏 𝒂 = 𝟏, 𝒄𝒉𝒂𝒏𝒈𝒆 𝒐𝒏 𝒃 𝒊𝒔 𝒏𝒐𝒕 𝒐𝒃𝒔𝒆𝒓𝒗𝒂𝒃𝒍𝒆
New Trends of Clock Gating with Multi level Boolean logics
 Stability Conditions (STC)
 Observability Don’t Care (ODC) Conditions
Stability Condition has derived through the SDC techniques in Multi level Boolean logics. Amount of power
saving depends on the assertion time (duration) of the enable signal. Shorten the enable signal duration,
more power saving can be taken place.

3.1.1.3 Advanced Clock Gating
3.1.1.3.1 Stability Condition (STC)
Stability condition is defined with the stability of the input to the flop when upstream flop is
stable, no new data or changes come to the downstream flop. If the input to the flop is not changing with
the (Stable) for a period of time, there is no use of toggling the flop for state changes. In such situation
input to the flop is just remain constant thus output of the flop also stable without changing. Therefore
we can shutdown that flop with clock gating. Now instead of pure local clock gating, we have a
logic/enable to gate the clock. Then we can reactivate
the flop by providing the clock, when a change
occurs.
 Advantages: Reduced activity on clock buffer
 Disadvantages: Area and power overhead with the new flop and clock gate
Sequential analysis techniques can be applied to apply to find the enable for stability conditions (STC).
In this techniques we usually called flop is looking forward, basically upstream with relevant inputs.
EN1
Upstream
register
Downstream
register

Digital Circuit before STC
EN
CLK
CLK
EN
Digital Circuit after STC

There are Situations where the output of the flop is changing or staying constant, but that output
is not used in the downstream and read only for a certain time period of time. Then toggling and state
changes of the flop for entire time period is not required. Therefore we can shut down that flop for a
relevant time period where the output of the flop will not be read and unnecessary. And we can reactivate
the flop when someone is actually reading its output.
Here also we have an area and power overhead and with ODC techniques we can reduce in both
clock and data path.
SEL
0
1
Q X
Digital Circuit After ODC
Digital Circuit Before ODC
0
1
Q

3.1.1.4 Clock Gating Efficiency and Enable Strengthening
Enable Strengthening
 Most of the devices have explicit or already instantiated clock enables in the digital designs
according to records advanced SOC designs such as mobile application units is recommended to have
around 90% of clock gating cross designs.
 Although the digital designs consist of explicit or instantiated clock enables, all of them are not
efficient and provided an efficient clock gating.
 Therefore modern approaches are focusing on finding a new enable which strengthen the existing
enable.
 This process and new enable are often known as Enable Strengthening and the Strengthened
Enable respectively.
 Basis behind this approach is to strengthen the existing one with new one, if the percentage of
power reduction through the new enable surpasses the existing enable.
There are two types of strengthening methodologies based on the logic they are acquired.
o Strong STC
o Strong ODC
Strong STC
SEL
0
1
Q X
CLK

In a gated flop, if the input is not changing for a period of time and the flop is still clocking or
toggling then we can find out a condition for causing input to be stable. We can use this new logic to
strengthen the existing enable.
Strong ODC
In a gated flop, if the output is not read for a period of time but the flop is still clocking, we can find out
the conditions for output not t be observed. Then we can enable the existing enable with this new logic.
This is known as strong ODC.
3.1.1.5 Memory Power Reduction
Most off the digital systems are associated with memory systems. There are different techniques
for memory power reduction.
o Remove redundant read
o Remove redundant write
o Memory as steering point for register power reduction
o Light sleep power reduction
3.1.1.5.1 Redundant Read Removal
Any read access occurring when the memory output is not observable is a redundant read and
can be removed based on the ODC technique.
And also if the read address is stable then every read after the first one is redundant, if no new
address write is taken. This is based on the STC techniques.

3.1.1.5.2 Redundant Write Removal
If the data and write addresses are stable, then ever write access after the first one is redundant
and can be removed.
There are techniques which are lightly used in digital gating designs.
o Memory as steering point for register power reduction
o Light sleep power reduction

3.2 Static Power Reduction
In the past few decades dynamic power is the major concern of design engineers due to fastening
the system clock and frequency. But prevailing technology revolution with advanced fabrication
techniques with technologies such as photolithography, the device or technology scaling is happening
with an exponential growth. Thus semiconductor devices scale down and leakages are becoming
paramount important for the overall power consumption. Therefore VLSI power architecture predicts that
static power (Leakage Power) will become a dominant component of the power architecture and most
researches are carrying through to support that concept. Power gating are effectively mitigating leakage
losses and becomes a major static power reduction technique.
Comparison with Dynamic Power
Technology world has predicted that how leakage losses will emerge their counterpart as
a major power factor.

Technology scaling is happening rapidly in the recent years; even 10nm level depth has already conquered
the semiconductor design world. Bin near future there may be a barrier to grow further because device
scaling has already forms restrictions on scaling down from nano scale towards atomic level.
We need to have a good understanding about the leakage power leverages to go for new
techniques.
Emerging Leakage Power in ASIC and SOC (System on Chip) Designs
Emerging Leakage Power in Microprocessor Design

Static power reduction techniques are the most influential techniques for the design architecture and
VLSI organization. Therefore for analytical purposes we can say that static power gating techniques can
be applied in three different levels of the digital designs. Therefore W can classified them into three main
categories based on that.
 Device Engineering
 Circuit Engineering
 System Engineering
Device Engineering
This refers to techniques that are implemented on the underlying transistor that form digital
circuitry. This is mostly involved with the transistor level components.
Circuit Engineering
These refer to techniques that are applied to gate/logic level, which are clusters of transistors that
perform a small computation like NAND, NOR etc.
System Engineering
These are referring to techniques that can be applied to macro-blocks that are part of a big data
path or micro-chip.
Sources of Static power, basically leakage power has already discussed in the previous chapter.
There are two major methods of static power reduction
1. Voltage Islands
2. Power Gating
Although the voltage islands are use for some extent power gating is the most preferred methods for
the static power reduction.

3.2.1 Power Gating
The basic strategy of power gating is to establish two power modes,
 Active Mode
 Low Power Mode
And switch between these power modes where necessary. Establishment of two power modes is a
pragmatic remedy for accurate switch between these modes at the appropriate time and in the
appropriate manner to maximize power saving while minimizing the impact on the performance.
Therefore switching and controlling process is also complex.
 Active Mode
 Sleep (Low power mode)
 Wake Up
Power gating techniques essentially increase the effective resistance of leakage path by adding sleep
transistor between logic stack and power supply rails. Transistor stacking techniques are widely concerned
in the power gating techniques. Power gating is basically cut of the power where unnecessary. More often
these power gating or sleep transistors are shared among the multiple-logic stacks to reduce the number
of leakage paths. Sleep transistors are important design of the power gating consideration. Sharing the
transistor effectively creates two new power nets, Gated- 𝑉𝐷𝐷 (𝑔𝑣𝑑𝑑𝑣) and Gated –Ground (𝑔𝑣𝑠𝑠𝑣),
which replace 𝑉𝐷𝐷 and GND for power gated logic stack.
3.2.1.1 Sleep Transistors (Switches)
3.2.1.1.1 Switch Types
There are two types of sleep transistors.
1. Head Sleep Transistor/Switch
2. Foot Sleep Transistor/Switch

𝑔𝑣𝑑𝑑𝑣 is connected to 𝑉𝐷𝐷 using the head sleep transistor.
𝑔𝑣𝑠𝑠𝑣 is connected to GND using a foot sleep transistor.
3.2.1.1.2 Switch Sizing
Smaller Switches: Smaller area, large resistance and good leakage reduction
Bigger Switches: Larger area, smaller resistance and relatively low leakage reduction

3.2.1.1.3 Switch Placing Architecture
Switch in Cell: Switch transistor in each standard cell. Area overhead is a disadvantage and physical design
easiness of EDA is an advantage
Grid of Switches: Switches placed in an array across the power gated block. 3 rails routed through the
logic block (Power, GND and Virtual).

Ring of Switches: Used primarily for legacy design where the physical design of the block may not be
disturbed.
3.2.1.1.4 Signal Isolation
Powering Down the region will not result in crowbar current in many inputs of powered up blocks.
None of the floating outputs of the power-down block will result in spurious behavior in the power-up
blocks. Clams will add some delays to the propagation paths.
Basic Power Gating Modes
o Fine Grained Power Gating
o Coarse Grained Power Gating

3.2.1.2 Power Gating modes
3.2.1.2.1 Fine-Grained Power Gating
Process of adding a sleep transistor to every cell is called a fine-grained power gating. This to
be turned off imposes a large area penalty. And also individual and independent gating of the power of
every cluster of cells form timing issues introduced by inter-cluster voltage variation that are difficult to
solve. This technique encapsulates the switching transistor as a part of the standard logic cell. Mostly the
gating transistor is designed as the high 𝑉𝑇.
3.2.1.2.2 Coarse-Grained Power Gating
Implementation of grid style sleep transistor, to stack of logic cell, which drive cell locally through shared
virtual power network, is known as coarse grain power gating.
There are two ways of doing power gating with coarse-grain approach.
 Ring Based
o Power gates (Switches) are places around the perimeter of the module that is being
switched off as a ring
 Column Based
o Power gates are inserted within the module with the cells abutted to each other in the
form of columns
3.2.1.3 Power Gating Factors
 Power gate size
 Gate control slew rate

 Simultaneous Switching Capacitance
 Power gate leakage
3.2.1.4 Synchronous and Asynchronous Power Gating
Efficient Power Gating with Asynchronous Digital Design
 Clock gating for dynamic power reduction which reduce the power consumption of idle section of
synchronous circuits
 Asynchronous circuits has a inherent strength of data driven capability and active while
performing useful tasks
 Asynchronous circuits implement the equivalent of a fine grain power gating network
 Power gating can be efficiently implemented in Pipelined flows
3.2.1.5 Power Gating/Controlling Mechanisms
There are two type of Power gating mechanism because of their state preservation mechanism
 Non-State Preserving Power Gating
 State-Preserving Power Gating
o State Retention Registers
3.2.1.5.1 Non State Preserving Power Gating
 Non-State Preserving Power Gating
 Cut-off (CO)
 Multi-Threshold (MTCMOS)
 Boosted-Gate (BGMOS)
 Super Cut-off (SCCMOS)
3.2.1.5.2 State Preserving Power Gating
 State Preserving Power Gating
 Variable Threshold (VTMOS)
 Zigzag Cut Off (ZZCO)

 Zero Delay Ripple Turn On (ZZRTO)
 State Preserving use some retention registers to store states.
3.2.1.5.2.1 State Retention Techniques
 Software Based Register Read and Write
 Scan Based approach based on using scan chains to store state off chip
 Retention Registers
Retention Registers
When power gating taking place we have to retain some critical register content (FSM
State).Saving and restoring state quickly and efficiently is the faster and power efficient method to get the
block fully functional after power up. There can be various methods for state retention.
 DSP Unit: data flow driven DSP unit can start from reset on new data input.
 Cache Processor: This mechanism is good for large residual state retention.
3.2.1.6 Software/Compiler vs. Hardware Based Power Gating
Since power gating is directly impacted on the design organization and architecture there can be
two types of power gating. Software/compiler driven power gating and hardware based power gating.
Most Researches are ongoing to support those two techniques and most of the time ASIC level/hardware
level power gating is emerging its counterpart as best. Basically the basis is on the controlling mechanisms
of gating and state preservations.
No Power Gating

3.2.1.7 EDA Power Gating
Designp power gating library cells
Determine which blocks to power gate
Determine state retention mechanism
Determine Rush Current Control Scheme
Design power gating controller
Power gating aware synthesis
Determine floor plan
power gating aware placement
clock tree synthesis
Route
Verify virtual rail electrical charateristics
verify timing

4 Power Verification
Power verification process in the EDA is consisting of the steps of analyzing, monitoring and
validating power rules related to EDA tool. Each and every power estimation and reduction rule and
algorithms should be test and check against digital cores. It is essential to have verification process in the
EDA development cycle e to ensure that the software infrastructure is working properly for electronic
prototyping.
For the design approach and test case generation we have used HDLs such as Verilog, VHDL etc.
Most of the time PERL, C++, and excel is used to analyze the results provided by the EDA flow. As an
example
4.1 Verification of Power Monitors
Power monitors where all mathematics is physics come to engineering, and solve a problem of
reality. It is Practical problem of a power estimation flow that is solved with power monitors. When we
have places where probability of the mathematic is always not true, power monitor comes up with a
solution. As a example,
 A and B nets have simulation data
 C does not have a simulation data
According to the mathematical formulas,
A
B
C
AND
A
B
C

If A, B are two independent event,
𝑃( 𝐵
𝐴⁄ ) =
𝑃(𝐴 ∩ 𝐵)
𝑃(𝐴)⁄
If those events are independent
𝑃( 𝐵
𝐴⁄ ) = 𝑃(𝐵) =
𝑃(𝐴 ∩ 𝐵)
𝑃(𝐴)⁄
𝑃(𝐴 ∩ 𝐵) = 𝑃(𝐴) ∗ 𝑃(𝐵)
In the Above example,
𝑃(𝐴) = 1
2⁄
𝑃(𝐵) = 1
2⁄
∴ 𝑃(𝐴 ∩ 𝐵) = 1
4⁄
Actual Scenario
𝑃(𝐴 ∩ 𝐵) = 0
This causes to huge estimated power variations and provide a erroneous values to propagated
nets.
Power Monitor Solution
A
B
𝑁 𝑡ℎ
Slot

𝑃(𝐴 ∩ 𝐵) = ∑ 𝑃(𝐴𝑖 ∩ 𝐵𝑖)
𝑁
0
Divide the simulation time into the fastest clock slots. And find the probability for each and every
portion and integrate them together.
5 Power Fix
Power fix is the process of fixing power issues in the design and redesign it using reduced techniques with
a background checks. SEC (Sequential equivalence check) is used to navigate and find the effect of
associated techniques and new design and compare them against the previous outcomes.
More Reading …..
iSaac- Intelligent Systems and Advanced Computing

Low power electronic design

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