1. ISSUE 4
c NTERNATIONAL
DAVID BERGMAN • NORBERT AMMANN • CLEMENS LASANCE
GARY FERRARI • JACK FISHER • CARLOS FERNANDEZ • JEFFRY F. KOON
DANN GUSTAVSON • CHARLIE MULLEN

2. 9
1
Our editorial panel introduced
SECTION 1
FUTURE VISIONS AND CURRENT CONCERNS
The Problem Of Interconnection And The Impact Of Printed Circuit Board Technology On
Integrated Circuit Package Development
James Hayward AMD
Microvias-Where Silicon And Printed Circuit Technology Meet
O,arles L. Lassen Prismark Partners
Supply Chain Transformation
Susan Hancock Siemens
Components In PCB Manufacturing: Future Challenges
Shobha Gupta Motorola
An Advanced Technology For The Test Of High-Density MCMs, Chip Carriers,
Ceramic Substrates And Hybrid Circuits
Karl F. Zimmermann CK Technologies
Application Specific Reliability Of IC Packages
Patrick Counihan and Steve Greathouse Intel
T
COMPONENT TECHNOLOGIES
• , or Poftr Modules In Avionics Appllcatlons
Mike Spadaro et al Raytheon
Assembly And lntwconnect Rellablllty Of BGA Assembled Onto Blind Micro And
i r Pad
Andrew Mawer et al Motorola
• 1 , .. .,, - Sul2 Packaging
0 atrick Dall'Agnese and Hans Bauer Siemens
6 SE CTION 3
0
:s
T H ERMAL MANAGEMENT
Semiconductor Thermal Trends And Importance Of Thermal Resistance
Bernie Siegal Thermal Engineering Associates and Tom Tiirter AMD
·conductor Device Temperature Measurements Using Electrical Parameters
David L. Blackbum NIST

3. 84 SECTION 4
89
95
103
109
PCB DESIGM
High Speed Design: Controlling Impedance For Signal Integrity And EMI
William D. Kimmel and Daryl D. Gerke Kimmel Gerke
GenCAM Addresses High Density Circuit Boards
Dieter Bergman IPC
Digital Goes Analog
Herry Veendrick Philips
Design And Process Optimization For 1.0mm Pitch CCGA
Marie Cole et al IBM
E 5
PCB MAM UFACTU RI MG
Joe Smetana DSC Advanced Technology
Franz Cordes and Ron Huemoeller Amkor Technology
ogy
Jack Fisher ITRI and Bob Forcier Nelco International
Steve Feltham, Jeff Wallace and Bill Wasson Automata International
no IN SIMOV'• Tcdmology
Hein1 BleiweiB end Eddy Roelants Siemens
Octavian lordache Viasystems
Wallace D. Doeling Sequent
y, Q ck T
174 S E C T I 0 N 6
PCA
rs
17 c Automation: Providing F1exibility Without Compromising Quality Or Productivity
18
Steve ~mer CS2
P s e rlnttng And Characterisation For Chip Scale Package (CSP) Assembly
Julian Partridge end Rick Gunn XeTel

4. 193 Assessing The Manufacturability And Reliability Of Electronla Assemblies Utilising
u Arrily ackages And High-Density Printed Wiring Boards
Petri Savolainen Nokia
196 S E C T I 0 N 7
201
217
22
SO L DERING TE C HNOLOGIE S
CCAMTF Phase 1And 2 Evaluations Of Alternative Surface Finishes And Conformal
Coating For Circuit-Card AssembJies: Results Of 85/85 And Thermal Shock Testing
Ronald L. Iman Southwest Technology Consultants Jeffry F. Koon Raytheon Tl
On The Economics Of Controlled Atmosphere Soldering
Johann Weber Zollner Elektronik and Tilman Schwinn Messer Griesheim
Influences On Solderablllty And Cleanliness By The Use Of Various Copper Protection Media
Gordon 0. Barr Pasg Corp and Koen Hollevoet lnterflux Electronics
226SE CT I O N 8
231
235
239
TEST
Developing A Complete Test Strategy-Three Key Elements
Dann Gustavson Solectron
DFT Enhances PCB Manufacturing
Gunnar Ca~sson Ericsson
Optimising The Use Of Electronic Data For Programming AOI Machines
Richard Frisk Lloyd Doyle
242 Acoustic Mlcroimaging In Microelectronics
Keny D. Oren ITT Aerospace Communications
247 Reliability of (63/37) Solder Bumped Fllp Chip Components on FR5 Board
Aulis Tuominen Nokia and Jarmo Miiattiinen and Petteri Palm Elcoteq
252 S E C T I 0 N 9
257
265
EMS / CEM
Integrating Technologies To Bring Speed To Market
Michael Durkan Dovatron International
Maintaining Part Data Integrity In Contract Manufacturing: A Logistics Challenge For The Enterprise
Miriam D'Souza Celestica 1md Donald N. Frank DN Frank Associates
269 Quality Considerations Of Channel Assembly
Dale W. Wilhite and David L. Anhder IBM
273 Manufacturing Applications Become Strategic Solution
BNce Reinhart Kimball Electronics
276 Advertiser Index
FUTURE CIRCUITS INTERNATIONAL

5. na:d the U.., EnVlfOlllOO'lla) ProtecuonAff;oc'/s 1995SlratosphencOzone
Pl'rualllAward~asthe fust ~dtheSanchaPresidenlsGoldQ.ialilyAw.ml
Koon!usauthorerl more than 40 technical papersonsoldenngandelearonics
HehasaB.S.degree in Cllerrucal Engmeenngfrom Clemson University.
CLEMENS LASANCE
~ Reward. L.boratoria, The Nctherl.nds
Afterfinishing hisstudies in physicsat the Eindhoven
Technical University in 1969, he joined Philips
SerrucondUClors,to work onsolidstate diffusion. In 1900,
he took up a post within the HeatTransferGroup, part
of the Centre of Manufacturing Technology (CFT).
From 1984 onwards, his main focus has been the
• managementofelectronicsystems. In 1996,he switched to Research,
c ,., ·~ a long-term research program in thlS field. Among.st his more
R&O acuV1ties, he contributedsigmficamly10 theSU<X:e$ ofthe ESPRIT
DElPHI
past few years he lecturedat the NATO AdvancedSrudyInstituteand
a:uda> the ProgramChairman ofthe Ftl'Sl EurothermConference onThermal
gement and V1ce-Cruurman of the second one. He is the European
son tor the SEM!THERM and !THERM conferences. He is also oneof the
Associate Editors of Electronics Cooling Maganne. He presented inV1ted
muresa1. severaloccasaons,andauthored andco-authored more than 30 papers
'lapterson varioussubjectsofelearomcscooling. ClemensJM. Lasance
" Re;earch laboratonesProf Holstlaan 4WB 31 5656AAEindhovenThe
'.'. erlands tel· +31 40 274 27 95 fax: +31 40 274 42 88 E-mail:
smte®nat.lab.research.ph1hps.com
CH A RLES MULLEN
Senor lncMby Consult.nt. Ekctronics Specialty
fullenhasa PhDdegree in Organizanonal Psychology from the California
Scio o[Professional Psychology. He received the OutstanchngDissenation
A <l for his research project on processesorganizationsemploy in forming
str.lli:gtc alliances. Previously, Dr Mullen was DirectorofSalesand Marketing
r electromcs contract manufactunngcompany based in Hong Kong. He
_,,alsoworked inaccount management, sales,and product managmemin the
·:miesandsemia:inductor!lldusuy.Dr Mullen managescoosultingandreseruch
p: ects atTA, oversees primary research, analyzes data, interprets the results,
;md recommends successful contract manufactunng and other strategic
~.
GARY FERRARI
Exec.utiYc Director, IPC DcsisncnCouncil
Gary Ferrari IS the Executive Director of the Institute
for lnterconnecungand PackagmgElectronicCircuits
(IPC) DesignersCouncil. Hehas more than 30 years of
expenence Ill electronic packaging withan emphasis
on pnnted wiring board (PWB) design and manufac-
tunng. As a former Manager of Technical Suppon
. Quahty Assurance at Tech Circuits in Wallingford, Connecticut, he
'lided volunteer mstructor semces for various !PC-sponsored technical
rkshops, and has chaireda number of!PCtechrucal commmees, including:
Pnrued BoardDesignCommittee,the ComputerAided DesignSubcorru:nittee,
Printed Board Complexny Subcommittee and the lPC-D-275 Design
' lx:ommittee.
Ferrari has written numerous technical anicles,and has provided Design
tanufaeture(DIM)consultingservices to the indUStry. ln 1990, Ferrariwas
iored with the !PC PresidentsAward, recognizing his contributions to LPC
~ the electronic interconnection industry.
...,..........tWr............,..
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PUTUlll CIRCUITS INTERNATION AL
OT......... ,........Llil. 1991
TI,...-tcnlfnl ol tllis pJ.lc.,,, ft PIOIO<tftl byc_.,,N. I.a ~ ol
;,J,ich..-i.bk""""llw~ ...."""'~ No,,...ol.... M!r
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"'b.,...,ro«.... ~~'-'=ti.~ -dnsC<...i-t.:-
wllhoul dw pnor _ _, ol dwc~ _,
Publiehed by
T..i...&o,y ,........_Lad
Floor Gt! t-io- s...,~
London SWIE W UK
Ttl ~4) 171447 7777 F.. (+44 CO 171 «7 7788
£-a~.,,,
Hoii,Ko.,
c.. it. Wor, (HIO Lid A.I B. 8/F Boci
r.P,,,1nc1..-1c~ s1 r..,"'*Rd.
T• Po. Hori, ~
Oper1tiont OINctor
Nol<ki Wood
OM.lollll M.,,..er
St,,1 81.c~lod
• V ' t .. ,.,CI,; '"
Edito<MI M.n.,c.
Rd..d ·lv.o'°'
lvtDincto<
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VI.ale ~effort "" been ....0. to - tl.t - oS the
contmlt ol ti.It bool<. t!.c ~ d oc:cept no tt_.;b;lity loo-...,
"""" 0< °""'tlon1, °'loo-.,.,Iott Of do-,c, con~ or olhcrwisc.
...fftt.d 01 o ,.,ult of °"Y motcriol here ~.
ISSN 1368..C361
Photo credits:
Front Cower. IBM - John Church,,,.,./T°"'Wry
Sections1throush 9: The lnllltutt I"' lntcrconn«tins ond
Poc~•9in9 Elcctronlc Cimiitt

6. ith increasing
emphasis on
miniaturization,
diip-on-board
'COB) technology is well suited for
•Pplications where thermal pertor- ch ip -0 n-B0 a rd pa ck ag i ng f 0 r
ance, package density, vibration,
rid shock requirements are stringent.
COBassembly techniques can be
-tegrated into the normal surface-
...,ount assembly process, where
sh-density packaging is used.
his paper describes an application
r COB technology in II high-
density, single-output DC-DC power
""odule for airborne radar appli-
C'ltion. The reason for using this
'echnology was to develop a reliable
attachment method for assemblies
that would be subjected to a typical
0 -year life environment for military
epplic:ations. Three 600-watt power
..,odules, that demonstrate signi~-
ant packaging enhancements in
~, output, and power density, were
built and tested. A reliable COB
u sembly to meet typical 10-year
~~was demoustiated.
Mi ke Spadaro
Mark Stalle r
David Stark
Puligandla
Vlswanadham
Raytheon
Power Modules •1n
Avionics
Applications
1. Introduction
The technique used to directly
bond a semiconductor device to a
printed wiring board (PWB) or a
substrate is termed "chip-on-board~
(COB). This term is only ageneric
description of the entire process.
Strictly speaking, COB can be
definedas an interconnectstrucrure
where a silicon device, devoid of
extraneous packaging structure
(suchas die-rirlead framearurlt, lead
framebody, and moldingcompound
or package) is attached to the
substrate. COB implies elimina-
tion ofa levelofinterconnectionin
the packaginghierarchy, and hence
falls into thecategoryofdirectchip
attach(DCA). Further,COBdenotes
one or more ofthe many configu-
rations in which the device is
attached to the carrier orsubstrate.
These include such interconnec-
tionschemes as controlledcollapse
chip connex:rion(C4), tape automated
bonding(TAB). and flip chipattach
(FCA). It is difficult to determine
which particularscheme isinvolved
when one refers to generic COB,
which may be confusing to the
uninitiated. However, the general
consensus is that COB refers to a
silicon device, with its active side
facing up, meclianicallyattached to
the substrate with adhesive or
solder, and electrically intercon-
nected to the substrate pads with
aluminum or goldwire.
With increasing emphasis on
miniaturization, COB technology
iswell suited for applications where
thermal performance, package
density, vibraLion, and shock
requirements are stringent. COB
technologyoffersseveral advantages.
The processes are proven and
established. Plasma cleaning
techniques and improved control
proces.5 ofultrasonics have ensured
good wire bonding yields. l.ow
temperature gold wire bonding
enables highvolume production.
Several consumer electronic
hardware manufacturers have
found this technique to be cost
effective. COB assembly techniques
can also be integrated into the
normal surface mount assembly
process when itiscompatiblewith
processchemicals(fluxes, cleaning
solvents, etc.).
This paper describes an appli-
cation of COB technology in a
high-density, single-output DC-
DC power module for airborne
radar application. The reason for
usingthistechnologywastodevelop
a reliable attachment method for
assemblies that wouldbe subjected
to atypical 10-year lifeenvironment
for military application. The paper
also presents design requirements,
process, mechanical packaging,
assemblyand reliabilitytest results,
andconclusions to demonstrate the
application ofCOB technology.
FUTURE CIRCUITS INTERNAT I ONAL
SI
i. 600-Watt DC-DC
Power Module
This powermodule demonstrates
significant packaging enhance-
ments insize and weight over the
currentmilitarymodulesinproduc-
tion. The 600-watt, single-output,
militaryunit (Figure 1) was devel-
oped for airborne radar power
systems primarilyas slat-mounted
on a liquid cooled-coldplate. Its
compactsize and full complement
of hermetic semiconductor parts
meettheaggressiveweight, thermal
performance, and failure criteria
needed for an uninhabited fighter
environmenl. Table 1 shows the
performance requirements of the
module.
The module operates as per
MIL-SID-704E, 270-voltDCpower.
Module input power is routed
through a flexible circuit, directly
soldered co a multilayer board.
This circuit board serves as the
primarysideofthe powerstage. The
switching technology chosen is
full-wave bridge, zero voltage with
averagecurrent modecontrol. Low
profilemagnetics, along withsurface
mount packaging, comprise 100
percent of the mechanical layout.
High-current lRF-450 MOSFET
diepackagedin 28-pinLCC(Jeadless
ceramic chip carrier) packages
function as the full-wave bridge
switches. To obtain thermalcycle
lifefor LCCswitha military temper-

7. F~ 1. Curra1t p.,_,. Module Without the COB.
Table 1. Pctfonnancc Requirements
Wei,ht
270volb DC_______
nv•t 55 •m~n______
225W/cubtr. inch
4.10 • 2.00 • 0.340 1nchn
85%1yp1c.1I
0.225 pounds
T1blc t. Rcqulrcmcnll for Typlcal 10-Yur Avionics Service Life
Tnt
Tcmpcatuoc/humodty
Conditions
Temper.W~ rtn,e: --40° to 100°C
c~ dlJf.000: 30 m111ute clwd 61 etch t -tture -
Tetnpet•ture lrtnslbon. >5-i'ndlute IJansition. boch directions
Test dU<abon: 200 to 600 cycln (p,ogram ~ )
Test <Mat.on: 10.4 hours/.,.;s
i'la:derttion kw!·6.0 to 8.5 g rms
l'vt.n: X. Y••ndZ
------------~
i'la:der•bon J.:...d: 20g half sine mechanal shock
Tnt duttt><>n: 11 ms
F~uency: 6 tunes, on positive and negotive directions
Tnt durthon: 48 houn
Con~oon conditions: 5% N.O (ult fog) solution
Tn t du.abon 240 houis
En.,,,onment 85% humidity
Ttmperature: 85 C
lnitiol ESS U•e some piof1le ts thermal cycling except lowertemper•ture
________.__,. SS C •nd tt1t duiation ~ 10c:ycles (see Figure 4)
Junclion tnnperotu1n Ln• •h•n no•C 11'14•imum
arure range of -55° Lo 100°C, Lhe
PW'B was manufactured wiLh an
Aramid, 1mpregnaLed material
(Thermount) to conslrain the
board's X·Yexpansion rate
3. Environmental
Requirements
Toensurea typical 10-yearavionics
service lire, the module must pass
several accelerated stress Lesl5 for
specified durations. These tests
include accelerated Lhermal c.ycling.
random vibration, mechanical
shock, sail spray, tempcraLure,
humidiLy, eLc. Table 2 deLails the
environmental test requirements
for atypical 10-yearavtonicsservice
life. The lCSlingfocused on boLh lhe
mechanical and Lhermal aspects.
4. Design and
Processing
Selection ofLhe IRF-450 MOSFET
die and their accompanymg NPN
and PNP transistordnvers for the
COB process wasa logical choice,
since chese devices previously
demonslrated high yieldsassooated
with procurement, handling, and
processing of either bare die or
the associated packaged parLS.
Before packaging the high-
current MOSFET die in a power
module, it was essential to ensure
LhecompleLed thermallife cycle. after
mounting,wire bondingand encap-
sulation, would meet design
expectalions. BeforeacLual assembly,
surface mount technology (SMT)
and COB process compatibility
was tested on similar boards. A
design of expenmems was
performed to Lest board matcnals
and surface finishes, posL-SMT
cleaning methods, d1e-auach
matenals, wirebond processes, and
encapsulaLion The Nauonal Center
for ManufacturingSoences(NCMS)
Surface F1mshes Team Final
Repon 11, provided recommenda-
tions for the mckeVgold plating
finish and Lhickness for SMT and
wirebond processes. Die mounung
variables included solder versus
epoxy, the useofa molybdenum tab,
and constrained PWBs (-14
ppml"C) versus uncons1ramed
boards (17.5 ppmf'C). The die
encapsulantwasan epoxy producL.
The die encapsulant epoxy was
FUTURF CIRCUITS INTERNAT I ONAL
not a variable in this study.
Thermal cycle tests were the
preferred method Lo choose the
appropriate materials, finishes,
and processes. Afler 650 thermal
cycles (-55°C to 100°C). testing
indicated that the most reliable
1merconnect under the die for
thermal heat conduclion was a
moly-tabbed die soldered to a
parually constrained PWB
(Thermount). Thermalcycle solder
fatigue modeling of the power
module die indicated that a 0.005-
inch-thick solder joint of Sn63
would be essential for aLLachment
of Lhe MOSFET to PWB. This
solder thickness was needed to
maintain good thermal conduc-
tivity, keepjunction temperatures
wil.hmspecilicanon, and tocompen-
sate for differences inI.hecoefficients
ofthennal expansion (CTE) between
the silicon die and the PW'B over
Lhe temperature range. The
MOSFET die was alloyed to a
plaLed molybdenum tab before
Sn63 solder preform mounting to
the board assembly.
The layolllofthe power module
PWB was also designed so that
the solder-attached bare die could
be placed in printed solder paste
and then re!low-solder attached as
part of the in-line SMT assembly
process. This could eliminate Lhe
die-atlach processstep in the post-
SMTassembly flow as astand-alone
process.
The power module had indus-
trial-rated plastic devicessubstiruted
for many hermetic parLS (Figure 7).
COB and surface mount processing
is not the cheapest way to build
power supplies. However, it is a
good way to sLUdy both the effects
of the increased space that COB
saves and the effects ofa military
Lest/screeningand thermal cycle life
env1ronmems on high-current
encapsulated devices. This
processing also enables use of
industnal-rated plastic surface
mount componentsover a military
temperature range. Circuitry was
added to the control board as a
result of the extra space made
available bythe COB processSome
hermetic packages were retained on
the COB control board due co
md1v1dual package size limita-
tions.
The Aramid® PWB is a six-
layer board with a double-layer.

8. acrylicless flexible center Lransi-
tiomng to the control side of the
board. In module assembly, the
board with the control section
pans is folded until it faces the
primary power switches. An
insulatedcopper shieldis insened
between the two sides to prevent
~TOsstalk and noise.
Die-attach material for mounting
die to the PWBs is solder for the
power components and silver-
llled conductive epoxy for the
drive transistors. The bare die
required special handling during
processing to avoid contarnina-
1on and to allow successful
wirebonding. During the assembly
poruon ofthe study, it was deter-
mined that the cleaning solvent
used after die attach was a critical
material. The use of acidic and
alkaline solvent chemistries could
corrode the aluminum wire bond
"'ad metalization on the die,
preventingsuccessful wire bonding.
The SMT processand the aqueous
cleaningsolventsused in thisstudy
.11ere found to be benign and did
not degrade the bond wires or the
bondability of the devices. The
selection of wire materials and
diameters was based on physical
properties ofthe die, such as bond
pad size and pad metalization,
and electrical requirements including
maximum currentand wire resis-
tance. The wirebond process
required 0.010-inch-diameter
aluminum wire for the high-current
'-ircuit and 0.00!-inch-diameter
gold wire for the gatedrive circuit.
The secondary power stage
(shown in Figure 8) consisted ofa
simple 0.020-inch-thick, two-layer
Kapton®-copper semi-flexible
circuit. The copper chosen was
thick enough to produce lowmilli-
ohm resistance when measured
between thediode land pad areaand
the output tabs. Output tabs were
tin/lead plated and required a
fastener LO connect LO the next
higher assembly.Thediodes, power
resistors, filters,and outputtantalum
capacitors were surface mounted
on chemically etched and tin/lead-
plated SMT pads. The output filter
magnetics were solder auached
to the circuit at module assembly.
The power module base that
adds structure and thermal heat
spreading is 6061 anodized
aluminum, machinedwithsidewalls
to provide stiffness. An aluminum
cover(shownin Figure9) is mated
to the base, covetingall electronics
and maintaininganoverallmodule
thickness ofonly 0.340 inches.
The primary and secondary
powerstages, along withmagnetics,
wereattached to the base with an
0.008-inch-thick layerofthermally
conductive cyanate-ester epoxy.
The epoxywas trimmed inuncured
form and placed insidetheanodized
base aluminum, and parts were
placed on its surface. The entire
assembly was vacuum bagged and
curedat 125°C. Thennalconduc-
tivity ofthe cyanate-estermaterial
wasin the 3W/M-K range. Full load
operation of the module required
good thermal conduction to a
liquid or air cooled aluminum
heatsink, no hotter than 50°C.
5. Assembly Flow
The first step ofmodule processing
was the SMTcomponentsassembly.
As panoftheSMT in-line process,
the boards were stencil printed
withsolderpasteusingamono-level
0.010-inch-thick stainless steel
stencil, producing a 0.005-inch
column of reflowedsolid solder for
die attach under the MOSFETs.
The board substrates were
manufactured in the form ofrectan-
gular panels with pre-routed
snap-oIT tabs to permit ftxtureless
transport on the in-line conveyor
system. Figure 2 shows such a
configuration.
Surface mounl components
were placed into the solder paste
and reflowedina convectionoven.
The boards continued on the
conveyor system through the
aqueous cleaner/defluxer. SMT
inspection and touch-up opera-
tions were performed.
AfterSMT processing, the COB
die were attached to the PWBs
usingsolderpreforms and reflowed
in a vacuum reflow chamber
(Figure 3). The in-line SMT
mounting method in wet paste
was not used for this first prototype
run. Plasma cleaningofthe boards
was performed in anoxygen atrnos-
phere. Wire bonding was
accomplished with an ultrasonic
wedge bonder for the 0.010-inch-
diameter aluminum wire, and a
thennosonic ball bonder for the
0.001-inch-diameter gold wire.
FisuM 2. Pre-Routed Subpanef Board.
COB ASSEMBLY
GoldThe!mosonlc
Wln1eon<1
Placemont ol SMT
Conu>oo•nls
Modulo
lntegra11on
VaoouuJT>llag Laminate Pdmocy
and 5->dOl)IPower St.ge
Boardslo Aluminum Housing
Final Boclrlcll - Final Fuoollonal 11Cenfocmal Itnttgr.>tJon Test Co•dng
figul'f: 3. SMT Assembly Proce<s Aow With COB Attachment Incorporated.
Non-Op
Electrical Temp Cycle
~
Electrical ...._
Test f---+ -55° to 100°C Test
10 Cycles
Non-Op
Random
Electrical Thermal_. Vibration f---+ Test
___..
Survey
10 min/axis
0.04 g2
/Hz
figure 4. InitialCOB Mil Environmental SwssScrttning.
FUTURE CIRCUITS INTER N ATIO N AL
SJ
I
I

9. Proceea RepMled four ttnM {minml.m)
Nolll: Dllconlhled vb.aon ~ .iterlourlh pass~ loop.
Met MOOnd loopc:henge lhenMIcyde COi.ili to 100 c:ycles.
--------
c,,_ 5. Simuleted 10-YurAvionics 5-icc Llfc Ev1lu1tion.
MSN S Ncn.()p Non-Op Ncn.()p
n-n.I Random ~
- .Sl>OCI<__, SllOCIC 1-t WH9Uon rt f--t ~
100 Cyclff 0.04 flltU
Tiit
.!~ Y·-
~· to+lOO'C 1.3Hr/A>cll 20g, ,,,,,.
l p- -...i~
I
•I
1 ~
48-Hour ~
Z40-Hour ElecOlc8I
H SdFcg
--- Tiii H 85185 H TiitT..._-Hlmdlly
F9n6. Simulated Airborne Ouel&etion (Mil 810 RJ.).
Ag.n7.PrilMly Power Stegc With COB.
Table l . Thermal ind Mccti.nlul Tm Results
Tests
COBModulc MSN3 MSN .. MSNs
Tham.iicycks 201 cycln 565 qcln 69Scydn
R.ndom Vlb<•hOll 2.6 ho...11laxls 7.6 hou11Iaxis 10.4 ho...rs/..US
-
Meclwnoc.I shoe~
- 20 gs :t6 time. 20gs±6hmcs 20gs ±6 tiints
s.kfos 48 hours NIA NIA
T~~•tu1clhum1doty 240 hours 85185 NIA NIA
6. COB Test Plan
6.1lnltlal Screening
Five modules were manufactured.
Three ofthe five weresubjected to
the following environmentalsLreSS
conditionsasdefined in Table 2: full
Mil environmental stress screening
(ESS), thermal survey, thermal
cycling, three-axis random vibra-
tion, and mechanical shock.
The initial ESS testl21 for the
assemblies is sequentiallyshown in
Figure 4. The included thermal
survey evaluated heat transfer
efficiencies and identified module
hot spots.
6.i Simulated Military
Qualification
All module tests wereconducted per
the flow diagramsshown in Figures
5 and6.All environmental testS were
performed with the module m a
non-operational state. Electncal
testing cons1Sted of a functional
check and measunng efficiency
over the load range. Testing was
terminated when the first failure
occurred.
One module (MSN 3) was
subjected tosalt foglll and temper-
ature/humidity testingl•I. Two
modules (MSNs 4 and 5) received
extended ESS testing.The modules
receiving extended ESS testing
were expected to complete a
minimum of 413 thermal cycles
before the first 28-pin LCC solder
joint failure, as calculated using
the Raytheon Systems Low Cycle
Fatigue Calculation Spreadsheetl>l
for estimating SMT solder joint
fatigue.
As described earlier, all the
above tests were conducted while
the modules were inanon-powered
state. All COB electrical tests were
performed at specific intervals as
shown in Figures 5 and 6.
7. Results
Table3 shows the resultsofthe teStS
on MSNs 3, 4, and 5. Figures 7
shows the pnmary COB power
stage board with the glob-topped
die mounted on the Aramid, flex
circuit board. Figure 8 shows the
secondary powerstage with diodes,
power magnetics, and capacitors
soldered to the high<Urremcopper·
Kapton circuit. Figure 9 shows the
assembly in its aluminum base
l'IJTllRI' r1 11 r111T~ INT l'R N A Tl()tJ A I
afterall processes werecompleted.
Module MSN 3 completed 201
thennalcycles,2.6 hoursofrandom
Vlbration testing, all mechanical
shock teStS, and 48 hoursofsalt fog
test without any failures. After
compleungthe 240-hourtemper-
ature/humidity test, an anomaly
was noted with the switching
frequency. Troubleshooongisolated
the fault, the unstable switchmg
frequency, to a non-mil ceramic
capacitor that was exhibitingsigns
of internal shorting. All other
components and circuits were
[unctioning normally.
Module MSN 4 completed the
following tests: 7.6 hoursofrandom
vibration, all mechanical shock,
and 162 thermal cycles beyond
the expectedsolderjoint lifetime.
Testingwasstopped at 565 thermal
cycles for a random visual inspec-
tion and electrical test. Visual
mspecuon detected a solderjoint
fracture ona 28-pin LCC. Electrical
testing verified the solder joint
fracture when the module failed to
operate.
Module MSN 5 completed the
followmg tests:a full service life of
random Vlbranon, all mechanical
shock, and 292 thermal cycles
beyond the expected solder joint
hletime. The module failed during
electrical test duea fractured current
sense wire unrelated to the COB
process.
The thermal surveyl6
1 shown
in Figure 10 identified the power
transformer and rectifiers as the
hottest components in the COB
design.The high<UrrentMOSFETs
case temperatureswere lowerby6°
to 22°C (at 42-ampere output),
when compared to the diodes,
which wereat96°C. Thebaseplate
temperaturesunder the MOSFETs
were 55° to 45°C, moving left to
nght away from the power trans-
former. Average temperature rise
from 00seplateto MOSFETcase was
32°C. Power dissipated in each
MOSFET was 5 warts.
8. Discussions and
Conclusions
This paper has described a COB
assembly integrated with surface
mount assembly processes and
environmental testingwasdescribed
for a high-density DC-DC power
module with avionicsapplications.

10. F~ 8. Secondary Power Stage.
sing this technology for such an
application offers the following
:idvantages:
I The encapsulated COB design of
the module's high-current MOSFETs
md bipolar drivers demonstrated
Jn ability to survive typical 10-
vear military avionicsenvironment
tests, consisting of mechanical
shock, random vibration, thermal
...-ycle, salt fog, and temperature/
humidity tests. None ofthe module
failures was a direct result ofCOB
lJrocesses or materials.
2 The COB process, through the
use of chip and wire technology,
.ncreased PWB layout area and
module density, allowingfor pans
.:> be added.
3 The environmental tests
performed during this study
lJrovided agood way tostudy other
encapsulated plastic component
power supply parts. The failures
experienced duringelectrical testing
were the results of solder joint
fatigue, insufficient mechanical
mounting of module controller
E'VBs,and a non-Milcomponent
failure.
he results indicated that, in
tlusdestgn. COB technolOg} demon-
stratedreliable attachmentproces.se.s,
thermal cycle integrity, and the
ability to manage high heat dissi-
pation, all ofwhichcontribute to a
final mechanical package usable
for future assemblies in a 10-year
military life environmenc.
Additionalsmdies identifiedas
corollaries Lo thecurrent investigation
will broaden the scope of COB
application:
1. Testing is required under
operatingbiasconditionsatenviron-
ments investigated in this study
and at altitude.
2. The current COB processing is
unrepairable. Studiesare needed to
develop repair methods andeasily
repairable COB packages.
3. Furthertestingis requiredon non-
COB plastic and industrial-rated
devices to ensure survivability at
military environment extremes.
9. Acknowledgments
The authors gratefully acknowl-
edge Marie-Josee Turgeon and
Jacques A. Coderre ofIBM Canada
Ltd, Bromont, Quebec, Canada,
for their valuableassistance with the
figure 9. Completed COB Module Assembly.
figure 10. COB IR Then-no.I Survey (MSN 3; Alter completion of tests).
nickel/gold plating, and Marty
Maxon, Bobbie Novak, Steve
Dunford, Shari Coleman, Dave
Strasser, SteveZanola,JeffBranyan,
and Sharon Willaby of RayLheon
Syste.mS Companystaffforexcellent
help and valuable discussions
during the course of this investi-
gation.
10. References
111 NCMS Surface Finishes Team
Final Repon, No.0189RE96 (Ann
Arbor: 1996).
[2] Environmental stress screening
was performed using Mll-HDBK-
781A.
[31 Mll-STD-810 methods(507.2).
[41 MlL-STD-810 methods (509.2).
[SI This Raytheon spreadsheeL is
described in an article by T. Carp-:r
P. Viswanadham,and R. Vonma}•
entitled, "A Design Tool fr
Evaluating LowCycle SolderFatig
ofSMT lmerconnections." Desi~
andReliabilityofSolderandSola.:
Interconnections, Proceedings
IMSAnnualSymposium (Orlan..
FL: 1997) pp 305-316.
(61 Thermal survey was perform·:<..
using Mll-HDBK-781A.
BIOGRAPHIES
MIKE SPADARO joined
Texas Instruments' Defense
Systemsand Electronics Goup (DSEG)
in 1980. He receiYecl aB.S.in MedlllWCll
En9ineerin9 from the Univu,ity or

11. Pittsburgh (1975) and a M.S.M.E.
degree from West Virginia University
(1980). Mike is a senior mechanical
padaging design engineer with 18 years
experience in the field of high densityand
discrete power supply and digital card
design, for military and commercial appli-
cations. He hes been with the Advanced
Power~ group at11/Raytheon silce
1983. Current responsibilities on Power
System design programs include Nl?)(t
Generation Power Supply Mechanical
Design; research and development;
design management; all phases of
thermal/structuraldesign and analysis; and
mechanical producability and reliability.
MARK STALLER isMernber
of the Group Technical Staff at
Raytheon Systems Company in Dallas,
Texas. Markis a.m?ntly theMnJactimg
and Process Engineering Manager in
the Thick Film, Hybrid and MCM
~· He;ooedTexes Instruments
(Tl) in 1986 and has been with Raytheon
since its acquisition of Tl's Defense
Systems Group in 1997. Mark received
a BSEE degree from The Ohio State
University in 1981. Before coming to
Tl, he served as a Commissioned Officer
of the US Navy from 1981-1986.
DAVID STARK is a Member
of the Group Technical Staff at
Raytheon Systems Company (RSQ,
andis rr.dwd ii theclewlopment oflisher
density packaging approaches for RSC.
He joinedTexas Instruments in 1978 as
an industrialengineer supporting radarand
infrared opto-electronic systems. He
managed Production Engineering for
Microelectronics Packaging Systems.
David Stark holds a B.S. in Industrial
Engineering from Rutgers University and
an MBA from Southern Methodist
University.
PUUGANDLAVISWAHADHAM
is a Sr. Member of the Technical
staff at the Circuit Card Assembly
Center of Excellence at Raytheon
Systems Co., Lewisville, Texas,
U.S.A He is a member of the
Technology Development group
involved in the implementation of
BGA, CSP, and other emerging and
maturing technologies. Prior to joining
he worked in the development and
manufacturing areas of IBM Corp. for
over16 years. He holds an M.Sc.
degree from India and a Ph.D. degree
from the USA. He has authored/co-
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In addition, he has written over 80
technical papers and several invention
disclosures & patents.
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• Baxter DN-63 Oven
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FU TUR E CIRCU IT S INTERN AT IO NAL
56