NG3S903 - Electronic Systems Engineering - Fault Modelling Techniques

2/29/2016 Electronic
Systems
Engineering
Assignment 2 – Fault Modelling
Techniques
Christopher Francis
STUDENT ID: 15060209

Christopher Francis Assignment 2 Fault Modelling Techniques
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Contents
1. Executive Summary.........................................................................................................................2
2. Introduction ....................................................................................................................................3
3. Task 1 ..............................................................................................................................................4
3.1. Step 1: Insert the single stuck-at fault models. ..........................................................................5
3.2. Step 2: Propagate the fault to an observable node....................................................................6
3.3. Step 3: Trace back through the circuit and set the logic of the remaining gate inputs..............7
3.4. Step 4: Apply a HEX map to the inputs and output to observe duplicate tests. ........................8
3.5. Step 5: Reduce the fault set by removing the duplicate tests....................................................9
3.6. Step 6: Further reduce the fault set by altering non-fixed inputs to create duplicate tests....10
3.7. Step 7: Remove the new duplicate tests and produce the minimum list of test vectors.........11
3.8. Step 8: Task 1 results. ...............................................................................................................12
4. Task 2 ............................................................................................................................................13
4.1. Step 1: Insert the single stuck-at fault models. ........................................................................14
4.2. Step 2: Propagate the fault to an observable node..................................................................15
4.3. Step 3: Trace back through the circuit and set the logic of the remaining gate inputs............16
4.4. Step 4: Apply a HEX map to the inputs and output to observe duplicate tests. ......................17
4.5. Step 5: Reduce the fault set by removing the duplicate tests..................................................18
4.6. Step 6: Further reduce the fault set by altering non-fixed inputs to create duplicate tests....19
4.7. Step 7: Remove the new duplicate tests and produce the minimum list of test vectors.........20
5. Task 3. ...........................................................................................................................................22
5.1. Step 1: Create a schematic design circuit for Tasks 1 and 2.....................................................23
5.2. Step 2: Enter the Task 1 and 2 test vectors into the digital pattern generators. .....................24
5.3. Step 3: Use simulation graphs to verify Task 1 and 2 circuits...................................................27
5.4. Step 4: Test each node by inserting stuck-at fault circuits. ......................................................29
5.5. Step 5: Verify each stuck-at fault using a simulation graph......................................................32
6. Conclusion.....................................................................................................................................43
7. Bibliography ..................................................................................................................................44

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1. Executive Summary
This assignment demonstrates the application of modern fault modelling techniques when applied
to small combinational logic circuits to determine their minimum set of test vectors and maximum
achievable fault coverage.
It opens with a quick introduction into Fault Modelling and then provides a full description of all the
steps taken during the fault modelling and minimisation process.
To further express understanding of these techniques the circuit is then made more complex by
including fan-out, repeating the fault modelling process, identifying any un-testable nodes and then
determining any undetectable faults.
The findings obtained via the fault modelling methods are verified through the use of Proteus 8, a
software circuit simulation tool which is used to apply stuck-at-0 and stuck-at-1 faults to verify the
results.
Finally, the report concludes by presenting a set of simulation graphs and a short paragraph
discussing some of the results.

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2. Introduction
In today’s diverse electronic arena, design for testability is vital to the successful fault detection on
printed circuit boards (PCB’s). There are numerous techniques which can be used to identify the
presence of a fault, of which Dorf (1997) lists three of the most widespread testing methods as
follows:
 The D-algorithm.
 The Path-Orientated Decision Making (Podem) algorithm.
 The Fan algorithm.
In their most basic form these digital algorithms involve producing a set of test vectors, applying
them as input stimuli to a PCB and propagating a fault to a visible output. This methodology,
referred to as fault modelling, is used in the main because functional tests are inadequate for root
cause analysis. Fault modelling utilises test vectors to analyse circuit defects logically, rather than
physically and is an efficient means of decreasing the quantity of test vectors.
Ghosh and Chakraborty (1991) tell us the most popular fault model in industry today is the single
stuck-at fault model. The underlying ethos behind the stuck-at model is that it can detect a very high
percentage of multiple faults if all the single faults are identified. These models, which are applied to
one node at a time in turn, present at either the input or output of a logic gate and come in two
forms:
 Stuck-at-0, where the faulty line is permanently set to a logic 0.
 Stuck-at-1, where the faulty line is permanently set to a logic 1.
In this assignment we shall use the stuck-at fault models as shown in Figure 1 below; the AND model
known as the “Walking 0 Test”, the OR model often referred to as the “Walking 1 Test”, and the XOR
model. Note that the tables illustrate both the 2 input and 3 input logic models.
AND OR XOR
1 1 1 0 0 0 0 0
0 1 1 1 0 0 1 1
1 0 1 0 1 0
1 1 0 1 0 1
Figure 1 – Single stuck-at fault models.

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3. Task 1
The first task will be to evaluate the combinational logic circuit in Figure 2 below and use fault
modelling techniques to produce a theoretical minimum set of test vectors, calculating the
maximum fault coverage that can be achieved. The circuit comprises of AND gates G1 and G4, OR
gates G2 and G5, and XOR gate G3.
G1
G2
G3
G4
G5
I
H
J
K
A
B
C
E
O/P
F
G
D
Figure 2 – Combinational logic circuit.
Evaluation of this circuit will be carried out over a number of steps as detailed below.

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3.1. Step 1: Insert the single stuck-at fault models.
Create a fault table, Figure 3, and insert the single stuck-at fault models in RED for each of the gates given in the logic circuit Figure 2. The number of tests
for each gate is defined as m+1 where m = the number of inputs. The exception to this rule is the XOR gate where the number of tests is simply m = the
number of inputs. Each test detects at least one fault and the furthest right hand column identifies whether the fault is a stuck-at 0 (SA0) or a stuck-at 1
(SA1).
GATE TEST No. A B C D E F G O/P H I J K HEX FAULTS DETECTED
G1
AND
1 1 1 1 A, B, or C SA0
2 0 1 1 A SA1
3 1 0 1 B SA1
4 1 1 0 C SA1
G2
OR
5 0 0 D or E SA1
6 1 0 D SA0
7 0 1 E SA0
G3
XOR
8 0 0 F or G SA1
9 1 1 F or G SA0
G4
AND
10 1 1 H or I SA0
11 0 1 H SA1
12 1 0 I SA1
G5
OR
13 0 0 J or K SA1
14 1 0 J SA0
15 0 1 K SA0
Figure 3 – Test vectors with single stuck-at fault models inserted.

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3.2. Step 2: Propagate the fault to an observable node.
Insert the BLUE propagation values into the table shown in Figure 4 by observing two fundamental rules:
 If the path of fault propagation passes through an AND or NAND gate, then set all other inputs apart from the faulty one to a logic 1.
 If the path of fault propagation passes through an OR or NOR gate, then set all other inputs apart from the faulty one to a logic 0.
G1
AND
1 1 1 1 1 0 A, B, or C SA0
2 0 1 1 1 0 A SA1
3 1 0 1 1 0 B SA1
4 1 1 0 1 0 C SA1
G2
OR
5 0 0 1 0 D or E SA1
6 1 0 1 0 D SA0
7 0 1 1 0 E SA0
G3
XOR
8 0 0 0 F or G SA1
9 1 1 0 F or G SA0
G4
AND
10 1 1 0 H or I SA0
11 0 1 0 H SA1
12 1 0 0 I SA1
G5
OR
13 0 0 J or K SA1
14 1 0 J SA0
15 0 1 K SA0
Figure 4 – Test vectors with single stuck-at fault models and propagation values inserted.

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3.3. Step 3: Trace back through the circuit and set the logic of the remaining gate inputs
Now trace back through the circuit for each test vector and enable the fault paths by setting the required node logic as identified in BLACK in Figure 5
below. Note that in some cases either a specific combination or a variety of conditions may be set as indicated by the additional symbols and the key at the
bottom of the table.
G1
AND
1 1 1 1 1* 1* 0+ 0+ 1 1 1 1 0 A, B, or C SA0
2 0 1 1 1* 1* 0+ 0+ 0 0 1 0 0 A SA1
3 1 0 1 1* 1* 0+ 0+ 0 0 1 0 0 B SA1
4 1 1 0 1* 1* 0+ 0+ 0 0 1 0 0 C SA1
G2
OR
5 1 1 1 0 0 0+ 0+ 0 1 0 0 0 D or E SA1
6 1 1 1 1 0 0+ 0+ 1 1 1 1 0 D SA0
7 1 1 1 0 1 0+ 0+ 1 1 1 1 0 E SA0
G3
XOR
8 0++ 0++ 0++ 0 0 0 0 0 0** 0** 0 0 F or G SA1
9 0++ 0++ 0++ 0 0 1 1 0 0** 0** 0 0 F or G SA0
G4
AND
10 1 1 1 1* 1* 0+ 0+ 1 1 1 1 0 H or I SA0
11 0++ 0++ 0++ 1* 1* 0+ 0+ 0 0 1 0 0 H SA1
12 1 1 1 0 0 0+ 0+ 0 1 0 0 0 I SA1
G5
OR
13 0++ 0++ 0++ 0 0 0+ 0+ 0 0** 0** 0 0 J or K SA1
14 1 1 1 1* 1* 0+ 0+ 1 1 1 1 0 J SA0
15 0++ 0++ 0++ 0 0 0~ 1~ 1 0** 0** 0 1 K SA0
* One of D or E or Both must be 1. + Both F and G must either be 0, 0 or 1, 1. ~ Both F and G must not be 0, 0 or 1, 1.
** At least one of H or I must be 0. ++ At least one of A, B or C must be 0.
Figure 5 - Test vectors with single stuck-at fault models, propagation values and backtraced logic inserted.

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3.4. Step 4: Apply a HEX map to the inputs and output to observe duplicate tests.
Hexadecimal mapping provides a simple visual method of identifying duplicate tests. The fault table in Figure 6 is set out in a way that allows ease of
evaluation by placing the inputs directly next to the output. The HEX code for Test No. 1 is identified as F9 which comprises of A+B+C+D = 8+4+2+1 = “F”
and E+F+G+O/P = 8+0+0+1 = “9”. We can now apply HEX codes for all of the test vectors using the same technique. The green highlight indicates the
duplicate tests which can easily be identified by the matching HEX codes.
HEX HEX
G1
AND
1 1 1 1 1* 1* 0+ 0+ 1 1 1 1 0 F9 A, B, or C SA0
2 0 1 1 1* 1* 0+ 0+ 0 0 1 0 0 78 A SA1
3 1 0 1 1* 1* 0+ 0+ 0 0 1 0 0 B8 B SA1
4 1 1 0 1* 1* 0+ 0+ 0 0 1 0 0 D8 C SA1
G2
OR
5 1 1 1 0 0 0+ 0+ 0 1 0 0 0 E0 D or E SA1
6 1 1 1 1 0 0+ 0+ 1 1 1 1 0 F1 D SA0
7 1 1 1 0 1 0+ 0+ 1 1 1 1 0 E9 E SA0
G3
XOR
8 0++ 0++ 0++ 0 0 0 0 0 0** 0** 0 0 00 F or G SA1
9 0++ 0++ 0++ 0 0 1 1 0 0** 0** 0 0 06 F or G SA0
G4
AND
10 1 1 1 1* 1* 0+ 0+ 1 1 1 1 0 F9 H or I SA0
11 0++ 0++ 0++ 1* 1* 0+ 0+ 0 0 1 0 0 18 H SA1
12 1 1 1 0 0 0+ 0+ 0 1 0 0 0 E0 I SA1
G5
OR
13 0++ 0++ 0++ 0 0 0+ 0+ 0 0** 0** 0 0 00 J or K SA1
14 1 1 1 1* 1* 0+ 0+ 1 1 1 1 0 F9 J SA0
15 0++ 0++ 0++ 0 0 0~ 1~ 1 0** 0** 0 1 03 K SA0
Figure 6 - Test vectors with single stuck-at fault models, propagation values, backtraced logic and HEX codes inserted.

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3.5. Step 5: Reduce the fault set by removing the duplicate tests.
Now we can reduce the fault set by deleting the green highlighted rows containing the duplicate test vectors and relocating the fault identifiers to the
remaining tests as shown in Figure 7. This is a trade-off though as there will be less exclusivity of identifiable faults.
TEST No. A B C D E F G O/P H I J K HEX FAULTS DETECTED
1 1 1 1 1* 1* 0+ 0+ 1 1 1 1 0 F9 A, B, or C SA0 H or I SA0 J SA0
2 0 1 1 1* 1* 0+ 0+ 0 0 1 0 0 78 A SA1
3 1 0 1 1* 1* 0+ 0+ 0 0 1 0 0 B8 B SA1
4 1 1 0 1* 1* 0+ 0+ 0 0 1 0 0 D8 C SA1
5 1 1 1 0 0 0+ 0+ 0 1 0 0 0 E0 D or E SA1 I SA1
6 1 1 1 1 0 0+ 0+ 1 1 1 1 0 F1 D SA0
7 1 1 1 0 1 0+ 0+ 1 1 1 1 0 E9 E SA0
8 0++ 0++ 0++ 0 0 0 0 0 0** 0** 0 0 00 F or G SA1 J or K SA1
9 0++ 0++ 0++ 0 0 1 1 0 0** 0** 0 0 06 F or G SA0
11 0++ 0++ 0++ 1* 1* 0+ 0+ 0 0 1 0 0 18 H SA1
15 0++ 0++ 0++ 0 0 0~ 1~ 1 0** 0** 0 1 03 K SA0
Figure 7 – Reduced test vector set with single stuck-at fault models, propagation values, backtraced logic and HEX codes inserted.

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3.6. Step 6: Further reduce the fault set by altering non-fixed inputs to create duplicate tests.
Our aim here is to create additional duplicate tests where possible to reduce the vector set even further. This is achieved by setting the non-fixed inputs so
that they create duplicate tests while the output remains the same. Figure 8 below demonstrates this by highlighting the HEX values in GREEN and YELLOW,
along with the modified non-fixed inputs in the same row. Once again duplicate tests have been highlighted in green along the row.
1 1 1 1 1* 0* 0+ 0+ 1 1 1 1 0 F1 A, B, or C SA0 H or I SA0 J SA0
2 0 1 1 1* 1* 0+ 0+ 0 0 1 0 0 78 A SA1
3 1 0 1 1* 1* 0+ 0+ 0 0 1 0 0 B8 B SA1
4 1 1 0 1* 1* 0+ 0+ 0 0 1 0 0 D8 C SA1
5 1 1 1 0 0 0+ 0+ 0 1 0 0 0 E0 D or E SA1 I SA1
6 1 1 1 1 0 0+ 0+ 1 1 1 1 0 F1 D SA0
7 1 1 1 0 1 0+ 0+ 1 1 1 1 0 E9 E SA0
8 0++ 0++ 0++ 0 0 0 0 0 0** 0** 0 0 00 F or G SA1 J or K SA1
9 0++ 0++ 0++ 0 0 1 1 0 0** 0** 0 0 06 F or G SA0
11 1++ 1++ 0++ 1* 1* 0+ 0+ 0 0 1 0 0 D8 H SA1
15 0++ 0++ 0++ 0 0 0~ 1~ 1 0** 0** 0 1 03 K SA0
Figure 8 – Reduced test vector set with single stuck-at fault models, propagation values, backtraced logic, non-fixed inputs and HEX codes modified.

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3.7. Step 7: Remove the new duplicate tests and produce the minimum list of test vectors.
As before we can reduce the fault set by deleting the green highlighted rows containing the duplicate test vectors and relocating the fault identifiers to the
remaining tests as shown in Figure 9. We have reduced down from 128 exhaustive tests to 9 tests using the single stuck-at fault model method. It can be
seen that 128 exhaustive tests are derived from 2n
, where n = number of inputs = 27
.
1 1 1 1 1* 0* 0+ 0+ 1 1 1 1 0 F1 A, B, or C SA0 H or I SA0 J SA0 D SA0
2 0 1 1 1* 1* 0+ 0+ 0 0 1 0 0 78 A SA1
3 1 0 1 1* 1* 0+ 0+ 0 0 1 0 0 B8 B SA1
4 1 1 0 1* 1* 0+ 0+ 0 0 1 0 0 D8 C SA1 H SA1
5 1 1 1 0 0 0+ 0+ 0 1 0 0 0 E0 D or E SA1 I SA1
7 1 1 1 0 1 0+ 0+ 1 1 1 1 0 E9 E SA0
8 0++ 0++ 0++ 0 0 0 0 0 0** 0** 0 0 00 F or G SA1 J or K SA1
9 0++ 0++ 0++ 0 0 1 1 0 0** 0** 0 0 06 F or G SA0
15 0++ 0++ 0++ 0 0 0~ 1~ 1 0** 0** 0 1 03 K SA0
Figure 9 – Final set of test vectors reduced from 128 tests for exhaustive testing to 9 tests using the fault model.

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3.8. Step 8: Task 1 results.
 Steps 1 to 7 illustrate how we arrive at a theoretical minimum set of 9 test vectors from 128.
 By adding up the individual faults in the “FAULTS DETECTED” column of Figure 9 the total
number of faults detected by the test vectors is 22. Given that the total number of faults in the
fault list is 22 we can determine the maximum fault coverage as follows:
Fault Coverage = Number of faults detected by test vectors x 100
Total number of faults in the fault list
= 22 x 100
22
= 2200
22
= 100%
As can be expected, in a circuit with no fan-out 100% of faults are detectable.

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4. Task 2
The second task will be to modify the logic circuit used in Task 1 to include fan-out as shown in
Figure 10 below and then repeat the steps taken in Task 1 to find a minimum set of test vectors.
Using the same methodology, we can then determine the maximum fault coverage that can be
achieved, but this time the inclusion of fan-out in the circuit may produce un-testable nodes from
which we can identify any undetectable faults.
G1
G2
G3
G4
G5
I
H
J
K
A
B
C
E
O/P
F
G
Figure 10 – Combinational logic circuit with fan-out included.
Evaluation of this circuit will be carried out over a number of steps as detailed below.

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4.1. Step 1: Insert the single stuck-at fault models.
Create a Fault Table, Figure 11, and insert the single stuck-at fault models in RED for each of the gates given in the logic circuit Figure 10. The number of
tests for each gate is defined as m+1 where m = the number of inputs. The exception is the XOR gate where the number of tests is simply m = the number of
inputs. Each test detects at least one fault and the furthest right hand column identifies whether the fault is a stuck-at 0 (SA0) or a stuck-at 1 (SA1). Note
that column D is no longer a primary input and not used due to the inclusion of fan-out in the circuit. Column D was left in to make this fact visible.
G1
AND
1 1 1 1
NOLONGERUSED
A, B, or C SA0
2 0 1 1 A SA1
3 1 0 1 B SA1
4 1 1 0 C SA1
G2
OR
5 0 0 C or E SA1
6 1 0 C SA0
7 0 1 E SA0
G3
XOR
8 0 0 F or G SA1
9 1 1 F or G SA0
G4
AND
10 1 1 H or I SA0
11 0 1 H SA1
12 1 0 I SA1
G5
OR
13 0 0 J or K SA1
14 1 0 J SA0
15 0 1 K SA0
Figure 11 – Test vectors with single stuck-at fault models inserted.

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4.2. Step 2: Propagate the fault to an observable node.
Insert the BLUE propagation values into the table shown in Figure 12 by observing two fundamental rules:
 If the path of fault propagation passes through an AND or NAND gate, then set all other inputs apart from the faulty one to a logic 1.
 If the path of fault propagation passes through an OR or NOR gate, then set all other inputs apart from the faulty one to a logic 0.
G1
AND
1 1 1 1
NOLONGERUSED
1 0 A, B, or C SA0
2 0 1 1 1 0 A SA1
3 1 0 1 1 0 B SA1
4 1 1 0 1 0 C SA1
G2
OR
5 0 0 1 0 C or E SA1
6 1 0 1 0 C SA0
7 0 1 1 0 E SA0
G3
XOR
8 0 0 0 F or G SA1
9 1 1 0 F or G SA0
G4
AND
10 1 1 0 H or I SA0
11 0 1 0 H SA1
12 1 0 0 I SA1
G5
OR
13 0 0 J or K SA1
14 1 0 J SA0
15 0 1 K SA0
Figure 12 – Test vectors with single stuck-at fault models and propagation values inserted.

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4.3. Step 3: Trace back through the circuit and set the logic of the remaining gate inputs
Backtrace through the circuit for each test vector and enable the fault paths by setting the required node logic as identified in BLACK in Figure 13 below.
Note that in some cases either a specific combination or a variety of conditions may be set as indicated by the additional symbols and the key at the bottom
of the table. The red highlight shows test vectors that cannot propagate because of the conflicting fan-out logic.
G1
AND
1 1 1 1
NOLONGERUSED
1* 0+ 0+ 1 1 1 1 0 A, B, or C SA0
2 0 1 1 1* 0+ 0+ 0 0 1 0 0 A SA1
3 1 0 1 1* 0+ 0+ 0 0 1 0 0 B SA1
4 1 1 0 1* 0+ 0+ 0 0 1 0 0 C SA1
G2
OR
5 1 1 0 0 0+ 0+ 0 1 0 0 0 C or E SA1 cannot propagate via H
6 1 1 1 0 0+ 0+ 1 1 1 1 0 C SA0
7 1 1 0 1 0+ 0+ 1 1 1 1 0 E SA0 cannot propagate via H
G3
XOR
8 0++ 0++ 0++ 0 0 0 0 0** 0** 0 0 F or G SA1
9 0++ 0++ 0++ 0 1 1 0 0** 0** 0 0 F or G SA0
G4
AND
10 1 1 1 1* 0+ 0+ 1 1 1 1 0 H or I SA0
11 0++ 0++ 0++ 1* 0+ 0+ 0 0 1 0 0 H SA1
12 1 1 0 0 0+ 0+ 0 1 0 0 0 I SA1 cannot propagate via H
G5
OR
13 0++ 0++ 0++ 0 0+ 0+ 0 0** 0** 0 0 J or K SA1
14 1 1 1 1* 0+ 0+ 1 1 1 1 0 J SA0
15 0++ 0++ 0++ 0 0~ 1~ 1 0** 0** 0 1 K SA0
* One of C or E or Both must be 1. + Both F and G must either be 0, 0 or 1, 1. ~ Both F and G must not be 0, 0 or 1, 1.
Figure 13 - Test vectors with single stuck-at fault models, propagation values and backtraced logic inserted.

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4.4. Step 4: Apply a HEX map to the inputs and output to observe duplicate tests.
Hexadecimal mapping provides a simple visual method of identifying duplicate tests. The fault table in Figure 14 is set out in a way that allows ease of
evaluation by placing the inputs directly next to the output. The HEX code for Test No. 1 is identified as 79 which comprises of A+B+C = 4+2+1 = “7” and
E+F+G+O/P 8+0+0+1 = “9”. We can now apply HEX codes for all of the test vectors using the same technique. The green highlight indicates the duplicate
tests which can easily be identified by the matching HEX codes.
HEX HEX
G1
AND
1 1 1 1
NOLONGERUSED
1* 0+ 0+ 1 1 1 1 0 79 A, B, or C SA0
2 0 1 1 1* 0+ 0+ 0 0 1 0 0 38 A SA1
3 1 0 1 1* 0+ 0+ 0 0 1 0 0 58 B SA1
4 1 1 0 1* 0+ 0+ 0 0 1 0 0 68 C SA1
G2
OR
5 1 1 0 0 0+ 0+ 0 1 0 0 0 60 C or E SA1 cannot propagate via H
6 1 1 1 0 0+ 0+ 1 1 1 1 0 71 C SA0
7 1 1 0 1 0+ 0+ 1 1 1 1 0 69 E SA0 cannot propagate via H
G3
XOR
8 0++ 0++ 0++ 0 0 0 0 0** 0** 0 0 00 F or G SA1
9 0++ 0++ 0++ 0 1 1 0 0** 0** 0 0 06 F or G SA0
G4
AND
10 1 1 1 1* 0+ 0+ 1 1 1 1 0 79 H or I SA0
11 0++ 0++ 0++ 1* 0+ 0+ 0 0 1 0 0 08 H SA1
12 1 1 0 0 0+ 0+ 0 1 0 0 0 60 I SA1 cannot propagate via H
G5
OR
13 0++ 0++ 0++ 0 0+ 0+ 0 0** 0** 0 0 00 J or K SA1
14 1 1 1 1* 0+ 0+ 1 1 1 1 0 79 J SA0
15 0++ 0++ 0++ 0 0~ 1~ 1 0** 0** 0 1 03 K SA0
Figure 14 - Test vectors with single stuck-at fault models, propagation values, backtraced logic and HEX codes inserted.

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4.5. Step 5: Reduce the fault set by removing the duplicate tests.
Now we can reduce the fault set by deleting the green highlighted rows containing the duplicate test vectors and relocating the fault identifiers to the
remaining tests as shown in Figure 15. This is a trade-off though as there will be less exclusivity of identifiable faults.
1 1 1 1
NOLONGERUSED
1* 0+ 0+ 1 1 1 1 0 79 A, B, or C SA0 H or I SA0 J SA0
2 0 1 1 1* 0+ 0+ 0 0 1 0 0 38 A SA1
3 1 0 1 1* 0+ 0+ 0 0 1 0 0 58 B SA1
4 1 1 0 1* 0+ 0+ 0 0 1 0 0 68 C SA1
6 1 1 1 0 0+ 0+ 1 1 1 1 0 71 C SA0
8 0++ 0++ 0++ 0 0 0 0 0** 0** 0 0 00 F or G SA1 J or K SA1
9 0++ 0++ 0++ 0 1 1 0 0** 0** 0 0 06 F or G SA0
11 0++ 0++ 0++ 1* 0+ 0+ 0 0 1 0 0 08 H SA1
15 0++ 0++ 0++ 0 0~ 1~ 1 0** 0** 0 1 03 K SA0
Figure 15 – Reduced test vector set with single stuck-at fault models, propagation values, backtraced logic and HEX codes inserted.

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4.6. Step 6: Further reduce the fault set by altering non-fixed inputs to create duplicate tests.
Our aim here is to create additional duplicate tests where possible to reduce the vector set even further. This is achieved by setting the non-fixed inputs so
that they create duplicate tests while the output remains the same. Figure 16 below demonstrates this by highlighting the HEX values in GREEN and
YELLOW, along with the modified non-fixed inputs in the same row. Once again duplicate tests have been highlighted in green along the row.
1 1 1 1
NOLONGERUSED
2 0 1 1 1* 0+ 0+ 0 0 1 0 0 38 A SA1
3 1 0 1 1* 0+ 0+ 0 0 1 0 0 58 B SA1
4 1 1 0 1* 0+ 0+ 0 0 1 0 0 68 C SA1
6 1 1 1 0 0+ 0+ 1 1 1 1 0 71 C SA0
8 0++ 0++ 0++ 0 0 0 0 0** 0** 0 0 00 F or G SA1 J or K SA1
9 0++ 0++ 0++ 0 1 1 0 0** 0** 0 0 06 F or G SA0
11 1++ 1++ 0++ 1* 0+ 0+ 0 0 1 0 0 68 H SA1
15 0++ 0++ 0++ 0 0~ 1~ 1 0** 0** 0 1 03 K SA0
Figure 16 – Reduced test vector set with single stuck-at fault models, propagation values, backtraced logic, non-fixed inputs and HEX codes modified.

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4.7. Step 7: Remove the new duplicate tests and produce the minimum list of test vectors.
As before we can reduce the fault set by deleting the green highlighted rows containing the duplicate test vectors and relocating the fault identifiers to the
remaining tests as shown in Figure 17. We have reduced down from 64 exhaustive tests to 7 useable tests using the single stuck-at fault model method. It
can be seen that 64 exhaustive tests are derived from 2n
, where n = number of inputs = 26
. To clarify the minimum list of “usable” test vectors I have also
removed the RED highlighted tests 5, 7 and 12 as they will not propagate via H, noting that C SA1 is already detectable in test vector 4.
1 1 1 1
NOLONGERUSED
2 0 1 1 1* 0+ 0+ 0 0 1 0 0 38 A SA1
3 1 0 1 1* 0+ 0+ 0 0 1 0 0 58 B SA1
4 1 1 0 1* 0+ 0+ 0 0 1 0 0 68 C SA1 H SA1
8 0++ 0++ 0++ 0 0 0 0 0** 0** 0 0 00 F or G SA1 J or K SA1
9 0++ 0++ 0++ 0 1 1 0 0** 0** 0 0 06 F or G SA0
15 0++ 0++ 0++ 0 0~ 1~ 1 0** 0** 0 1 03 K SA0
Figure 17 – Final set of test vectors reduced from 64 tests for exhaustive testing to 7 useable tests using the fault model.

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 Steps 1 to 7 illustrate how we arrive at a theoretical minimum set of 7 test vectors from 64,
noting the 3 additional tests which are unusable as the fan-out prevents fault detection.
 By adding up the individual faults in the “FAULTS DETECTED” column of Figure 17 the total
number of faults detected by the test vectors is 17. Given that the total number of faults in the
fault list is 20, because C SA0 and C SA1 were duplicated, we can determine the maximum fault
coverage as follows:
Fault Coverage = Number of faults detected by test vectors x 100
Total number of faults in the fault list
= 17 x 100
20
= 1700
20
= 85%
In this instance we do not get 100% coverage because the fan-out in the circuit results in un-
testable nodes and undetectable faults.
 The un-testable nodes are E and I, but I can still be tested for the SA0 fault despite fan-out which
prevents propagation.
 There are 3 undetectable faults which are a result of fan-out: E and I SA1, and E SA0.

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5. Task 3.
In this task the circuit simulation tool Proteus 8 will be used to simulate and verify both
combinational logic circuits that were created in Tasks 1 and 2. A control circuit consisting of an AND
and OR gate combination will then be used to apply stuck-at 0 and stuck-at 1 faults to each node to
confirm fault detection is consistent with the final set of reduced test vectors from Figures 9 and 17.
The detectable faults from each circuit can then be verified using simulation graphs. However, as
there are 22 faults in Figure 9 and 17 in Figure 17, it seemed sensible to demonstrate the verification
methodology by producing one simulation graph for each test vector. Therefore, only a total of 16
graphs will be produced despite the fact that each stuck-at fault was actually be tested.
Assessment of the circuits will be carried out over a number of steps as detailed below.

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5.1. Step 1: Create a schematic design circuit for Tasks 1 and 2.
The full schematic designs shown in Figure 18 and 19 below have been created using the Proteus 8
circuit simulation software tool. The circuits were then configured so that simulation of the final set
of Task 1 and Task 2 test vectors could be created by placing digital pattern generators on the
primary inputs A to G and voltage monitoring probes on both the internal nodes H to K and the
output O/P.
Figure 18 – Proteus 8 schematic showing Task 1 combinational logic circuit without fan-out.
Figure 19 – Proteus 8 schematic showing Task 2 combinational logic circuit with fan-out.

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5.2. Step 2: Enter the Task 1 and 2 test vectors into the digital pattern generators.
Each test vector can now be entered into the simulator by setting up a digital pattern generator on the primary inputs A to G as shown in Figures 18 and 19
above. The pattern generators are created by taking the logic states from the appropriate primary input columns of the minimised set of test vectors shown
in Figures 20 and 21 below, and then entering them as a sequence into each generator. For example; input column “A” of Figure 20 is loaded into digital
pattern generator A (Figure 21.1) of the Task 1 circuit as “101111000”. Next, input column “B” is loaded into digital pattern generator B as “110111000”.
This process is repeated until all digital pattern generators have been entered for each primary input into both test circuits from Tasks 1 and 2.
1 1 1 1 1* 0* 0+ 0+ 1 1 1 1 0 F1 A, B, or C SA0 H or I SA0 J SA0 D SA0
2 0 1 1 1* 1* 0+ 0+ 0 0 1 0 0 78 A SA1
3 1 0 1 1* 1* 0+ 0+ 0 0 1 0 0 B8 B SA1
4 1 1 0 1* 1* 0+ 0+ 0 0 1 0 0 D8 C SA1 H SA1
5 1 1 1 0 0 0+ 0+ 0 1 0 0 0 E0 D or E SA1 I SA1
7 1 1 1 0 1 0+ 0+ 1 1 1 1 0 E9 E SA0
8 0++ 0++ 0++ 0 0 0 0 0 0** 0** 0 0 00 F or G SA1 J or K SA1
9 0++ 0++ 0++ 0 0 1 1 0 0** 0** 0 0 06 F or G SA0
15 0++ 0++ 0++ 0 0 0~ 1~ 1 0** 0** 0 1 03 K SA0
Figure 20 – Final set of Task 1 test vectors reduced from 128 tests for exhaustive testing to 9 tests using the fault model.

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1 1 1 1
NOLONGERUSED
2 0 1 1 1* 0+ 0+ 0 0 1 0 0 38 A SA1
3 1 0 1 1* 0+ 0+ 0 0 1 0 0 58 B SA1
4 1 1 0 1* 0+ 0+ 0 0 1 0 0 68 C SA1 H SA1
8 0++ 0++ 0++ 0 0 0 0 0** 0** 0 0 00 F or G SA1 J or K SA1
9 0++ 0++ 0++ 0 1 1 0 0** 0** 0 0 06 F or G SA0
15 0++ 0++ 0++ 0 0~ 1~ 1 0** 0** 0 1 03 K SA0
Figure 21 – Final set of Task 2 test vectors reduced from 64 tests for exhaustive testing to 7 useable tests using the fault model.

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Figure 21.1 – Proteus 8 digital pattern generator properties for generator A.
Once the digital pattern generators A – G have all been set up we can move on to circuit verification.

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5.3. Step 3: Use simulation graphs to verify Task 1 and 2 circuits.
Before inserting any stuck-at faults into the Task 1 and 2 circuits it seemed judicious to verify the
fault free logic operation of the designs using Proteus 8 simulation graphs. This was achieved by
reading down the Y axis of the logic traces in Figures 22 and 23 below and verifying the output (O/P)
goes high or low as expected within each relative X axis period. For example; test vector 1 of Figure
20 above has primary inputs A to G set as “1111000”; internal nodes H to K result as “1110”; and the
output O/P results in a logic “1”. The red dashed line in Figure 22 below confirms these logic states
to be true. This process is then repeated for the remaining 8 test vectors of Task 1 so that we can
simulate each vector every 500ms within one trace, confirming the logic states to be valid for each
test. Please note that in practice the maximised simulation graph windows were used while
evaluating the traces, but were not included in the report as they take up too much room and
require zooming in to read the detail.
Figure 22 – Proteus 8 simulation graph for Task 1 minimum test vectors without fan-out
Following verification of the results found in Task 1 above the same methodology was applied to
Task 2 and the results obtained in Figure 21 above were also proven to be valid as can be seen in
Figure 23 below.

28 | P a g e
Figure 23 – Proteus 8 simulation graph for Task 2 minimum test vectors with fan-out
Having established both circuits and test vectors to be functioning correctly we could confidently
progress with the individual stuck-at fault testing of each node as detailed over the next steps.

29 | P a g e
5.4. Step 4: Test each node by inserting stuck-at fault circuits.
Each node is now tested for the presence of a fault by using the Proteus software to apply stuck-at-0
and stuck-at-1 faults to the Task 1 and 2 circuit schematics using one of the following two methods:
METHOD 1: Switch on and latch a power rail to one of the primary inputs A to G in the form of a
logic 0 (GND) as shown in the example Figure 24 below, or a logic 1 (VCC) as shown in Figure 25.
Figure 24 – Example stuck-at-0 fault applied using push button PB A to latch in a GND power rail.
Figure 25 – Example stuck-at-1 fault applied using push button PB A to latch in a VCC power rail.

30 | P a g e
METHOD 2: Insert a stuck-at-0 or stuck-at-1 AND and OR gate circuit combination into the internal
nodes H to K of the Task schematic as shown below in the example Figures 26, 27, 28 and 29.
Figure 26 – Proteus 8 schematic stuck-at-0 AND and OR test circuit.
As can be seen in Figure 26 above, if a logic 1 (red square) is applied to the Input (IN) a logic 0 (blue
square) will result at the Output (OUT), thus simulating a stuck-at-0 fault. Note that both “GND”
inputs to the gates set up the logic to achieve the desired effect. In this case it does not matter
whether you apply a low or high signal to the Input as the output will always remain stuck-at-0 as
indicated by V=SLO in the diagram.
Figure 27 – Example of a stuck-at-0 AND and OR test circuit inserted into internal node H.
In Figure 27 above simply insert the stuck-at-0 test circuit from Figure 26, shown in a red dashed
box, into the Task 1 test schematic to force internal node H to a logic 0. In this example a simulation
graph would then be used to detect and verify the stuck-at-0 fault on node H using test vector 1.

31 | P a g e
Figure 28 – Proteus 8 schematic stuck-at-1 AND and OR test circuit.
As shown in Figure 28 above, if a logic 0 (blue square) is applied to the Input (IN) a logic 1 (red
square) will result at the Output (OUT), thus simulating a stuck-at-1 fault. Note that both “VCC”
inputs to the gates set up the logic to achieve the desired effect. In this case it does not matter
whether you apply a low or high signal to the Input as the output will always remain stuck-at-1 as
indicated by V=SHI in the diagram.
Figure 29 – Example of a stuck-at-1 AND and OR test circuit inserted into internal node H.
In Figure 29 above simply insert the stuck-at-1 test circuit from Figure 28, shown in a red dashed
box, into the Task 1 test schematic to force internal node H to a logic 1. In this example a simulation
graph would then be used to detect and verify the stuck-at-1 fault on node H using test vector 4.

32 | P a g e
5.5. Step 5: Verify each stuck-at fault using a simulation graph
Both stuck-at test methods demonstrated in Step 5.4 were applied to the Task 1 and Task 2 circuit
schematics to verify each fault individually and the results were confirmed to be good using the
simulation graphs. However, as there were 22 detectable faults in Task 1 and 17 in Task 2 it was
considered prudent to condense the volume of simulation graphs by representing only one fault
from each test vector as detailed in Figures 30 to 45 below. The Y axis in the graphs show the node
logic status as a high or low signal and the X axis represents the period in seconds. Additionally, the
yellow solid line indicates a Proteus 8 logic contention warning on the relevant node and the dashed
red line shows the period within the digital pattern generator that is being evaluated.
Figure 30 – Task 1 – Test vector 1 – A SA0 fault detected
The yellow line in Figure 30 above indicates a logic contention warning has been detected on input
A, which was defined to be VCC, but was in fact deliberately SA0 by shorting the supply to GND.
Propagation of the SA0 fault on the primary input A is proven as the O/P is expected to be at logic 1
in the first 500ms period as dictated by test vector 1 of Figure 20 above, but remains low.

33 | P a g e
A, which was defined to be GND, but was in fact deliberately SA1 by shorting the supply to VCC.
in the second 500ms period as dictated by test vector 2 of Figure 20 above, but remains high.
Figure 32 – Task 1 – Test vector 3 – B SA1 fault detected
B, which was defined to be GND, but was in fact deliberately SA1 by shorting the supply to VCC.
Propagation of the SA1 fault on the primary input B is proven as the O/P is expected to be at logic 0
in the third 500ms period as dictated by test vector 3 of Figure 20 above, but remains high.

34 | P a g e
Figure 33 – Task 1 – Test vector 4 – C SA1 fault detected
C, which was defined to be GND, but was in fact deliberately SA1 by shorting the supply to VCC.
Propagation of the SA1 fault on the primary input C is proven as the O/P is expected to be at logic 0
in the fourth 500ms period as dictated by test vector 4 of Figure 20 above, but remains high.
Figure 34 – Task 1 – Test vector 5 – E SA1 fault detected
The yellow line in Figure 34 above indicates a logic contention warning has been detected on input E,
which was defined to be GND, but was in fact deliberately SA1 by shorting the supply to VCC.
Propagation of the SA1 fault on the primary input E is proven as the O/P is expected to be at logic 0
in the fifth 500ms period as dictated by test vector 5 of Figure 20 above, but remains high.

35 | P a g e
Figure 35 – Task 1 – Test vector 7 – E SA0 fault detected
which was defined to be VCC, but was in fact deliberately SA0 by shorting the supply to GND.
Propagation of the SA0 fault on the primary input E is proven as the O/P is expected to be at logic 1
in the sixth 500ms period as dictated by test vector 7 of Figure 20 above, but remains low.
Figure 36 – Task 1 – Test vector 8 – J SA1 fault detected
Figure 36 above has had its internal node J deliberately SA1 by shorting the circuit path to VCC
though it is defined as logic 0 in the test vector. Propagation of the SA1 fault on the internal node J is
proven as the O/P is expected to be at logic 0 in the seventh 500ms period as dictated by test vector
8 of Figure 20 above, but remains high.

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Figure 37 – Task 1 – Test vector 9 – F SA0 fault detected
The yellow line in Figure 37 above indicates a logic contention warning has been detected on input F,
Propagation of the SA0 fault on the primary input F is proven as the O/P is expected to be at logic 0
in the eighth 500ms period as dictated by test vector 9 of Figure 20 above, but remains high.
Figure 38 – Task 1 – Test vector 15 – K SA0 fault detected
Figure 38 above has had its internal node K deliberately SA0 by shorting the circuit path to GND
though it is defined as logic 1 in the test vector. Propagation of the SA0 fault on the internal node K
is proven as the O/P is expected to be at logic 1 in the ninth 500ms period as dictated by test vector
15 of Figure 20 above, but remains low.

37 | P a g e
Figure 39 – Task 2 – Test vector 1 – J SA0 fault detected
Figure 39 above has had its internal node J deliberately SA0 by shorting the circuit path to GND
though it is defined as logic 1 in the test vector. Propagation of the SA0 fault on the internal node J is
proven as the O/P is expected to be at logic 1 in the first 500ms period as dictated by test vector 1 of
Figure 21 above, but remains low.
A, which was defined to be GND, but was in fact deliberately SA1 by shorting the supply to VCC.
in the second 500ms period as dictated by test vector 2 of Figure 21 above, but remains high.

38 | P a g e
Figure 41 – Task 2 – Test vector 3 – B SA1 fault detected
B, which was defined to be GND, but was in fact deliberately SA1 by shorting the supply to VCC.
Propagation of the SA1 fault on the primary input B is proven as the O/P is expected to be at logic 0
in the third 500ms period as dictated by test vector 3 of Figure 21 above, but remains high.
Figure 42 – Task 2 – Test vector 4 – C SA1 fault detected
C, which was defined to be GND, but was in fact deliberately SA1 by shorting the supply to VCC.
Propagation of the SA1 fault on the primary input C is proven as the O/P is expected to be at logic 0
in the fourth 500ms period as dictated by test vector 4 of Figure 21 above, but remains high.

39 | P a g e
Figure 43 above has had its internal node K deliberately SA1 by shorting the circuit path to VCC
is proven as the O/P is expected to be at logic 0 in the fifth 500ms period as dictated by test vector 8
of Figure 21 above, but remains high.
Figure 44 – Task 2 – Test vector 9 – F SA0 fault detected
The yellow line in Figure 44 above indicates a logic contention warning has been detected on input F,
Propagation of the SA0 fault on the primary input F is proven as the O/P is expected to be at logic 0
in the sixth 500ms period as dictated by test vector 9 of Figure 21 above, but remains high.

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Figure 45 above has had its internal node K deliberately SA0 by shorting the circuit path to GND
is proven as the O/P is expected to be at logic 1 in the seventh 500ms period as dictated by test
vector 15 of Figure 21 above, but remains low.
Figure 46 – Task 2 – Simulation – K SA0 fault not detected
which was deliberately SA0 by shorting the supply to GND. While no test vector has been defined
capable of detecting this fault, comparison of the output O/P logic to that of the output O/P in
Figure 23 shows no change. Thus the fault is not propagated or detected.

41 | P a g e
Figure 47 – Task 2 – Simulation – K SA1 fault not detected
which was in fact deliberately SA1 by shorting the supply to VCC. While no test vector has been
defined capable of detecting this fault, comparison of the output O/P logic to that of the output O/P
in Figure 23 shows no change. Thus the fault is not propagated or detected.
Figure 48 – Task 2 – Simulation – I SA1 fault not detected
Figure 48 above has had its internal node I deliberately SA1 by shorting the circuit path to VCC.
While no test vector has been defined capable of detecting this fault, comparison of the output O/P
logic to that of the output O/P in Figure 23 shows no change. Thus the fault is not propagated or
detected.

42 | P a g e
Figure 49 below lists each stuck-at fault that has been applied and then verified by propagation to an
observable output as proven by the logic inversion in the “Actual Output” column.
TASK
NUMBER
TEST
VECTOR
FAULT
DETECTED
EXPECTED
OUTPUT
ACTUAL
OUTPUT
FAULT
STATUS
1
1
A SA0
1 0
DETECTED
B SA0 DETECTED
C SA0 DETECTED
D SA0 DETECTED
H SA0 DETECTED
I SA0 DETECTED
J SA0 DETECTED
2 A SA1 0 1 DETECTED
3 B SA1 0 1 DETECTED
4
C SA1
0 1
DETECTED
H SA1 DETECTED
5
D SA1
0 1
DETECTED
E SA1 DETECTED
I SA1 DETECTED
7 ESA0 1 0 DETECTED
8
F SA1
0 1
DETECTED
G SA1 DETECTED
J SA1 DETECTED
K SA1 DETECTED
9
F SA0
0 1
DETECTED
G SA0 DETECTED
15 K SA0 1 0 DETECTED
2
1
A SA0
1 0
DETECTED
B SA0 DETECTED
C SA0 DETECTED
H SA0 DETECTED
I SA0 DETECTED
J SA0 DETECTED
2 A SA1 0 1 DETECTED
3 B SA1 0 1 DETECTED
4
C SA1
0 1
DETECTED
H SA1 DETECTED
8
F SA1
0 1
DETECTED
G SA1 DETECTED
J SA1 DETECTED
K SA1 DETECTED
9
F SA0
0 1
DETECTED
G SA0 DETECTED
15 K SA0 1 0 DETECTED
Figure 49 – Table showing detected stuck-at faults for Tasks 1 and 2.

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6. Conclusion
In the first phase of this assignment it could be seen that the single stuck-at fault modelling
technique can reduce a set of test vectors by a significant factor, but the process of minimising those
tests made the detection of several faults less exclusive.
Additionally, after the fault modelling process of the Task 1 schematic was completed it became
apparent that 100% of the faults were detectable when there was no fan-out present in the circuit.
Furthermore, the inclusion of fan-out in the Task 2 schematic prevented propagation of some stuck-
at faults, resulting in untestable nodes and undetectable faults.
Finally, Task 3 illustrated how the use of simulation software such as Proteus can be used to test and
verify circuits before actually designing and building them. Having never used Proteus, it was
necessary to browse on-line help tutorials and watch YouTube videos to gain an understanding of
the software application (Malik, 2014). A fault Simulator compares a circuit against a set of good
results by introducing faults through a test vectors and looking for a difference in the expected
outputs (Gosling, 1993). Benefits of simulation packages include a reduction in fault simulation time,
an early approximation of fault coverage, and the presentation of more visible, meaningful data to
high-level circuit designers.

44 | P a g e
7. Bibliography
 Dorf, R. (1997). The electrical engineering handbook. Boca Raton: CRC Press.
 Ghosh, S. and Chakraborty, T.J. (1991). On behaviour fault modelling for digital designs. J
Electron Test, 2(2), pp.135-151.
 Gosling, J. (1993). Simulation in the design of digital electronic systems. Cambridge [England]:
Cambridge University Press.
 Lombardi, F. and Sami, M. (1988). Testing and Diagnosis of VLSI and ULSI. Dordrecht: Springer
Netherlands.
 Malik, B. (2014). Proteus video tutorials for circuit designing. [online] Microcontrollers Lab.
Available at: http://microcontrollerslab.com/proteus-tutorials/
[Accessed 29 Feb. 2016].
 McMahan, C. (2010). Root cause analysis made easy: A Guide for Investigating Errors and
Improving Processes.
 Wilson, P. (2011). The circuit designer's companion. Oxford: Newnes.

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