Writing more complex models (continued)


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Modeling more complicated logic using sequential statements
Skills gained:
1- Model simple sequential logic using loops
2- Control the process execution using wait statements

This is part of VHDL 360 course

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Writing more complex models (continued)

  1. 1. VHDL 360©<br />by: Mohamed Samy<br /> Samer El-Saadany<br />
  2. 2. Copyrights<br />Copyright © 2010 to authors. All rights reserved<br />All content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Mohamed Samy and Samer El-Saadany or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws.<br />Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses.<br />Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact. <br />Product names and trademarks mentioned in this presentation belong to their respective owners.<br />VHDL 360 ©<br />2<br />
  3. 3. Objective<br />Modeling more complicated logic using sequential statements<br />Skills gained:<br />Model simple sequential logic using loops<br />Control the process execution using wait statements<br />VHDL 360 ©<br />3<br />
  4. 4. Sequential Statements<br />Sequential Statements<br />Case statement <br />If statement<br />loop statements<br />While Loop<br />For Loop<br />Wait statement<br />Think Hardware<br />VHDL 360 ©<br />4<br />
  5. 5. While-Loop<br /><Loop_Label> While <condition> loop <br /> -- list of sequential statements<br />end loop;<br />5<br />VHDL 360 ©<br />Syntax:<br /><ul><li>Keep looping while <condition> is true</li></ul><Loop_Label> optional label to identify the loop<br /><condition> Boolean expression that evaluates to either TRUE or FALSE<br />Example 1: count number of ONES in vector A<br />A: (7DOWNTO0), count: integerrange0to8;<br />PROCESS(A)IS<br /> VARIABLEtempCount, iteration:integerrange0to8;<br />BEGIN<br />iteration :=0;tempCount:=0;<br />my_loop:WHILE (iteration <= 7) LOOP<br />if A(iteration)= '1' then<br />tempCount:=tempCount+1;<br />endif;<br />iteration := iteration +1;<br />ENDLOOP;<br />Count <=tempCount;<br />ENDPROCESS;<br />
  6. 6. Skills Check<br />6<br />VHDL 360 ©<br />After the loop finishes what will be the value of “count” signal?<br />While count <10loop<br /> count <= count +1;<br />Endloop;<br />
  7. 7. Skills Check (Soln.)<br /><ul><li>This is an infinite loop since “count” is a signal which will only update its value when the process suspends
  8. 8. To fix this :</li></ul>“count” must be a variable<br />7<br />VHDL 360 ©<br />While count <10loop<br /> count := count +1;<br />Endloop;<br />Or<br />the process should be suspended inside the while loop using a wait statement<br />While count <10loop<br /> count <= count +1;<br /><wait statement>-- more on “Wait” later<br />Endloop;<br />Golden rules of thumb<br /><ul><li>Variables are updated immediately
  9. 9. Signals are updated after the process suspends</li></li></ul><li>Sequential Statements<br />Sequential Statements<br />Case statement <br />If statement<br />loop statements<br />While Loop <br />For Loop<br />Wait statement<br />Think Hardware<br />VHDL 360 ©<br />8<br />
  10. 10. For-Loop<br /><Loop_Label> for <idenifier> in <range> loop <br /> -- list of sequential statements<br />end loop;<br />9<br />VHDL 360 ©<br />Syntax:<br /><ul><li>For-loop</li></ul><Loop_Label> optional label to identify the loop<br /><identifier> loop iterator that can only be read inside the loop and is not available outside it <br /><Range> loop range and can be one of the following<br /> <integer> to <integer><br /> <integer> downto <integer><br />Example 2: Anding A with each bit in the vector B_bus<br />SIGNAL A: std_logic;<br />SIGNALB_bus,C_bus:std_logic_vector(7downto0);<br />…<br />process( A,B_bus)<br />begin<br />foriin7downto0loop<br />C_bus(i)<= A andB_bus(i);<br />endloop;<br />Endprocess;<br />
  11. 11. For-Loop<br />10<br />VHDL 360 ©<br />Example 3: 8-bit shift register<br />Library ieee;<br />Use ieee.std_logic_1164.all;<br />entityshift_registeris<br />Port(clk, D, enable :inSTD_LOGIC;<br /> Q :outSTD_LOGIC);<br />endentity;<br />architecture Behavioral ofshift_registeris<br /> signalreg:std_logic_vector(7downto0); <br />begin<br />process(clk)<br />begin<br />ifrising_edge(clk)then<br />if enable = '1' then<br />reg(7)<= d;<br /> foriin7downto1loop<br />reg(i-1)<=reg(i);<br /> endloop;<br />endif;<br />endif;<br />endprocess;<br />Q <=reg(0);<br />end Behavioral;<br />
  12. 12. Exercise 1 <br />The following diagram and flow chart show a “Serial In Parallel Out” register’s interface and describe how it behaves.<br />11<br />VHDL 360 ©<br />
  13. 13. Exercise 1<br />To complete the “Serial In Parallel Out” we need to do the following:<br />Add necessary assignments to the reset condition<br />Add a for loop to shift each bit of the internal register “reg” to the right<br />Decide the condition by which the 8 queued values goes outside the register<br />12<br />VHDL 360 ©<br />libraryieee;<br />useieee.std_logic_1164.all;<br />useieee.std_logic_unsigned.all;<br />entityserialinparalleloutis<br />port(clk:instd_logic;<br /> d :instd_logic;<br />rst:instd_logic;<br /> enable :instd_logic;<br />ready :outstd_logic;<br /> q :outstd_logic_vector(7downto0));<br />endserialinparallelout;<br />
  14. 14. Exercise 1<br />architecture behave ofserialinparalleloutis<br /> signal count:std_logic_vector(2downto0);<br />begin<br /> process(clk)<br /> variablereg:std_logic_vector(7downto0);<br /> begin<br /> ifrising_edge(clk)then<br /> ifrst= '1' then<br /> Q <= X"00";-- hexadecimal format<br /> <Here> <br /> else<br /> Ready <= '0';<br /> if enable = '1' then<br /> < Add the loop Here> <br />reg(7):= d;<br /> count <= count+1;<br /> …<br />VHDL 360 ©<br />13<br />
  15. 15. Exercise 1<br /> …<br /> if count = ?? then<br /> Q <=reg;<br /> count <="000";<br /> Ready <= '1';<br /> endif;<br /> endif;<br />endif;<br />endif;<br />endprocess;<br />end behave;<br />VHDL 360 ©<br />14<br />
  16. 16. Sequential Statements<br />Sequential Statements<br />Case statement <br />If statement<br />loop statements<br />While Loop <br />For Loop<br />Wait statement<br />VHDL 360 ©<br />15<br />
  17. 17. Wait Statement<br />wait [ sensitivity clause ] [ condition clause ] [timeout clause] ;<br />16<br />VHDL 360 ©<br />Syntax:<br />Process’ sensitivity list is only one means for controlling when a process is executed. Process execution can also be controlled with one or more waitstatements<br />The wait statement causes suspension of a process<br />Sensitivity clause, condition clause and timeout clause can optionally coexist in the same wait statement<br />sensitivity_clause: onsignal_name<br />Condition clause: until condition<br />timeout_clause: fortime_expression<br />Example 4:<br />wait; -- suspends process forever<br />waiton clock;-- suspends process execution until an event occurs on clock <br />waitfor10 ns;-- suspends process execution for 10 ns <br />waituntil A < B and enable;-- suspends process until the condition is true<br />waituntil A = '0' for2 ns;-- after A equals 0 wait 2 ns then resume execution of process<br />
  18. 18. Wait Statement<br />Example 5: Counter generator 1 <br />Architecture waveform oftestbenchis<br /> signal z :std_logic_vector(2downto0);<br />Begin<br /> process-- no sensitivity list<br /> begin<br /> foriin0to7loop<br /> z <=conv_std_logic_vector(i,3);-- converts integer to std_logic_vector<br /> waitfor20 ns;<br /> endloop;<br /> wait;<br /> Endprocess;<br />Endarchitecture;<br />17<br />VHDL 360 ©<br />
  19. 19. Skills Check<br />Architecture waveform oftestbenchis<br /> signal z :std_logic_vector(2downto0);<br />Begin<br /> process<br /> begin<br /> foriin0to7loop<br /> z <=conv_std_logic_vector(i,3);<br /> waitfor20 ns;<br /> endloop;<br />-- wait; <br /> Endprocess;<br />Endarchitecture;<br />18<br />VHDL 360 ©<br />What will happen if we remove this “wait”?<br />
  20. 20. Skills Check (Soln.)<br />Architecture waveform oftestbenchis<br /> signal z :std_logic_vector(2downto0);<br />Begin<br /> process<br /> begin<br /> foriin0to7loop<br /> z <=conv_std_logic_vector(i,3);<br /> waitfor20 ns;<br /> endloop;<br />-- wait;<br /> Endprocess;<br />Endarchitecture;<br />19<br />VHDL 360 ©<br />The waveform will not stop when Z reaches “111”, Z will start over again from “000”<br />
  21. 21. Skills Check<br />20<br />VHDL 360 ©<br />Catch me If you can!<br /><ul><li>Spot any problems in the below code
  22. 22. After fixing the problems, draw the waveforms
  23. 23. When do you think one of them can’t be used for clock generation?</li></li></ul><li>Skills Check (Soln.)<br />21<br />VHDL 360 ©<br /><ul><li>Initialization is a must in architecture “behave2”
  24. 24. Architecture “behave2” can’t generate a clock with duty cycle other than 50%</li></li></ul><li>Wait Statement<br /><ul><li>Signals in the sensitivity list form an implied wait condition</li></ul>22<br />VHDL 360 ©<br /><ul><li>Both Process 1 & Process 2 yield exactly the same simulation results
  25. 25. Process 3 differs only at initialization time…afterwards the simulation results will be similar to Process 1 & Process 2</li></li></ul><li>Skills Check<br />23<br />VHDL 360 ©<br /><ul><li>Are these equivalent in Simulation?</li></li></ul><li>Skills Check (Soln.)<br />24<br />VHDL 360 ©<br /><ul><li>Are these equivalent in Simulation?</li></ul>They are not equivalent<br />
  26. 26. Conversion Functions<br />25<br />VHDL 360 ©<br />Reference page<br />Syntax:<br />conv_integer()<br />Converts a std_logic_vector type to an integer;<br />Requires:<br />library ieee;<br />use ieee.std_logic_unsigned.all;<br />Or<br />use ieee.std_logic_signed.all;<br />conv_integer(std_logic_vector);<br />Example 6:<br />libraryieee;<br />useieee.std_logic_unsigned.all;<br />signal tour:std_logic_vector(3downto0);<br />signal n:integer;<br />n <=conv_integer(tour);<br />
  27. 27. Conversion Functions<br />26<br />VHDL 360 ©<br />Reference page<br />conv_std_logic_vector()<br />Converts an integer type to a std_logic_vector type <br />Requires:<br />library ieee;<br />use ieee.std_logic_arith.ALL;<br />Syntax:<br />conv_std_logic_vector(integer, number_of_bits)<br />Example 7:<br />libraryieee;<br />useieee.std_logic_arith.all;<br />signal tour:std_logic_vector(3downto0);<br />signal n:integer;<br />tour <=conv_std_logic_vector(n,4);<br />
  28. 28. Sharpen your Saw<br />
  29. 29. Lab work<br />Write the code for a Fibonacci sequence generator: <br />Output is the sum of the two previous outputs (0,1,1,2,3,5,8,13,…)<br />Port names & types must be:<br />Clk, rst: std_logic<br />Fib_out : integer<br />Don’t use inoutports<br />rst: synchronous reset<br />28<br />VHDL 360 ©<br />
  30. 30. Knight Rider LEDs<br />29<br /><ul><li>Write the code for a knight rider circuit: </li></ul>The shining led moves from left to right then from right to left…etc<br />VHDL 360 ©<br />
  31. 31. Contacts<br />You can contact us at:<br />http://www.embedded-tips.blogspot.com/<br />VHDL 360 ©<br />30<br />