1. Segmented Timing Arc Gate Delay Modelling
Method with Timing Anchor
Byungha Joo
San Jose, California, USA
byunghajoo@yahoo.com
Abstract—This paper discusses the segmented timing arc gate
delay modelling method. Until today, the gate was considered a
black box in the gate delay model. To improve accuracy, external
or non-linear parameters were added to the delay model. In the
new method, the black box is opened and propagation delay is
segmented into several timing arcs and connected by timing
anchors of input threshold voltage. Additionally, each timing arc
is modelled as a function of real source of driving force. In that
way, precise voltage based delay calculation is accomplished
while maintaining the same interfacing way with parasitic RC
elements from wirings.
Keywords—Delay Model; Gate Delay Equation; Input Slew;
Output Capacitance; PVT variation; Input Threshold Voltage;
Negative Delay; Timing Anchor; Segmented Timing Arc
I. INTRODUCTION
The importance of the delay model is growing as chip
complexity is increasing. In the past, the goal of designing
chips was to build a faster chip at any cost. But today,
minimizing power consumption is also considered a major
design goal, especially for mobile applications. This power and
performance co-optimization can be achieved by maximizing
utility of a clock period with useful data transactions. This
accurate gate delay model can contribute toward this goal.
CMOS propagation delay was modelled in a function of
resistor and capacitor product [1] [2]. Usually, propagation
delay is measured at half the supply voltage (½VDD). There was
an attempt to use the input threshold voltage (VIT) [3], but that
method was not able to cover timing gaps caused by the
threshold voltage (VIT) difference between instances. When
input slew rate effect was introduced, negative delay appeared
in characterization. Propagation delay is measured from ½VDD
but the CMOS logic gate responds to input change at VIT. This
gap between the logic threshold voltage and input threshold
voltage ( |½VDD – VIT| ) results in a negative value in
propagation delay [4], which CHARMS tried to avoid [5]. The
21-term polynomial to describe the CMOS gate delay was
proposed [6]. But soon, the table model was proposed with
higher accuracy [7]. There were more attempts to build an
analytic equation of propagation delay [8]. Eventually, the
table model was proven to be more accurate than a multi-
coefficient equation [9]. In all the previous gate delay models,
the gate had been considered a black box. The attempts to
improve accuracy have been done through the introduction of
new external characteristics and non-linear parameters.
In this paper, propagation delay of the gate is referenced
from ½VDD while parasitic wire RC models are calculated in
the traditional passive device timing model. However, the gate
is no longer a black box. The propagation delay is segmented
into several timing arcs and connected by the anchor of VIT.
Each arc represents a distinctive characteristic with respect to
the current-source element of that specific timing arc. Function
of the anchor determines how the timing arcs are combined to
calculate appropriate propagation delay.
II. DELAY ANALYSIS
A. Arcs of Propagation Delay
Propagation delay and logic threshold voltage
JEDEC defined that propagation delay is the timing interval
from the specified voltage level of input to the same level in
output [10]. Usually, ½VDD is chosen for the specified voltage
a.k.a. logic threshold voltage.
Input threshold voltage (VIT) and role of the gate
VIT is the input voltage level that makes the output logic
level transit to the opposite logic level. This voltage level is
different from ½VDD which is used in the propagation delay
definition. This VIT can be easily measured in DC analysis with
a circuit simulator. VIT is determined by the ratio of PMOS to
NMOS on-resistances. Each input pin has its own VIT from
transistor topology. In time domain, VIT has a very important
meaning in gate delay calculation. The role of the gate is
changed near VIT. The gate is in the “receiving load” role
before input reaches VIT since the gate is doing nothing, and
then changes to the “driving source” role after the input passes
VIT because the gate starts to drive the next gate connected to
output. Since the role of the gate is changed at VIT, gate delay
should be precisely modelled to best describe each role.
Timing Arcs
In Fig 1 and TABLE I, the timing arc from input crossing
½VDD to VIT is called the “receiver arc” because the gate is
observing the input level change until the voltage level reaches
VIT. In this “receiver arc”, propagation delay is determined by
the input driving force from the previous gate (N–1). There are
two parameter types based on input signal direction.
The timing arc from VIT to the output crossing ½VDD is
called the “driver arc”. Now the output driver of this gate is the
“driving source” to make a change in output node. Propagation
delay is determined by the output driver’s driving capability

2. and size of load. The anchor function determines availability
and usage of the four parameter types of the “driver arc”.
TABLE I. TYPES OF ARC AND ANCHOR
Receiver Arc Anchor Function Driver Arc
TIT FALL
TIT RISE
Non-Inverting
Inverting
Both
TITHLpHL TITLHpHL
TITLHpLH TITHLpLH
Fig 2 shows a conceptual timing arc drawing of a NAND
gate. From input A and B to output O, propagation delay is
divided into two timing arcs. Each input has its own input
threshold voltage (VIT A, VIT B). Since the anchors have
inverting function, there are two parameter types of “driver
arc”: TITHLpLH and TITLHpHL.
Timing Arc Characterization and Delay Calculation
Propagation delay from input to output is the sum of the
“receiver arc” and “driver arc”. Those two arcs are connected
by the anchor of VIT. Fig 3 shows how propagation delays are
constructed from timing arcs. Table II shows how propagation
delay can be calculated from different sets of timing arcs.
Anchor function “Both” can be found at the gate like XOR
gate, etc.
The timing parameter of the “driver arc” can be prepared
through the traditional characterization system. The only
change is that the timing measurement begins at VIT and stops
at ½VDD. The table model would work well, but any analytical
model can be used as long as the timing arc measurement
begins at VIT and stops at ½VDD and the analytical model meets
the expected level of accuracy.
TABLE II. PROPAGATION DELAY FORMULA
Propagation
Delay
Anchor
Function
Direction of
Input
Equation
TPHL
Non-Inverting Falling TIT FALL + TITHLpHL
Inverting Rising TIT RISE + TITLHpHL
TPLH
Non-Inverting Rising TIT RISE + TITLHpLH
Inverting Falling TIT FALL + TITHLpLH
In Fig 4, the timing value of the “receiver arc” is
dynamically calculated during the delay calculation by a logic
simulator. The active current source at this timing arc is the
output of the previous instance (N–1) which is connected to the
input of the gate. The rise/fall times (TRISE, TFALL) of the
previous instance (N–1) are available from the characterization
database. The timing of the “receiver arc” is derived using the
Triangle Proportionality Theorem.
TIT RISE(N) = (VIT – ½VDD) × TRISE(N–1) ÷ (0.8VDD – 0.2VDD) (1)
TIT FALL(N) = (½VDD – VIT) × TFALL(N–1) ÷ (0.8VDD – 0.2VDD) (2)
B. Timing Hazards of Sequential Cells and Timing Arcs
Timing hazard can be modelled with three timing arcs –
“receiver arc” of data, “receiver arc” of clock, and “driver arc”
of data to the clock circuit path in Fig 5. The “receiver arc” of
data has two types of timing arc parameters: TIT FALL D and TIT
RISE D. But the “receiver arc” of clock has only one timing arc
input output
Anchor:
VIT
Receiver Arc Driver Arc
Fig 1. Anchor and Arcs
VIT A
A
B
OTITHLpLHTIT FALL
TIT RISE TITLHpHL
VIT B
Fig 2. Sample of timing arcs in NAND gate
VIT
½VDD
½VDD
TITLHpHL
TIT RISE
TPHL
TITHLpLH
TIT FALL
TPLH
INPUT
OUTPUT
Fig 3. Inverting function and ½VDD > VIT
½VDD
0.2VDD
0.8VDD
VIT
TFALL(N–1)
TIT FALL(N)
Fig 4.Calculation of TIT FALL from TFALL
D
CK
O
TIT FALL D
TIT RISE D
TIT RISE CK
TIT SETUP
TIT HOLD
VIT D
VIT CK
Fig 5. Timing arcs of setup and hold time in D-flipflop
TIT RISE D
VIT D
½VDD
½VDD
TIT SETUP D=1
D
CK
VIT CK
TIT RISE CK TIT FALL D
TIT HOLD D=1
Fig 6. Setup and Hold Timing when D=1

3. parameter, TIT RISE CK, for rising edge flip flop. The “driver
arc” is equivalent to the pure timing interval requirement for
the sequential gate between the data and clock signal.
In Fig 6, pure setup and hold times (TIT SETUP, TIT HOLD) for
the D-flipflop is the “driver arc” measured at the input
threshold voltage of each pin (VIT D and VIT CK).
Setup and Hold Time Check when D = 1
Timing interval from D
rising at ½VDD to CK
rising at ½VDD
> TIT SETUP D=1 + TIT RISE D – TIT RISE CK (3)
Timing internal from CK
rising at ½VDD to D
falling at ½VDD
> TIT HOLD D=1 + TIT RISE CK – TIT FALL D (4)
Setup and Hold Time Check when D = 0
Timing interval from D
falling at ½VDD to CK
rising at ½VDD
> TIT SETUP D=0 + TIT FALL D – TIT RISE CK (5)
Timing interval from CK
rising at ½VDD to D rising
at ½VDD
> TIT HOLD D=0 + TIT RISE CK – TIT RISE D (6)
C. Process, Voltage and Temperature variation
Linear regression with derating factor has been used in
industry to generate timing databases at many Process, Voltage,
and Temperature (PVT) variations. The derating factor has
been multiplied to a single timing arc delay as in (7). In the
new delay model, each timing arc is converted individually
with linear regression of the derating factor as described in (8).
Let Derating Factor = K,
Propagation
Delay
= Propagation Delay Reference*K (7)
Propagation
Delay
= Receiver Arc(K*Slew(N–1)) + K*Driver Arc (8)
III. EXPERIMENTS
A. Circuit level input threshold voltage (VIT) variations
Since VIT has a very important role in this new delay model,
sensitivity of VIT against PVT variation needs to be checked.
The VIT of an inverter is traced while the supply voltage is
varying from 0.66*VDD to 1.33*VDD in Fig 7, and Fig 8 shows
the normalized VIT with respect to temperature change.
With 60+ nano-process technology, at every 10% of the
supply voltage change, the VIT variation was less than 3% and
VIT was shifted less than 1% per 10⁰C temperature variation.
B. Extracting timing arcs from propagation delay
In Fig 9, propagation delay of a four input NAND gate was
measured while increasing input slew up to 2 nanoseconds. The
voltage gap between the logic threshold voltage and input
threshold voltage ( |½VDD – VIT| ) results in different curve
shapes in TPHL and TPLH.
From the same simulation deck, it is possible to measure
the “receiver arc” and “driver arc”. “Receiver arc” shown in
Fig 10 are symmetrical with respect to the x-axis. In Fig 11,
both rising and falling “driver arc” are presented in similar
curve shape. It is clear that each timing arc in Fig 10 and 11 is
much easier to describe in a mathematic model than the
propagation delay in Fig 9.
0.97
0.98
0.99
1
1.01
1.02
1.03
1.04
0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4
ff
fs
nn
sf
ss
Fig.7 Normalized VIT changes from VDD variation
0.4
0.41
0.42
0.43
0.44
0.45
0.46
0.47
0.48
0.49
-40 -20 0 20 40 60 80 100 120
ff
fs
nn
sf
ss
Fig. 8 Normalized VIT change from Temperature variation
0
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tphl pin A
tplh pin A
tphl pin B
tplh pin B
tphl pin C
tplh pin C
tphl pin D
tplh pin D
Fig 9. Propagation delay of NAND4 vs. input slew
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tit_fall pin A
tit_rise pin A
tit_fall pin B
tit_rise pin B
tit_fall pin C
tit_rise pin C
tit_fall pin D
tit_rise pin D
Fig 10. Receiver arc vs. input slew
0
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1E-10
1.5E-10
2E-10
2.5E-10
3E-10
3.5E-10
0 5E-10 1E-09 1.5E-09 2E-09 2.5E-09
tit_lhphl pin A
tit_hlplh pin A
tit_lhphl pin B
tit_hlplh pin B
tit_lhphl pin C
tit_hlplh pin C
tit_lhphl pin D
tit_hlplh pin D
Fig 11. Driver arc vs. input slew
0
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2E-10
3E-10
4E-10
5E-10
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7E-10
0 5E-10 1E-09 1.5E-09 2E-09 2.5E-09
tphl A ckt sim
tplh A ckt sim
tphl B1 ckt sim
tplh B1 ckt sim
tphl B2 ckt sim
tplh B2 ckt sim
tphl A model
tplh A model
tphl B1 model
tplh B1 model
tphl B2 model
tplh B2 model
Fig 12. AO21 circuit simulation and delay model value

4. C. Calculate propagation delay and comparison
From the authors’ experiment, the error rate of the new
delay model against circuit simulation was average 5.37% at
output loading axis and 0.38% at input slew axis, but the
largest error rate was 1188% and 717% at near-zero circuit
simulation delay. In Fig 12, AO21 has two-stage transistor
depths from input to output and high output loading. AO21
model delay value follows circuit simulation delay curves very
closely. Between the 2-D table model and the new delay model,
difference in propagation delay is negligible with linear
interpolation.
D. Extracting timing arcs from Timing hazard
For D-flipflop, when setup and hold hazard timings were
measured at ½VDD in Fig 13, the value of data determined the
shape of the hazard timing. Under the same simulation
environment, the “driver arc” of the setup and hold hazard
timings were measured at the input threshold voltages (VIT D,
VIT CK) in Fig 14 and the measurement trace appears to be
independent of data values. Two “receiver arcs” of data and
clock inputs can be added later to build the full length of the D-
flipflop hazard timing as described in Fig 5 and (3) ~ (6).
By most ASIC cell library venders, setup and hold times
have been set to a certain pessimistic number to cover all data
values with a safety margin. Now, it is possible to calculate the
exact timing hazard value using the new delay model, so the
safety margin can be minimized.
E. Timing data and PVT variation
PVT variation and derating results are shown in Fig 15. The
top-left chart is the circuit simulation result in NN corner and
the top-right chart is the SS corner result. In the NN corner,
negative delay can be found at slow input slew and low output
load area. However, the negative delay almost disappears in SS
corner. The 2-D table derating to the SS corner at bottom-right
chart has the same number range as the top-right chart, but
keeps the similar curvature shape from the NN corner. So the
negative delay exists like it does in the NN corner. The bottom-
left chart of SS corner from the new delay model resembles the
top-right chart from the circuit simulation SS result. The error
rate between the new delay model against circuit simulation
was average 7.13% at output loading axis and 6.67% at input
slew axis, and twice accurate compared to the 2-D table model.
IV. CONCLUSION AND FUTURE RESEARCH ISSUES
The authors propose an open box gate delay modelling
method with segmented timing arcs. Through this method,
timing arcs are easy to describe in a math model and there is no
need to add a large margin in the timing hazard value.
Eventually, a clock period will be able to hold greater numbers
of valid data transactions under the same clock speed.
Additionally, linear regression can produce timing data at other
PVT corners. This new model will be a stepping stone toward
future research such as switching current intensity, Miller
capacitance effect modelling, and power calculation.
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[10] JEDEC, "Propagation (delay) Time, Low-to-high-level Output (tPLH)."
Dictionary Entries. N.p., n.d. Web. 24 Sept. 2016.
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5E-10
0 5E-10 1E-09 1.5E-09 2E-09 2.5E-09
t_hold_0
t_hold_1
t_setup_0
t_setup_1
Fig 13. D-flipflop timing hazards at ½ VDD vs. input slew
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0 5E-10 1E-09 1.5E-09 2E-09 2.5E-09
t_hold_0
t_hold_1
t_setup_0
t_setup_1
Fig 14. D-flipflop timing hazard driver arcs at VIT vs. input slew
Fig 15. TPHL PVT variation results of circuit sim and derating