1. System Monitoring Display and Logic Device
Observations
EE 2511 Logic Design Laboratory
Final Project
Team members:
Ali Alajmi
Khaled Alajmi
Ibrahim Almuqrin
Bruno Diaz
Due Date: May 30th 2014
Instructor: August Allo

2. For our project we needed to design a logic circuit that took in 3 inputs and the outputs
follow a certain sequence not depending on which of the inputs were switched on but how many
have 4 possible states. The project also required us to follow a certain sequence for the output,
which may or may not require a flashing light depending on what was needed. This circuit
required loops and delays that needed to be implemented with the tools available to us in
SimUaid. Although using counters to create the delays was considered it was determined that
using shift registers would be better since they were easier to control particularly. We developed
two designs for this project, and initial design that did technically meet all the requirements of
the project and an improved design that fixed what we felt the other circuit was lacking and
improved it. Our finished circuit is shown in figure C-A1.
The circuit works in two stages, the condition discrimination stage and the output stage.
The first stage uses combination logic to discriminate which of the 4 conditions were met and the
second outputs the corresponding sequence needed to indicate what type of conditions were met.
In the condition discrimination stage combination logic is used to determine how many of
conditions were met outputting a 1 when the conditions met for a state were met.. The There are
four different states that will output a 1 the “all 1” state which will output a 1 when all inputs are

3. 1 the “all 0” state when all of the inputs are 0, The “two 1s” state when two and only two inputs
are 1, and the “one 1” state when 1 and only 1 condition is met.
The all 1 condition is fairly easy to implement, a 3 input AND gate that will only display
a 1 if all inputs are 1. The all zero condition can output a 1 if that AND gate had all of its inputs
inverted displaying a 1 only when all inputs are 0, this however can be replaced with a NOR gate
which does the exact same thing. The next two states were a bit trickier. The general approach to
develop the output for next two is to divide the logic into what things have to be met to output a
1. For the two 1 condition we know that there has to be two 1s that occurs somewhere and we
also know that three 1s cannot occur at the same time this happens, so three AND gates were
attached at the three possible places two 1s could occurred this in term was attached to an OR
gate to display a 1 if it ever happened the other limitation is that all three of inputs can’t be 1 so
the three inputs were attached to an AND gate and both the OR gate and the AND gate were
attached to an exclusive OR gate so that it will only display a 1 is its 01. The one 1 condition is
made by putting two limitations on it a 1 has to be present in at least one of the inputs an three
input OR gate easily accomplishes this task the other limitation is that two or more 1s cannot be
present , we can reuse the AND gates for the previous condition and attach it to a NOR gate that
displays a 1 if and only if there are no two 1s in the inputs. These two things are then attached to
an AND gate that displays a 1if both of these limitations are held.
The second stage was used to output what we needed when our conditions were met. It
took in the four outputs from the previous stage to determine what type of outputs happens. It
used four shift registers and 1 d flip flop latch. [The behavior] 2 of the shift registers were 11 bit
long and two of them were 2bit long. The shift registers were chosen because they could be used
to accomplish a trick to get them to flash. Two methods were used depending on the number of
bits . One of the 2 bit registers used were to output the all 0 output attached to the green light it
didn’t used any flashing so the register was only used for its clear input used to determine if any
condition or permanent flashing condition was met,
We had four different outputs, the one 1 output needed a 10 cycles delay to represent a 5
second delay and needed to flash with half second delay between each flash, logically this would
be represented with a cycle of either 1 or 0. All the conditions used stuff with clear inputs to
determ of the other conditions were true

4. The one 1 condition output was implemented using an 11 bit right shift register. The way
it worked was that once the one 1 condition was met and output a 1 this would in turn toggle off
the clear on the register the output for the yellow light was connected to the 1st
bit of the register.
The register was already set up to shift in numbers from a NAND gate connected to the first and
last bits of the registers so once the clear was toggled off the a 1 would continually be shifted
until a 1 reached the last digit casing the NAND gate to output a 0 thus when the next shift was
clocked in there would be a 0 and a 1 on its inputs causing it return to outputting a 1 but then as
this 1 shifted into the 1st
digit again this could cause the NAND to output a 0 into the feeding
system causing this to endlessly alternate between 0 and 1 until the clear input on the shift
register read a 1 which indicated that one of the other conditions were met forcing the circuit to
transition to that output. The Number of bits were chosen to implement the 10 cycle delay,
originally a 10 bit register was chosen since it would take 10 shifts to get to the flashings state,
but as we later found the particular trick we used to achieve the flashing state after 10 cycles did
not work since for an even numbered register for every 10 cycles two 1s would repeat so an odd
number register was needed. To overcome the fact that by doing this we would be 1 cycles over
we set up the register to have the load input activated and load two 1s at first two bits when the
first two bits are 00 once the bits are load the load is then turned off and shift can continue, in
this way we could have continue uninterrupted alternation between 0s and 1s while style having
an exactly 10 cycle delay.
The 0 1s was met using a register that would output a 1 if and only if its clear input was
0. the clear input was attached to an or gate that read if any of the other conditions were met.
The all 1s conditions was controlled using a 2 bit register that alternated between 0 and 1
for every clock cycles. This was accomplished attaching an inverter to the last bit and connected
to the shift feed input and was set up to continue feeding in digits, by doing this the output will
keep alternating between 0 and 1. The condition is activated by having the clear attached to an
inverted of a D latch flip flap that would read in both when the all 1s condition was met or when
it read in the end of the 2 1 condition delay as we will see below.
The two 1 output worked much the same as the one 1 output except when the 10 cycles
were reached instead of using the flashing trick like the yellow light it would activate the latch of
the all 1s condition creating a permanently red flashing light.
We designed four tests to test the circuit as seen in figures T-A1 to T-A4

5. In T-A1 we test the on 1 condition by bringing one of the conditions high and then low to
see if the 5 second delay and flashing would work. It did and we brought the condition back to
low to see that it could still go green.
In T-A2 we raised both conditions high and let it get to the flashing point then lowered
both to low to see if it still maintain the red flashing state.
In T-A3we raised all three conditions simultaneously and saw that it remained in the red
flashing state. And finally in TA-4 we raised one but then lowered it before it could get to the

6. flashing state to see if it will transition back to green then we lowered both and got to flashing
and lowered it again.
Our final design was actually an improvement on a previous design. Our original design
is seen in figure C-1B
Though his design did meet the project requirement the over use of combination logic to
try to maintain the states absolute caused significant propagation delay. The propagation delays
seen in he old design caused the circuit 50 nanoseconds to respond to a condition change which
we found to be unacceptable so the redesign was done to mitigate this. With our new design as
you can see in our test the circuit responds to changes in the inputs with a 6-nanosecond delay an
improvement that was nearly 1/10th
of the pervious design. Other improvements over the old
design was the use of the NAND gate to produces the alternating 0 and 1 routine.
In conclusion we met the requirements for the project and implemented them. There were
some difficulties such as misinterpreting the project requirements but these were overcome.
And as the last part of our report here is the list of 15 items that use digital logic

7. 1. House Bell.
2. Remote Control.
3. LCD displays
4. Digital clock.
5. Washing machine.
6. Microwave oven.
7. Digital camera.
8. Headphones.
9. Flash Drive.
10. Bluetooth Handfree.
11. Wireless Router.
12. ATM machine.
13. Parking tickets Auto-pay machine.
14. Water Dispenser.
15. Air conditioner.