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Server Router
Client1
Client2
Client3
Reference: Carzaniga, A., and Wolf, A.L. Forwarding in a content-based network. In SIGCOMM, 163-174, 2003
0
50
100
150
200
250
300
350
1 2 3 4 5
MatchingTime(ms)
Total # of Routing Constraints
Matching Time Per Message
DATA
Hardware
Accelerator
D-wall
Processor
FIFO/
SRAM
Node1
Node3
Node2
Routing Overview
Decryption
Engine
Node 0
packet
packet
packet
CORE
CAMDecoder
Bloom
Filter 1
match[4]
match[3]
match[2]
match[1]
Deep Packet Inspection
Bloom
Filter 2
Bloom
Filter 3
Bloom
Filter 4
Payload
address
PayloadPayloadPayload
match[4]
match[3]
match[2]
match[1]
count
hit/miss
count
address
hit/miss
Hash Function 1
Hash Function 2
Hash Function 3
Hash Function 4
Bloom
MEM
Bloom
MEM
Bloom
MEM
Bloom
MEM
No Match
1
0
1
1
PacketPacketPacketPacket
Hash Function 1
Hash Function 2
Hash Function 3
Hash Function 4
Bloom
MEM
Bloom
MEM
Bloom
MEM
Bloom
MEM
Match
1
1
1
1
PacketPacketPacketPacket
Hash Unit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Payload
Bloom Filter
Memory
9 7 14
0292h
Addr:0292h == ‘1’
Pattern Matcher
Payload
match = ‘1’
Addr:0292h != ‘1’
match = ‘0’
CORE
CAMDecoder
Bloom
Filter 1
match[4]
match[3]
match[2]
match[1]
Deep Packet Inspection
Bloom
Filter 2
Bloom
Filter 3
Bloom
Filter 4
address
match[4]
match[3]
match[2]
match[1]
count
hit/miss
count
address
hit/miss
4-bit
comparator
4-bit
register
4-bit
comparator
Count
4-bit
register
4-bit
comparator
4-bit
register
4-bit
comparator
4-bit
register
E
N
C
O
D
E
R
Address of the matched
location
Hit or miss
CONTENT ADRESSABLE MEMORY
0
1
0
CountCountCountCount
0
2H
Hit
CORE
CAMDecoder
Bloom
Filter 1
match[4]
match[3]
match[2]
match[1]
Deep Packet Inspection
Bloom
Filter 2
Bloom
Filter 3
Bloom
Filter 4
address
count
hit/miss
address
hit/miss
Hardware
Accelerator
D-wall
Processor
FIFO/
SRAM
packet
packet
packet Node1
Node3
Node2
Routing Overview
Decryption
Engine
Node0
IM
PC
1
RF SRAM
or
FIFO
Thread
Scheduler
PC
2
A
L
U
T1
T2
Inst
1
Inst
2
T1
T2
Packet Modification
Packet Encryption
Dual-thread Processor
0001Address
Destination IP Destination Address
(Hex)
10.1.1.3 10456789
10.1.2.3 87345614
10.1.3.3 50758185
0001
Dest. IP
XXXXXXXX
Source IP
A0010003
Payload
48494A4B4C4D4E4F 00420
HIT
ForwardingTable
Destination IP Destination Address
(Hex)
10.1.1.3 10456789
10.1.2.3 87345614
10.1.3.3 50758185
Address 1011
Dest. IP
XXXXXXXX
Source IP
A0010003
Payload
48494A4B4C4D4E4F 00420
0001
10456789
ForwardingTable
Address 1011
Dest. IP
XXXXXXXX
Source IP
A0010003
Payload
48494A4B4C4D4E4F 00420
0001
10456789
Destination IP Destination Address
(Hex)
10.1.1.3 10456789
10.1.2.3 87345614
10.1.3.3 50758185
ForwardingTable
0001Address 0001
Dest. IP
XXXXXXXX
Source IP
A0010003
Payload
48494A4B4C4D4E4F 00420
Destination IP Destination Address
(Hex)
10.1.1.3 10456789
10.1.2.3 87345614
10.1.3.3 50758185
MISS
ForwardingTable
Node1
Node3
Node2
Hardware
AcceleratorNode 0
D-wall
Processor
FIFO/
SRAM
packet
packet
packet
Routing Overview
Decryption
Engine
Project Timelines
Date Tasks Status
April 11th, 2016 Multi-threaded Processor Completed
April 18th, 2016 Multi-core Multi-threaded Processor Completed
April 25th, 2016 RSA Integration with Processor Completed
May 2nd, 2016 Hardware Accelerator Integration with
Processor
Completed
May 5th, 2016 Performance Analysis of the System Completed
Presentation533_Final

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Presentation533_Final