Computer architecture MCQ's and ANSWER

1. COMPUTER
ARCHITECTURE
MCQ’S & ANSWERS
PART – 2
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3. 31. The logic operations are implemented using _______ circuits.
a. Bridge
b. Logical
c. Combinatorial
d. Gate Answer: - C
32. The carry generation function: ci + 1 = yici + xici + xiyi, is
implemented in ____________.
a. Half adders
b. Full adders
c. Ripple adders
d. Fast adders Answer: - B
Answer: - B
33. The carry in the ripple adders
a. Are generated at the beginning only
b. Must travel through the configuration
c. Is generated at the end of each operation
d. None of the above
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4. 34. In full adders the sum circuit is implemented using ________.
a. AND & OR gates
b. NAND gate
c. XOR gate
d. XNOR gate Answer: - C
35. The usual implementation of the carry circuit involves _________.
a. AND and OR gates
b. XOR gate
c. NAND gate
d. XNOR gate
Answer: - B
Answer: - B
36. A _______ gate is used to detect the occurrence of an overflow.
a. NAND
b. XOR
c. XNOR
d. AND
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5. 37. In a normal adder circuit the delay obtained in generation of
the output is _______.
a. 2n + 2
b. 2n
c. n + 2
d. None of the above
Answer: - A
38. The final addition sum of the numbers, 0110 & 0110 is
a. 1101
b. 1111
c. 1001
d. 1010 Answer: - A
Answer: - A
39. The product of 1101 & 1011 is
a. 10001111
b. 10101010
c. 11110000
d. 11001100
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6. 40. We make use of ______ circuits to implement multiplication.
a. Flip flops
b. Combinatorial
c. Fast adders
d. None of the above Answer: - C
41. Which of the following shift operations divide a signed binary number
by 2 ?
a. Logical left shift
b. Logical right shift
c. Arithmetic left shift
d. Arithmetic right shift Answer: - B
Answer: - B
42. Normally digital computers are based on
a. AND and OR gates
b. NAND and NOR gates
c. NOT gate
d. None of the above
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7. 43. BCD stands for
a. Boolean code definition
b. Binary coded division
c. Binary coded decimal
d. None of the above Answer: - C
44. The basic circuit ECL supports the
a. NAND logic
b. NOR logic
c. EX-OR logic
d. OR-NOR logic
Answer: - D
Answer: - B
45. An adder-subtractor single unit can be designed using full adder and
a. OR gates
b. XOR gates
c. NOR gates
d. NAND gates

8. 46. Which of the following is not a universal building block ?
a. 2 input NAND gate
b. L3 input NAND gate
c. 2 input XOR gate
d. None of the above Answer: - C
47. CARRY in half adder can be obtained using
a. EX-OR gate
b. AND gate
c. OR-gate
d. EX-NOR gate
Answer: - B
Answer: - B
48. A NAND gate has inputs A and B. It's output is connected to the both of the
inputs of another NAND gate. An equivalent gate for these two NAND gates is
a. OR gate
b. AND gate
c. NOR gate
d. XOR gate

9. 49. The operation which commutative but not associative is
a. AND
b. OR
c. XOR
d. NAND Answer: - D
50. In which of the following gates, the output is 1 if and only if at
least one input is 1?
a. OR
b. NOR
c. AND
d. NAND Answer: - A
Answer: - A
51. The minimum time delay between two successive memory
read operations is ______.
a. Cycle time
b. Latency
c. Delay
d. None of the above

10. 52. The logical addresses generated by the CPU are mapped onto
physical memory by ____.
a. Relocation register
b. TLB
c. MMU
d. None of the above Answer: - C
53. Circuits that can hold their state as long as power is applied is _______.
a. Dynamic memory
b. Static memory
c. Register
d. Cache
Answer: - B
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11. 54. The number of external connections required in 16 X 8
memory organization is _____.
a. 14
b. 19
c. 15
d. 12
Answer: - A
Answer: - C
55. In a 4M-bit chip organization has a total of 19 external
connections. Then it has _______ address if 8 data lines are there.
a. 10
b. 8
c. 9
d. 12

12. 56. The reason for the implementation of the cache memory is
a. To increase the internal memory of the system
b. The difference in speeds of operation of the processor and memory
c. To reduce the memory access and cycle time
d. All of the above Answer: - B
57. The effectiveness of the cache memory is based on the
property of ________.
a. Locality of reference
b. Memory localisation
c. Memory size
d. None of the above Answer: - A
Answer: - B
58. The correspondence between the main memory blocks and
those in the cache is given by _________.
a. Hash function
b. Mapping function
c. Locale function
d. Assign function

13. 59. When two or more clock cycles are used to complete data
transfer it is called as ________.
a. Single phase clocking
b. Multi-phase clocking
c. Edge triggered clocking
d. None of the above
Answer: - b
Answer: - C
60. The drawback of building a large memory with DRAM is
a. The large cost factor.
b. The inefficient memory organization.
c. The Slow speed of operation.
d. All of the above.