A note on the Register Set and Addressing Modes in Microprocessor Motorola 68020.

1. computer organization and architecture
Topic- Write a note on the Register Set and Addressing Modes
in Microprocessor Motorola 68020.
GROUP NO- VI
Jubin kashyap
DEPT- ELECTRICAL
Roll No- EEB17020
Aniket Raj
DEPT- ELECTRICAL
Roll No- EEB17031
Muzammil Ahmed
DEPT- ELECTRICAL
Roll No- EEB17040

2. SHORT INTRODUCTION ABOUT MOTORALA µP 68020(MC68020)
The MC68020 is the first full 32-bit implementation of the M68000 family of
microprocessors from Motorola. The MC68020 is implemented with 32-bitregisters
and data paths, 32-bit addresses, a rich instruction set, and versatile addressing
mode.
The main features of the MC68020 are as follows:
• Object-Code Compatiblewith Earlier M68000 Microprocessors
• Addressing Mode Extensions for Enhanced Support of High-Level Languages
• Full Support of Virtual Memory and Virtual Machine
• Sixteen 32-Bit General-Purpose Data and AddressRegisters
• Two 32-Bit Supervisor Stack Pointers and Five Special-PurposeControl
Registers
• Eighteen Addressing Modes and Seven Data Types
Types Of Registers in MC68020
1. Data registers
➢ It stores the data being transferred to and from the immediate
access storage
➢ The MC68020 Has Eight 32-Bit Multifunction Data Registers
2. Address registers
➢ either stores the memory address from which data will be
fetched from the CPU, or the address to which data will be
sent and stored.
➢ The MC68020 Has Seven 32-Bit General Addressing Registers
3. User stack pointer
➢ is a small register that stores the address of the last program
request in a stack
➢ The MC68020 Has Three 32-Bit Stack Pointers
4. Program counter
➢ It contains the address (location) of the instruction being
executed at the current time
➢ The MC68020 Has A 32-Bit Program Counter
5. Condition code
➢ It is used for storing the current values of the condition codes

3. 6. Interrupt pointer
7. Master stack pointer
8. Status register
➢ it keeps the information about the state of the processor.
➢ The MC68020 Has A 16-Bit Status Register
9. Vector base register
➢ holds the exception base address for all exceptions that are
taken to Monitor mode
➢ The MC68020 Has A 32-Bit Vector Base Register
10. Alternate function code registers
➢ The MC68020 Has Two 3-Bit Alternate Function Code Register
11. Cache control register
➢ provide information on the size and architecture of the
instruction and data caches
➢ The MC68020 Has A 32-Bit Cache Control Register
12. Cache address register
➢ The MC68020 Has A 32-Bit Cache Address Register

4. Addressing Modes in 68020
There are total 18 differents types of addressing modesin 68020
● Register Direct
1. Data
2. Address
● Register Indirect
3. Address
4. Address with Postincrement
5. Address with Predecrement
6. Address with Displacement
● Address Register Indirect with Index
7. 8-Bit displacement
8. Base displacement
● Memory indirect
9. Postindexed
10. Preindexed
● Program Counter Indirect
11. with Displacement
● Program Counter Indirect with Index
12. 8-Bit displacement
13. Base displacement

5. ● Program Counter Memory Indirect
14. Postindexed
15. Preindexed
● Absolute Data Addressing
16. Short
17. Long
● Immediate
18. Immediate
Register Direct mode
1: Data register direct mode
2: Address register direct mode
➢ In the register direct modes, the instruction specifies the data or address register containing
the operand;
3: Address register indirect mode
➢ the operand is in memory;
➢ the instruction specifies which address register contains the address of the operand in
memory;
4: Address Register Indirect with Postincrement mode
➢ the operand is in memory;
➢ the instruction specifies which address register contains the address of the operand in
memory;
➢ after the operand address is used, it is incremented by 1, 2 or 4 depending on the operand
size (byte, word, long word respectively)
➢ if the address register is stack pointer and operand size is byte, the address is incremented
by 2 to preserve alignment
5: Address Register Indirect with Predecrement mode
➢ the operand is in memory;
➢ the instruction specifies which address register contains the address of the operand in
memory;
➢ before the operand address is used, it is decremented by 1, 2 or 4 depending on the operand
size (byte, word, long word respectively)
➢ if the address register is stack pointer and operand size is byte, the address is decremented
by 2 to preserve alignment;

6. 6: Address Register Indirect with Displacement mode
➢ the operand is in memory;
➢ the operand's address in memory is the sum of:
● an address contained in an address register (the instruction specifies which register
● a 16-bit displacement integer (the instruction specifies it)
Address Register Indirect with Index mode
7: 8-Bit Displacement
8: Base Displacement
➢ The operand's address in memory is the sum of:
● an address contained in an address register (the instruction specifies which register
● a scaled index register (the instruction specifies which register); and
● a 8-bit displacement or a base displacement integer (the instruction specifies it)
9: Memory Indirect Post-indexed mode
➢ the operand is in memory and the operand's address is in memory too;
➢ an intermediate address IA is obtained as: IA = address (in reg.) + base displacement (in
instr.)
➢ the operand is at the final address, obtained as: value @IA + index (in reg.) + outer
displacement (in instr.)
10: Memory Indirect Pre-indexed mode
➢ the operand is in memory and the operand's address is in memory too;
➢ an intermediate address IA is obtained as: IA = address (in reg.) + base displacement (in
instr.) + index (in reg.)
➢ the operand is at the final address, obtained as: value @IA + outer displacement (in instr.)
11: Program Counter Indirect with Displacement mode
➢ the operand is in memory;
➢ the operand's address is the sum of the address in PC and a 16-bit displacement (in the
instruction);
➢ the operand is at the final address, obtained as: value @IA + outer displacement (in instr.);
this mode is allowed only for reads;

7. Program Counter Indirect with Index modes
12/13: PC Indirect with Index
➢ (8-Bit/Base Displacement) are like modes 7/8 Reg. Indirect with Index, except the PC is the
base register;
➢ the operand's address is the sum of the address in PC, an 8-bit or base displacement (in the
instruction) and the scaled index (in the index register);
Program Counter Memory Indirect modes
14/15: PC Mem. Indirect Post-/Pre-index modes
➢ are like modes 9/10 Memory Indirect Post-/Pre-index, except the PC is the base register;
➢ the operand's address is the sum of the address in PC, an 8-bit or base displacement (in the
instruction) and the scaled index (in the index register);
Absolute addressing modes
16: Absolute Short Addressing mode
17: Absolute Long Addressing mode
➢ the operand is in memory;
➢ the operand's address is a 16-/32-bit value in the instruction;
18: Immediate data
➢ the operand is in the instruction;
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