1. Application of Selective Epitaxial Growth in the
Sub 20 nm FinFET Device Fabrication
A.Hikavyy, E. Rosseel, G. Eneman, P. Favia, R. Loo
(imec)

2. Content
• Introduction
• Integration of high Ge content SiGe for pMOS transistors
• Integration of Si:C:P and Si:P for nMOS transistors
• Use of Si, SiGe and Si:C for merged Source/Drains

3. Introduction
• From 2012 we officially live in the era of fin field effect transistors (fin FETs)
with products on the market utilizing this technology at 22 nm node [Intel].
• Most of the major semiconductor players (Intel, TSMC, Samsung,
GlobalFoundries) announced transition from planar architectures to fin FETs
at 14-16 nm technology node.
• It is often considered that 10 nm or even smaller nodes will be based on
group IV semiconductors (Si, SiGe, Ge).

4. Introduction
• An important step in device manufacturing is strain incorporation in the
source/drain areas (S/D).
• Importance of embedded S/D in the case of Si finFETs still remains (limited
space availability).
• Raised S/D will probably be prevailing if a high mobility channel used due to
relaxation after the dry etch step.
• This consequently will lead to increased Ge concentration in both
raised/elevated SiGe S/D and possibly different way of strain incorporation
via strain relaxed buffers in order to improve FETs performance.

5. Integration of high Ge content SiGe for pMOS transistors
• SiGe S/D strain booster is used since
90 nm technology node.
• Every next node, Ge concentration in
the S/D areas of pMOS transistors
increased by roughly 10%.
• At present 22 nm node concentration
of Ge in SiGe S/D reached 50%.
• One can easily predict that in the next
two generations Ge concentration
might reach ~60 - 70%.K. J. Kuhn, et al. ECS Transactions, 33 (6) 3-17 (2010)
Chipworks reports.

6. Imec 500C
Imec 450C
HRXRD ~85 nm
HRXRD ~25 nm
65 nm
55 nm
Critical thickness for SiGe
55% is ~25 nm (450C growth)
S/D is grown well above
critical thickness!
Elastic relaxation due to
faceted growth in free space.
Plastic relaxation Elastic relaxation
Intel’s 22 nm pMOS
Integration of high Ge content SiGe for pMOS transistors
T
J. M. Hartmann, et al. J. Appl. Phys. 110, 083529 (2011).

7. Integration of high Ge content SiGe for pMOS transistors
STI STI
Si fin
Si recess SiGe regrowth
(111) facets
SiGe diamond
shaped S/D
STI STI
STI
Si fin
STI STI
SiGe regrowth
(111) facets
SiGe diamond
shaped S/D
Faceted growth in a free space allows to slightly elastically relax the strained structure.
Increase of Ge content is needed in order to maintain the same level of strain.
Raised S/D
Embedded
S/D

8. Si precursors : SiH4, SiH2Cl2, Si2H6, Si3H8, etc.
Ge precursor : GeH4,
Integration of high Ge content SiGe for pMOS transistors
Si25Ge75 grown on a planar
FET structure (SEM)
Si25Ge75 grown on a finFET
structure (HAADF-STEM)

9. Integration of high Ge content SiGe for pMOS transistors
• SiGe with Ge content ~ 50% is already in production. These layers are
already grown well above the critical thickness.
• Even higher Ge concentrations can be utilized from epi deposition
perspective.
• Different precursors can be used for deposition. Growth temperature should
be low (to avoid elastic relaxation), which will be reflected in the growth rate.
• SiGe with Ge~75% have been demonstrated on both planar and finFET
structures.

10. Integration of Si:C:P and Si:P for nMOS transistors
• Traditionally nMOS transistors easily outperformed pMOS due to higher
mobility of electrons in Si.
• Use of different stressor techniques (CESL and stacking faults) allowed to
boost performance even higher.
• Unfortunately these techniques are not applicable in the next technology
nodes due to space limitation.
• As an alternative use of Si:C:P or Si:P is often considered and has been
demonstrated previously.

11. • Si:C as a stressor material for nMOS transistors is
being investigated for almost a decade and was
demonstrated in devices.
• To our knowledge, the mainstream industry has not
embraced this technology yet.
• Several factors and their combination can explain
this situation:
 Incorporation of C in the Si lattice is not
straightforward - C tends to precipitate
and the highest concentration of
substitutional C reported is around 3%.
 Defective growth on (111) plane.
Integration of Si:C:P and Si:P for nMOS transistors
1E+01
1E+02
1E+03
1E+04
1E+05
1E+06
1E+07
-500 500 1500 2500 3500
XRDIntensity(cps)
 (arcsec)
Si:C:P, Csub = 1.2%
Si:C:P, Csub = 1.8%

12. Integration of Si:C:P and Si:P for nMOS transistors
K.D. Weeks et al, Thin Solid Films, Vol.520 (8), p 3158 (2012)
1E+01
1E+02
1E+03
1E+04
1E+05
1E+06
1E+07
-500 0 500 1000 1500 2000 2500
XRDIntensity(cps)
 (arcsec)
Si:P, [P]=0.8%
Si:P, [P]=1.2%
Si:P, [P] = 4%
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
[P]= 0.8% [P]=1.2% [P]=4%
(mOhm.cm)
After epi
After LA
(0,0) X
Y
(0,150)
(150,0)
(0,0) X
Y
(0,150)
(150,0)
vv
• Adding of high concentrations of P (few
percent) in Si changes Si lattice. Introduces
tensile strain comparable to C.
• Such a process can be selective in the CDE
mode.
• A care should be taken in order to keep
layers resistance low.
• Laser anneal allows to considerably lower
layer resistance.
E.Rosseel et al, to be presented at ECS Fall 2014

13. Integration of Si:C:P and Si:P for nMOS transistors
• Selective epitaxial growth of Si:C typically
involves cycling of precursors in order to
gain selectivity.
• Si:C is grown defect free until the (111) plane
is formed, further growth is highly defective,
contrary to the Si or SiGe case.
• This behavior was also confirmed by growing
Si:C on Si wafers with different surface
orientation.
• At present it is difficult to conclude if
problems with Si:C and Si:P are fundamental
or are related to particular processes.
J. Tolle, et al, ECS Transactions, 50 (9), p.491 (2013)

14. • Si:C:P and Si:P still are considered as a promising material for boosting
nMOS transistors.
• For both materials its resistance should be under control. Laser annealing
helps to reduce resistance in the case of Si:P.
• Growth of Si:C:P on (111) plane is defective. Not enough data for Si:P.
• At present it is not clear if such growth is fundamental or process related.
• More fundamental studies on growth of Si:C:P on (111) Si is needed.
Integration of Si:C:P and Si:P for nMOS transistors

15. Use of Si, SiGe, Si:C for merged Sourse/Drains
• Source/drain areas diminish considerably in the advanced nodes.
• Amount of stressor material applicable in a fin FET structure depends on
the fin size and separation between fins.
• The maximal stress will be obtained when individual diamonds grown
around fins will just touch.
• In an extreme case full merging of individual fins can be considered.
• Although fins merging was heavily investigated and patented by IBM no
data on the epitaxial growth is available.

16. Imec simulation data for 14 nm node.
S/D epi with 10nm S/D separation: about 15% less effective
than “imperfect” merged fins
Use of Si, SiGe, Si:C for merged Sourse/Drains

17. Use of Si, SiGe, Si:C for merged Sourse/Drains
S/D pads – (100) surface – the highest GR
for typically used materials (Si, SiGe)
GR(100) > GR(110)~GR(111)
J.Tolle et al,
ECS Transactions, 50 (9) 491-497 (2012)
Si SiGe Si:С
Si S/D
(100)
(110)

18. Use of Si, SiGe, Si:C for merged Sourse/Drains
Si45Ge55 Si55Ge45 Si Si25Ge75 Si:P
Si
Si Si
Si
rGe
rGe
• Rhombic shape of raised S/D is an eventual shape when enough growth time
is given. Effect of Si fin orientation, presence of (110) sidewall and formation
of (111) facets.
• The same shape is observed for all investigated materials : Si, SiGe, Ge, Si:P
and Si:C.
• Until merging epi growth is governed by (111) facets (typically slow GR).

19. Wide fins Narrow fins
Fast growth on the top of
the fin till the (111) facet is
created.
Quite some growth on the
side wall before (111) facets
are created.
(111) facets are created
almost from the start of
the growth, no vertical
growth
=> Very slow GR on
isolated scaled fins.
Low GR till the fins start to
merge (111) facets
Increase of GR when fins are
merged due to (100) surface
reappearance
High GR (100) surface

20. Different spacing between fins and difference in fins geometry results in uneven epi growth
A 23.4 nm => fully merged (100) surface
B 25.5 nm => almost merged
C 27.5 nm=> just merged , strong influence of (111) facets.
The final layer after merging: surface is not smooth, voids between fins, defects.
A BC
void
defects
Use of Si, SiGe, Si:C for merged Sourse/Drains
Si SEG

21. 1 1 12 2 2
Periodic difference in Si75Ge25 growth is probably related
to fins and STI dimension periodicity caused by double
patterning.
Merging of fins results in a pyramid (no [100] surface).
Defectivity of the merged SiGe is limited (limited
relaxation).
Use of Si, SiGe, Si:C for merged Sourse/Drains SiGe SEG

22. J.Tolle et al, ECS Transactions,
50 (9) 491-497 (2012)
(100)
(110)
GR and C% vary depending on the growth orientation.
Although Si and SiGe can be grown with a relatively decent quality on all
three surfaces, situation with Si:C seems to be different.
Si:C grows very defectively once (111) facet is developed .
Si:C SEG
Use of Si, SiGe, Si:C for merged Sourse/Drains

23. • For advanced nodes merging is often considered and might be needed
in order to obtain the necessary performance.
• Rhombic shape of epi growth on fins is independent of material and is
governed by fins geometry and orientation.
• In order to obtain even merging between fins both: fins dimensions and
spacing between fins must be tightly controlled.
• If in the case of Si and SiGe relatively good epi growth is observed (with
some defects), for Si:C highly defective growth is seen after (111) facet
development.
Use of Si, SiGe, Si:C for merged Sourse/Drains

24. Acknowledgments
• The imec core CMOS program members
• European commission and local authorities
• Imec pilot line
• ASM for continuous fruitful collaboration on epitaxial growth