Micro-processor Laboratory Experiment

1. Department of Electrical and Electronic
Engineering
Khulna University of Engineering & Technology
Khulna-9203
Course code : EE 3214
Sessional on
Microprocessors, Micro-controllers and Peripherals
Presented By
Amit Kumer Podder
Experiment No. 08

2. (a) Introduction to 8254 (8253) programmable
interval timer (b) Design and implementation of
traffic controller using 8255 PPI and 8253
programmable interval timer in 8086
microprocessor environment
Experiment Name
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3. Not Possible
To Generate
Accurate
Time Delays
Using Delay
Routines in
8086
Intel’s Programmable Counter/
Timer Device (8253/8254)
Facilitates
• Accurate Time Delays
• Minimizes Load On Mp
• Real Time Clock
• Event Counter
• Digital One Shot
• Square Wave Generator
• Complex Waveform Generator
Why 8253/8254
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4. 8253 can operate
at frequency from
dc to 2mhz
8254-ADVANCED VERSION OF 8253
• 8254 can operate with higher clock Frequency
Range ( DC To 8 Mhz AND 10 Mhz FOR 8254-2)
• Includes Status Read Back Command That Latches
The Count And Status Of Counters
8253 Vs 8254
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5. Pin diagram of 8253
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6. Pin diagram of 8253
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7. Counters:
 Three Counters – C1,C2 & C3
 Each 16 Bit Identical Presettable
 Down Counter Operates In BCD /Hex
 Controlled By Loading Count To Command Word Register
 “On The Fly” Reading
Control Logic:
 CS – Logic 0 – Enables 8254
 RD – Logic 0 – Tells Microprocessor Reads Count From 8254
 WR – Logic 0 – Tells Microprocessor Writes Count/ Command Into 8254
 A1,a0 – Address Input Pins To Select Modes And Counters
Pin description of 8253
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8. Data Buffers:
 8 Bit Bidirectional D0-d7 Connected To Data Bus Of Microprocessor
 In  Reads Data From Peripheral
 Out  Writes Data To Peripheral
Control Word Register:
 Accepts 8 Bit Control Word Written By Microprocessor
 Can Only Be Written ( Not Read)
 Control Word Chooses One Of The Six Modes Of Operation
Pin description of 8253
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9. Control word format of 8253
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10. MDA Win 8086 Trainer Kit Port Address
For 8254 For 8255
Port
Address
Port Name
09H Counter 0
0BH Counter 1
0DH Counter 2
0FH Control register
Port Address Port Name
19H Port A
1BH Port B
1DH Port C
1FH Control register
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11. G3 Y3 R3
G4 Y4 R4G2 Y2 R2
G1 Y1 R1Road 1
Road 3 Road 4
Road 2
Traffic Signal Flow Diagram
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12. PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
0 0 G2 Y2 R2 G1 Y1 R1 0 0 G4 Y4 R4 G3 Y3 R3
R1 R2 G3 G4 0 0 0 0 1 0 0 1
= 09H
0 0 1 0 0 1 0 0
=24H
Y1 Y2 Y3 Y4 0 0 0 1 0 0 1 0
= 12H
0 0 0 1 0 0 1 0
= 12H
R3 R4 G1 G2 0 0 1 0 0 1 0 0
= 24H
0 0 0 0 1 0 0 1
= 09H
Y1 Y2 Y3 Y4 0 0 0 0 1 0 1 0
= 12H
0 0 0 1 0 0 1 0
= 12H
Traffic signal generating coding table
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13. For Latching
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
For Load Operation
Control word for 8255
0 1 1 1 0 0 0 0
0 1 0 0 0 0 0 0
1 0 0 0 0 0 0 0
Control Word
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