1. Alexis, Ian, Matt, Spencer
Digital Electronics Lab 2 notes and measurements:
II. components and instrumentation:
important to note that the given schematic of the IC was not the same IC that was used in this
lab; therefore the schematic in reference was taken from the Digital electronics lab manual
located in the robotics lab. 74LS00 IC with pins 14 being the 5V and 7 grounded.
E1.1 The NAND logic function:
using our DVM with negative lead grounded, verified the supply to by 5.0V (approx 4.9V) then
measured voltages at each pin in triples (i.e: 1,2,3;4,5,6;7,8,9). ideally we should get inputs to
measure close to zero volts, and outputs to measure from 3-5V. due to the configuration of high
to low, low to high outputs.
our chip test results:
(all were tested to ground; “P” stands for pin and “G” stands for ground)
P1 to G=0
P2 to G=0
P3 to G=4.87
P4 to G= 0.005 ~ 0
P5 to G=0
P6 to G=4.87
lab then asked after testing a few pins, test pins together (i.e P1+P2 to P3)
this is where our chip was displaying irregular results yet still recorded for testing purposes.
P4+P5 to P6=3.45 * drop in V
P1+P2 to P3=1.5* drop in V
P12+P13 to P11=2.78* drop
P10+P9 to P8=4.7 ***which ideally should have been a drop
single input to output tests
P12 to P11=4.38
P13 to P11=4.3
P6 to P4= 4.44
P6 to P5=4.45
P10 to P8=4.66
P9 to P8=4.87
P1 to P3=4.43
P2 to P3=1.5*** did not match with truth table logic (another red flag)
these results did not match our truth table in which H(high) and L(low) represents logic levels
and where an input is high when left open. One final test to check the voltage across the chip

2. with our power supply at 5V and an oscilloscope showed the chip was faulty. Switching out our
chip we re tested the NAND gate logic, did in fact match truth table (see spencer’s OneNote
document- 8 inputs 4 outputs)
E1.2 operating speed - propagation delay
connected ring of three NAND gates joined together to the preceding gate:
our ring of NAND gates was: (G standing for gate)
G5+G6 connected to G3 then G1+G2 connected to G13 then G11+G12 connected to G8
(pictures of 3 gates, 5 and 7 gates with second IC are attached to email)
with probes at A and B measure the 2 propagation delays which characterize the intervening
gate:
f=36 MHz
T= 1/f=1/(36*10^6) ~ 0.05*10^-6
50*10^-9 =50 nanoseconds/3 gates ~ 1 gate approx. 17 nanoseconds.
connecting any even number of gates will result in a 0V.
part f refer to photos of the freq of 3 5 and 7 gates connected. freq increases with added gates.
E1.3 Switching threshold, transfer Characteristics and input Characteristics: (last part)
assemble circuit
with DVM connected between nodes A and C measure voltages. then while measuring move
node A to 0V momentarily then back up to 5V while C stays grounded. record measurements.
measured @ 0V ~0.0011 V starting
node A at 0V=1.1V then at 5V=3.9V
lastly, while measuring the voltage at node C, adjust Vs for a few interesting values ranging
from high to low record observations: little to no change occurred in DVM measurements.