parallel self timed adder using recursive approach vlsi

1. 1
CHAPTER 1
INTRODUCTION TO VLSI DOMAIN
1.1 VLSI Design
The complexity of VLSI is being designed and used today makes the manual
approach to design impractical. Design automation is the order of the day. With the rapid
technological developments in the last two decades, the status of VLSI technology is
characterized by the following.
A steady increase in the size and hence the functionality of the ICs:
• A steady reduction in feature size and hence increase in the speed of operation as well as
gate or transistor density.
• A steady improvement in the predictability of circuit behavior.
• A steady increase in the variety and size of software tools for VLSI design.
The above developments have resulted in a proliferation of approaches to VLSI design.
1.2 History of VLSI
VLSI began in the 1970s when complex semiconductor and communication
technologies were being developed. The microprocessor is a VLSI device. The term is no
longer as common as it once was, as chips have increased in complexity into the hundreds
of millions of transistors.
This is the field which involves packing more and more logic devices into smaller
and smaller areas. VLSI circuits can now be put into a small space few millimeters across.
VLSI circuits are everywhere. Our computer, our car, our brand new state-of-the-art digital
camera, the cell-phones, and what we have.
1.3 Various integrations
Over time, millions, and today billions of transistors could be placed on one chip,
and to make a good design became a task to be planned thoroughly.
In the early days of integrated circuits, only a few transistors could be placed on a
chip as the scale used was large because of the contemporary technology, and
manufacturing yields were low by today's standards. As the degree of integration was small,

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the design was done easily. Over time, millions, and today billions of transistors could be
placed on one chip, and to make a good design became a task to be planned thoroughly.
1.3.1 SSI technology
The first integrated circuits contained only a few transistors called "small-scale
integration" (SSI), digital circuits containing transistors numbering in the tens provided a
few logic gates for example, while early linear ICs such as the Plessey SL201 or the Philips
TAA320 had as few as two transistors. The term Large Scale Integration was first used by
IBM scientist Rolf Landauer when describing the theoretical concept from there came the
terms for SSI, MSI, VLSI, and ULSI.
1.3.2 MSI technology
The next step in the development of integrated circuits, taken in the late 1960s,
introduced devices which contained hundreds of transistors on each chip, called "medium-
scale integration" (MSI).
They were attractive economically because while they cost little more to produce
than SSI devices, they allowed more complex systems to be produced using smaller circuit
boards, less assembly work (because of fewer separate components), and a number of other
advantages.
1.3.3 LSI technology
Further development, driven by the same economic factors, led to "Large Scale
Integration" (LSI) in the mid 1970s, with tens of thousands of transistors per chip.
Integrated circuits such as 1K-bit RAMs, calculator chips, and the first microprocessors,
that began to be manufactured in moderate quantities in the early 1970s, had under 4000
transistors. True LSI circuits, approaching 10,000 transistors, began to be produced around
1974, for computer main memories and second-generation microprocessors.
1.3.4 VLSI technology
Final step in the development process, starting in the 1980s and continuing through
the present, was in the early 1980s, and continues beyond several billion transistors as of
2009.In 1986 the first one megabit RAM chips were introduced, which contained more than
one million transistors. Microprocessor chips passed the million transistor mark in 1989 and
the billion transistor mark in 2005.The trend continues largely unabated, with chips
introduced in 2007 containing tens of billions of memory transistors.

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1.4 VLSI Design Flow
Fig 1.1 VLSI design flow
Start
DesignEntity
Pre layoutSimulation
Logic Synthesis
SystemPartitioning
Pre layoutSimulationFloor Planning
Placement
CircuitExtractionRoutingFinish

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CHAPTER 2
LITERATURE SURVEY
2.1 Brief study about adders
With the advancements in VLSI technology, the circuit designs are getting miniature
in size, consuming lesser power for performing their intended operation and becoming
faster in operation. We all know that area, power and speed are the major constraints in
VLSI design, and the designers are taking enormous efforts to improve their designs
relative to these constraints, but all of these cannot be improved simultaneously.
In this modern era of technological advancements, everything is becoming fast-
paced and heading towards completely digital processes. Hence, there is an immense
need of developing faster processors which would operate on digital signals, but as we
head towards improving any one of the design parameter, the other parameters are also
affected, and so with the improvement in speed of operation of any circuit, its area
occupancy also increases.
In circuits like digital signal processor (DSP), microprocessor, or arithmetic and logic
unit (ALU) of any processor, the unit performing arithmetic operations is very important
when considered with respect to the design constraints mentioned above. Most arithmetic
circuits consist of adder, subtractor, multiplier, divider, etc.; the adder unit being the most
basic unit among all the other units.
In this paper, we are comparing various adders in terms of their delay and area, as the
adder is used in the construction of other arithmetic circuits and the performance of the
adder is decisive of the performance of other circuits employing the use of adders.
2.1.1 Single-bit Adders
2.1.1.1 Half adder
Half adder is a combinational arithmetic circuit that adds two numbers and produces a
sum bit (S) and carry bit (C) as the output. If A and B are the input bits, then sum bit (S)
is the X-OR of A and B and the carry bit (C) will be the AND of A and B. From this it is
clear that a half adder circuit can be easily constructed using one X-OR gate and one
AND gate. Half adder is the simplest of all adder circuit, but it has a major disadvantage.

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The half adder can add only two input bits (A and B) and has nothing to do with the carry
if there is any in the input. So if the input to a half adder have a carry, then it will be
neglected it and adds only the A and B bits. That means the binary addition process is not
complete and that’s why it is called a half adder. The truth table, schematic representation
and XOR,AND realization of a half adder are shown in the figure below.
Table 2.1 Truth table Fig. 2.1 Schematic and realization of half adder
NAND gates or NOR gates can be used for realizing the half adder in universal logic and
the relevant circuit diagrams are shown in the figure below.
Fig. 2.2 Half adder using NAND & NOR logic
2.1.1.2 Full Adder
The full adder is a little more difficult to implement than a half adder. The main
difference between a half adder and a full adder is that the full adder has three inputs and
two outputs. The two inputs are A and B, and the third input is a carry input CIN. The
output carry is designated as COUT, and the normal output is designated as S.

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Table 2.2 Truth table of Full Adder
The output S is an EX – OR between the input A and the half adder SUM output
B. The COUT will be true only if any of the two inputs out of the three are HIGH or at
logic1.
Thus, a full adder circuit can be implemented with the help of two half adder
circuits. The first half adder circuit will be used to add A and B to produce a partial sum.
The second half adder logic can be used to add CIN to the sum produced by the first half
adder circuit. Finally, the output S is obtained.
If any of the half adder logic produces a carry, there will be an output carry. Thus,
COUT will be an OR function of the half adder CARRY outputs.
.Fig. 2.3 Full Adder

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Figure 2.4 Schematic representation of a single bit Full Adder
With the help of this type of symbol, one can add two bits together, taking a carry from
the next lower order of magnitude and sending a carry to the next higher order of
magnitude.
NAND gates or NOR gates can be used for realizing the full adder in universal logic and
the relevant circuit diagrams are shown in the figure below.
Figure 2.5 Full Adder using NAND Logic

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Figure 2.6 Full adder using NOR logic
2.1.2 Multi-bit Adders
The half-adder and the full-adder are the simplest addition elements which are limited
to single-bit addition. For performing multi-bit addition, we need to cascade multiple full-
adder (FA) units.
The design of various adders such as Ripple Carry Adder (RCA), Carry Skip Adder
(CSkA), Carry Increment Adder (CIA), Carry Look Ahead Adder (CLA), Carry Save
Adder (CSA), Carry Select Adder (CSlA) and Carry Bypass Adder (CBA) are discussed
below. The each and every adder is named based on the propagation of carry between the
stages.
2.2.1 Ripple Carry Adder
Arithmetic operations like addition, subtraction, multiplication, division are basic
operations to be implemented in digital computers using basic gates like AND, OR, NOR,
NAND etc. Among all the arithmetic operations if we can implement addition then it is easy
to perform multiplication (by repeated addition), subtraction (by negating one operand) or
division (repeated subtraction). Half Adders can be used to add two one bit binary numbers
and Full adders to add two three bit numbers. The block diagram of 4-bit Ripple Carry Adder
is shown here below in Figure 2.1. It is possible to create a logical circuit using multiple full
adders to add N-bit numbers. Each full adder inputs a Cin, which is the Cout of the previous
adder. This kind of adder is called a ripple-carry adder, since each carry bit "ripples" to the
next full adder. Note that the first (and only the first) full adder may be replaced by a half
adder (under the assumption that Cin = 0). The block diagram of 4-bit Ripple Carry Adder is
shown here below –

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Fig 2.7 A 4 bit Ripple Carry Adder
The layout of a ripple-carry adder is simple, which allows for fast design time;
however, the ripple carry adder is relatively slow when number of stages get increased,
since each full adder must wait for the carry bit to be calculated from the previous full
adder. The gate delay can easily be calculated by inspection of the full adder circuit. Each
full adder requires three levels of logic. In a 32-bit ripple-carry adder, there are 32 full
adders, so the critical path (worst case) delay is 3 (from input to carry in first adder) + 31
* 2 (for carry propagation in later adders) = 65 gate delays.
The disadvantage of the ripple-carry adder is that it can get very slow when one needs to add
many bits.
2.2.2 Carry Look Ahead Adder
A carry-look ahead adder (CLA) is a type of adder used in digital logic. A carry-look
ahead adder improves speed by reducing the amount of time required to determine carry
bits. It can be contrasted with the simpler, but usually slower ripple carry adder for which
the carry bit is calculated alongside the sum bit, and each bit must wait until the previous
carry has been calculated to begin calculating its own result and carry bits (see adder for
detail on ripple carry adders). The carry-look ahead adder calculates one or more carry
bits before the sum, which reduces the wait time to calculate the result of the larger value
bits. The kogge- stone adder and brent- kung adder are examples of adder.

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Fig 2.8 A 4 bit Carry Look Ahead Adder
Carry look ahead logic uses the concepts of generating and propagating carries.
Although in the context of a carry look ahead adder, it is most natural to think of
generating and propagating in the context of binary addition, the concepts can be used
more generally than this. In the descriptions below, the word digit can be replaced
by bit when referring to binary addition of 2.
The addition of two 1-digit inputs A and B is said to generate if the addition will
always carry, regardless of whether there is an input carry (equivalently, regardless of
whether any less significant digits in the sum carry). For example, in the decimal addition
52 + 67, the addition of the tens digits 5 and 6 generates because the result carries to the
hundreds digit regardless of whether the ones digit carries (in the example, the ones digit
does not carry (2+7=9)).
In the case of binary addition, A + B generates if and only if both A and B are 1. If
we write G(A, B) to represent the binary predicate that is true if and only if A+B
generates, we have:
G(A,B) = A+B
The addition of two 1-digit inputs A and B is said to propagate if the addition will
carry whenever there is an input carry (equivalently, when the next less significant digit
in the sum carries). For example, in the decimal addition 37 + 62, the addition of the tens
digits 3 and 6 propagate because the result would carry to the hundreds digit if the ones
were to carry (which in this example, it does not). Note that propagate and generate are

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defined with respect to a single digit of addition and do not depend on any other digits in
the sum.
In the case of binary addition, A +B propagates if and only if at least one
of A or B is 1. If we write P(A, B) to represent the binary predicate that is true if and only
if A+B propagates, we have
P(A,B) = A+B
Sometimes a slightly different definition of propagate is used. By this definition A
+ B is said to propagate if the addition will carry whenever there is an input carry, but
will not carry if there is no input carry. Fortunately, due to the way generate and
propagate bits are used by the carry look ahead logic, it doesn't matter which definition is
used. In the case of binary addition, this definition is expressed by:
Pi= Ai⊕Bi
For binary arithmetic, or is faster than xor and takes fewer transistors to
implement. However, for a multiple-level carry look ahead adder, it is simpler to use
P’(A,B).
Given these concepts of generate and propagate, when will a digit of addition
carry? It will carry precisely when either the addition generates or the next less significant
bit carries and the addition propagates. Written in Boolean algebra, with Ci the carry bit
of digit i, and Pi and Gi the propagate and generate bits of digit i respectively,
Ci+1 = Gi + (Pi·Ci).
Implementation details
For each bit in a binary sequence to be added, the Carry Look Ahead Logic will
determine whether that bit pair will generate a carry or propagate a carry. This allows the
circuit to "pre-process" the two numbers being added to determine the carry ahead of
time. Then, when the actual addition is performed, there is no delay from waiting for the
ripple carry effect (or time it takes for the carry from the first Full Adder to be passed
down to the last Full Adder). Below is a simple 4-bit generalized Carry Look Ahead
circuit that combines with the 4-bit Ripple Carry Adder we used above with some slight
adjustments:
For the example provided, the logic for the generate (g) and propagate (p) values
are given below. Note that the numeric value determines the signal from the circuit above,
starting from 0 on the far left to 3 on the far right:
C1 = G0 +P0·C0

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C 2= G1 + P1·C1
C3 = G2 + P2·C2
C4= G3 + P3·C3
Substituting C1 into C2, then C2 into C3, then C3 into C4 yields the expanded
equations:
C1 = G0 +P0·C0
C 2= G1 + G0·P1 + C0·P0·P1
C3 = G2+ G1·P2 + G0·P1·P2 + C0·P0·P1·P2
C4 = G3 + G2·P3 + G1·P2·P3 + G0·P1·P2·P3 + C0·P0·P1·P2·P3
To determine whether a bit pair will generate a carry, the following logic works:
Gi = Ai · Bi
To determine whether a bit pair will propagate a carry, either of the following logic
statements work:
Pi= Ai ⊕Bi
The reason why this works is based on evaluation of C1 = G0 +P0·C0. The
only difference in the truth tables between (Pi= A⊕B) and (A+B) is when
both A and B are 1. However, if both A and B are 1, then the G0 term is 1 (since its
equation is A·B) and the P0· C0 term becomes irrelevant. The XOR is used normally
within a basic full adder circuit; the OR is an alternate option (for a carry look ahead
only) which is far simpler in transistor-count terms.
The Carry Look Ahead 4-bit adder can also be used in a higher-level circuit
by having each CLA Logic circuit produce a propagate and generate signal to a higher-
level CLA Logic circuit. The group propagate (PG) and group generate (GG) for a 4-bit
CLA are:
PG = P0·P1·P2·P3
GG = G3 + G2·P3 + G1·P2·P3 + G0·P1·P2·P3
Putting 4 4-bit CLAs together yields four group propagates and four group
generates. A Look ahead Carry Unit (LCU) takes these 8 values and uses identical logic
to calculate Ciin the CLAs. The LCU then generates the carry input for each of the 4
CLAs and a fifth equal to C16.
The calculation of the gate delay of a 16-bit adder (using 4 CLAs and 1 LCU) is not as
straight forward as the ripple carry adder. Starting at time of zero:
 calculation of Pi and Gi is done at time 1

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 calculation of Ci is done at time 3
 calculation of the PG is done at time 2
 calculation of the GG is done at time 3
 calculation of the inputs for the CLAs from the LCU are done at
 time 0 for the first CLA
 time 5 for the second, third & fourth CLA
 calculation of the are done at
 time 4 for the first CLA
 time 8 for the second, third & fourth CLA
 calculation of the final carry bit (C16) is done at time 5
 The maximum time is 8 gate delays (for S8-15). A standard 16-bit ripple carry
adder would take 31 gate delays.
2.3 Multiplexer
A Multiplexer is a device that allows one of several analog or digital input signals
which are to be selected and transmits the input that is selected into a single medium.
Multiplexer is also known as Data Selector. A multiplexer of 2n inputs has n select lines
that will be used to select input line to send to the output. Multiplexer is abbreviated as
Mux. MUX sends digital or analog signals at higher speed on a single line in one shared
device. It recovers the separate signals at the receiving end. The Multiplexer boosts or
amplifies the information that later transferred over network within a particular
bandwidth and time.

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Fig 2.9 A n:1 Mux
A two–to–one multiplexer is a combinational circuit that uses one control switch (S)
to connect one of two input data lines (A or B) to a single output (Z). Only one of the
input data lines can be aligned to the output of the multiplexer at any given time.
Fig 2.10 A Schematic diagram Table 2.3 A 2x1 mux truth table

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Fig 2.11 Realization of 2:1 MUX

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CHAPTER 3
PROPOSED PROJECT
3.1 Introduction
Binary addition is the single most important operation that a processor performs. Most
of the adders have been designed for synchronous circuits even though there is a strong
interest in clockless/asynchronous processors/circuits. Asynchronous circuits do not
assume any quantization of time. Therefore, they hold great potential for logic design as
they are free from several problems of clocked(synchronous) circuits. In principle, logic
flow in asynchronous circuits is controlled by a request-acknowledgment hand shaking
protocol to establish a pipeline in the absence of clocks. Explicit handshaking blocks for
small elements, such as bit adders, are expensive. Therefore, it is implicitly and
efficiently managed using dual-rail carry propagation in adders. A valid dual-rail carry
output also provides acknowledgment from a single-bit adder block. Thus, asynchronous
adders are either based on full dual-rail encoding of all signals (more formally using null
convention logic that uses symbolically correct logic instead of Boolean logic) or
pipelined operation using single-rail data encoding and dual-rail carry representation for
acknowledgments. While these constructs add robustness to circuit designs, they also
introduce significant overhead to the average case performance benefits of asynchronous
adders. Therefore, a more efficient alternative approach is worthy of consideration that
can address these problems.
This brief presents an asynchronous parallel self-timed adder(PASTA) using the
algorithm originally proposed. The design of PASTA is regular and uses half-adders
(HAs) along with multiplexers requiring minimal interconnections. Thus, it is suitable for
VLSI implementation. The design works in a parallel manner for independent carry chain
blocks. The implementation in this brief is unique as it employs feedback through XOR
logic gates to constitute a single-rail cyclic asynchronous sequential adder. Cyclic circuits
can be more resource efficient than their acyclic counterparts.
On the other hand, wave pipelining (or maximal rate pipelining) is a technique
that can apply pipelined inputs before the outputs are stabilized. The proposed circuit
manages automatic single-rail pipelining of the carry inputs separated by propagation and
inertial delays of the gates in the circuit path.

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Thus, it is effectively a single-rail wave-pipelined approach and quite different from
conventional pipelined adders using dual-rail encoding to implicitly represent the
pipelining of carry signals.
3.2 Background
There are a myriad designs of binary adders and we focus hereon asynchronous self-
timed adders. Self-timed refers to logic circuits that depend on and/or engineer timing
assumptions for the correct operation. Self-timed adders have the potential to run faster
averaged for dynamic data, as early completion sensing can avoid the need for the worst
case bundled delay mechanism of synchronous circuits. They can be further classified as
follows.
3.3 Design of PASTA
In this section, the architecture and theory behind PASTA is presented. The adder first
accepts two input operands to perform half additions for each bit. Subsequently, it iterates
using earlier generated carry and sums to perform half-additions repeatedly until all carry
bits are consumed and settled at zero level.
Fig 3.1. GENERAL BLOCK DIAGRAM OF PASTA
Fig. 3.2. State diagrams for pasta. (a) initial phase. (b) iterative phase

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3.3.1 Architecture of PASTA
The general architecture of the adder is shown in Fig. 1.8Theselection input for
two-input multiplexers corresponds to the Req handshake signal and will be a single 0 to
1 transition denoted by SEL. It will initially select the actual operands during SEL = 0
and will switch to feedback/carry paths for subsequent iterations using SEL = 1. The
feedback path from the HAs enables the multiple iterations to continue until the
completion when all carry signals will assume zero values.
3.3.2 State Diagrams
In Fig.3.2 two state diagrams are drawn for the initial phase and the iterative phase
of the proposed architecture. Each state is represented by (Ci+1 Si) pair where Ci+1, Si
represents carry out and sum values, respectively, from the ith bit adder block. During the
initial phase, the circuit merely works as a combinational HA operating in fundamental
mode. It is apparent that due to the use of HAs instead of FAs, state (11) cannot appear.
During the iterative phase (SEL = 1), the feedback path through multiplexer block is
activated. The carry transitions (Ci) are allowed as many times as needed to complete the
recursion.
From the definition of fundamental mode circuits, the present design cannot be
considered as a fundamental mode circuit as the input–outputs will go through several
transitions before producing the final output. It is not a Muller circuit working outside the
fundamental mode either as internally, several transitions will take place, as shown in the
state diagram. This is analogous to cyclic sequential circuits where gate delays are
utilized to separate individual states.
3.3.3 Recursive Formula for Binary Addition
Let𝑆𝑖
𝑗
and𝐶𝑖+1
𝑗
denote the sum and carry, respectively, for ith bit at the jth iteration.
The initial condition (j = 0) for addition is formulated as follows:
The j th iteration for the recursive addition is formulated by

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The recursion is terminated at kth iteration when the following condition is met:
Now, the correctness of the recursive formulation is inductively proved as
follows.
Theorem 1: The recursive formulation of (1)–(4) will produce correct sum for any
number of bits and will terminate within a finite time.
Proof: We prove the correctness of the algorithm by induction on the required number of
iterations for completing the addition (meeting the terminating condition).
Basis: Consider the operand choices for which no carry propagation is required, i.e
𝐶0
𝑖
= 0 for ∀i,
i∈ [0..n]. The proposed formulation will produce the correct result by a single-bit
computation time and terminate instantly as (4) is met.
Induction: Assume that 𝐶𝑖+1
𝑘
≠0for some ith bit at kth iteration.
Let l be such a bit for which 𝐶𝑖+1
𝑘
= 1. We show that it will be successfully transmitted to
next higher bit in the (k + 1)th iteration.
As shown in the state diagram, the kth iteration of lth bit state(𝐶𝑖+1
𝑘
,𝑆𝑙
𝑘
) and (l + 1)th
bit state (𝐶𝑖+2
𝑘
,𝑆𝑙+1
𝑘
) could be in any of (0, 0), (0, 1), or (1, 0) states. As𝐶𝑖+1
𝑘
= 1, it implies
that𝑆𝑙
𝑘
= 0. Hence, from (3), 𝐶𝑖+1
𝑘+1
= 0 for any input condition between0 to l bits.
We now consider the (l + 1)th bit state (𝐶𝑖+2
𝑘
,𝑆𝑙+1
𝑘
)for kth iteration. It could also be
in any of (0, 0), (0, 1), or (1, 0) states. In (k+1)th iteration, the (0, 0) and (1, 0) states from
the kth iteration will correctly produce output of (0, 1) following (2) and (3). For (0, 1)
state, the carry successfully propagates through this bit level following (3).
Thus, all the single-bit adders will successfully kill or propagate the carries until
all carries are zero fulfilling the terminating condition.

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The mathematical form presented above is valid under the condition that the
iterations progress synchronously for all bit levels and the required input and outputs
for a specific iteration will also be in synchrony with the progress of one iteration. In
the next section, we present an implementation of the proposed architecture which is
subsequently verified using simulations.

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CHAPTER 4
SIMULATION AND RESULTS
Fig. 4.1 Simulation result of recursive adder
Fig 4.2 Synthesis report for recursive adder

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4.3 Figure RTL SCHEMATIC

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CHAPTER 5
SIMULATION TOOL – XILINX
5.1 Xilinx ISE overview
The Integrated Software Environment (ISE) is the Xilinx design software suite
that allows you to take your design from design entry through Xilinx device
programming.
The ISE Project Navigator manages and processes your design through the
following steps in the ISE design flow.
5.1.1 Design Entry
Design entry is the first step in the ISE design flow. During design entry, you
create your source files based on your design objectives. You can create your top-level
design file using a Hardware Description Language (HDL), such as VHDL, Verilog, or
ABEL, or using a schematic. You can use multiple formats for the lower-level source
files in your design.
5.1.2 Synthesis
After design entry and optional simulation, you run synthesis. During this step,
VHDL, Verilog, or mixed language designs become net list files that are accepted as
input to the implementation step.
5.1.3 Verification
You can verify the functionality of your design at several points in the design
flow. You can use simulator software to verify the functionality and timing of your design
or a portion of your design. The simulator interprets VHDL or Verilog code into circuit
functionality and displays logical results of the described HDL to determine correct
circuit operation. Simulation allows you to create and verify complex functions in a
relatively small amount of time. You can also run in-circuit verification after
programming your device.
5.1.4 Device configuration
After generating a programming file, you configure your device. During
configuration, you generate configuration files and download the programming files from
a host computer to a Xilinx device.

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5.2 Project navigator overview
Project Navigator organizes your design files and runs processes to move the design
from design entry through implementation to programming the targeted Xilinx® device.
Project Navigator is the high-level manager for your Xilinx FPGA and CPLD designs,
which allows you to do the following:
 Add and create design source files, which appear in the Sources window
 Modify your source files in the Workspace
 Run processes on your source files in the Processes window
 View output from the processes in the Transcript window
5.2.1 Project navigator main window
The following figure shows the Project Navigator main window, which allows you to
manage your design starting with design entry through device configuration.
Fig 5.1 Project navigator

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1. Toolbar
2. Sources window
3. Processes window
4. Workspace
5. Transcript window
5.2.2 Using the sources window
The first step in implementing your design for a Xilinx® FPGA or CPLD is to
assemble the design source files into a project. The Sources tab in the Sources window
shows the source files you create and add to your project, as shown in the following
figure. For information on creating projects and source files, see Creating a Project and
Creating a Source File.
Fig 5.2 Sources window
The Design View ("Sources for") drop-down list at the top of the Sources tab
allows you to view only those source files associated with the selected Design View (for
example, Synthesis/Implementation). For details, see u. The "Number of" drop-down list,
Resources column, and Preserve column are available for designs that use Partitions. For
details, see Using Partitions.
The Sources tab shows the hierarchy of your design. You can collapse and expand
the levels by clicking the plus (+) or minus (-) icons. Each source file appears next to an
icon that shows its file type. The file you select determines the processes available in the
Processes window. You can double-click a source file to open it for editing in the
Workspace. For information on the different file types, see Source File Types.

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You can change the project properties, such as the device family to target, the top-
level module type, the synthesis tool, the simulator, and the generated simulation
language. For information, see Changing Project, Source, and Snapshot Properties.
Depending on the source file and tool you are working with, additional tabs are
available in the Sources window:
 Always available: Sources tab, Snapshots tab, Libraries tab
 Constraints Editor: Timing Constraints tab
 Floor plan Editor: Translated Netlist tab, Implemented Objects tab
 iMPACT: Configuration Modes tab
 Schematic Editor: Symbols tab
 RTL and Technology Viewers: Design tab
 Timing Analyzer: Timing tab
5.2.3 Using the Process Window
The Processes tab in the Processes window allows you to run actions or
"processes" on the source file you select in the Sources tab of the Sources window. The
processes change according to the source file you select.
The Process tab shows the available processes in a hierarchical view. You can
collapse and expand the levels by clicking the plus (+) or minus (-) icons. Processes are
arranged in the order of a typical design flow: project creation, design entry, constraints
management, synthesis, implementation, and programming file creation.
Depending on the source file and tool you are working with, additional tabs are available
in the Processes window:
 Always available: Processes tab
 Floor plan Editor: Design Objects tab, Implemented - Selection tab
 IMPACT: Configuration Operations tab
 ISE Simulator: Hierarchy Browser tab
 Schematic Editor: Options tab
 Timing Analyzer: Timing Objects tab

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5.2.4 Process types
The following types of processes are available as you work on your design:
 Tasks
When you run a task process, the ISE software runs in "batch mode," that is, the
software processes your source file but does not open any additional software tools in
the Workspace. Output from the processes appears in the Transcript window.
 Reports
Most tasks include report sub-processes, which generate a summary or status report,
for example, the Synthesis Report or Map Report. When you run a report process, the
report appears in the Workspace.
 Tools
When you run a tools process, the related tool launches in standalone mode or appears
in the Workspace where you can view or modify your design source files.
5.2.5 Process status
As you work on your design, you may make changes that require some or all of the
processes to be rerun. For example, if you edit a source file, it may require that the
Synthesis process and all subsequent process be rerun. Project Navigator keeps track of
the changes you make and shows the status of each process with the following status
icons:
 Running
This icon shows that the process is running.
 Up-to-date
This icon shows that the process ran successfully with no errors or warnings and does
not need to be rerun. If the icon is next to a report process, the report is up-to-date;
however, associated tasks may have warnings or errors. If this occurs, you can read the
report to determine the cause of the warnings or errors.
 Warnings reported
This icon shows that the process ran successfully but that warnings were encountered.
 Errors reported

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This icon shows that the process ran but encountered an error.
 Out-of-Date
This icon shows that you made design changes, which require that the process be
rerun. If this icon is next to a report process, you can rerun the associated task process
to create an up-to-date version of the report.
 No icon
If there is no icon, this shows that the process was never run.
5.2.6 Running processes
To run a process, you can do any of the following:
 Double-click the process
 Right-click while positioned over the process, and select Run from the popup menu, as
shown in the following figure.
Fig 5.3 Running processes
 Select the process, and then click the Run toolbar button .
 To run the Implement Design process and all preceding processes on the top module
for the design, select Process>Implement Top Module, or click the Implement
Top Module toolbar button .
When you run a process, Project Navigator automatically processes your design as
follows:
 Automatically runs lower-level processes
When you run a high-level process, Project Navigator runs associated lower-level
processes or sub-processes. For example, if you run Implement Design for your FPGA
design, all of the following sub-processes run: Translate, Map, and Place & Route.
 Automatically runs preceding processes

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When you run a process, Project Navigator runs any preceding processes that are
required, thereby "pulling" your design through the design flow. For example, to pull
your design through the entire flow, double-click Generate Programming File.
 Automatically runs related processes for out-of-date processes
If you run an out-of-date process, Project Navigator runs that process and any related
processes required to bring that process up to date. It does not necessarily run all
preceding processes. For example if you change your UCF file, the Synthesize process
remains up to date, but the Translate process becomes out of date. If you run the Map
process, Project Navigator runs Translate but does not run Synthesize.
5.2.7 Setting process properties
Most processes have a set of properties associated with them. Properties control
specific options, which correspond to command line options. When properties are
available for a process, you can right-click while positioned over the process and select
properties from the popup menu, as shown in the following figure.
Fig 5.4 Setting process properties
When you select Properties, a Process Properties dialog box appears, with
standard properties that you can set. The Process Properties dialog box differs depending
on the process you select.
After you become familiar with the standard properties, you can set additional,
advanced properties in the Process Properties dialog box; however, setting these options
is not recommended if you are just getting started with using the ISE software. When you
enable the advanced properties, both standard and advanced properties appear in the
Process Properties dialog box.
5.3 Using the workspace
When you open a project source file, open the Language Templates, or run certain
processes, such as viewing reports or logs, the corresponding file or view appears in the

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Workspace. You can open multiple files or views at one time. Tabs at the bottom of the
Workspace show the names for each file or view. Click a tab to bring it to the front.
To open a file or view in a standalone window outside of the Project Navigator
Workspace, use the Float toolbar button. To dock a floating window, use the Dock
toolbar button.
 Float
 Dock
5.3.1 Using the transcript window
The Console tab of the Transcript window shows output messages from the processes
you run. When the following icons appear next to a message, you can right-click the
message and select Go to Answer Record to open the Xilinx website and show any
related Answer Records. If a line number appears as part of the message, you can right-
click the message and select Go to Source to open the source file with the appropriate
line number highlighted.
 Warning
 Error
Depending on the source file and tool you are working with, additional tabs are
available in the Transcript window:
 Always available: Console tab, Errors tab, Warnings tab, Tcl Shell tab, Find in Files
tab
 ISE Simulator: Simulation Console tab
 RTL and Technology Viewers: View by Name tab, View by Category tab
5.3.2 Using the toolbars
Toolbars provide convenient access to frequently used commands. Click once on a
toolbar button to execute a command. To see a short popup description of a toolbar
button, hold the mouse pointer over the button for about two seconds. A longer
description appears in the status bar at the bottom of the main window.

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5.4 Creating a project
Project Navigator allows you to manage your FPGA and CPLD designs using an
ISE™ project, which contains all the files related to your design. First, you must create a
project and then add source files. With your project open in Project Navigator, you can
view and run processes on all the files in your design. Project Navigator provides a
wizard to help you create a new project, as follows.
5.4.1 To create a project
1. Select File > New Project.
2. In the New Project Wizard Create New Project page, do the following:
a) In the Project Name field, enter a name for the project. Follow the naming
conventions described in File Naming Conventions.
b) In the Project Location field, enter the directory name or browse to the directory.
c) In the Top-Level Source Type drop-down list, select one of the following:
 HDL: Select this option if your top-level design file is a VHDL, Verilog, or
ABEL (for CPLDs) file. An HDL Project can include lower-level modules of different
file types, such as other HDL files, schematics, and "black boxes," such as IP cores
and EDIF files.
 Schematic: Select this option if your top-level design file is a schematic file. A
schematic project can include lower-level modules of different file types, such as HDL
files, other schematics, and "black boxes," such as IP cores and EDIF files. Project
Navigator automatically converts any schematic files in your design to structural HDL
before implementation; therefore, you must specify a synthesis tool when working with
schematic projects, as described in step 5.
 EDIF: Select this option if you converted your design to this file type, for
example, using a synthesis tool. Using this file type allows you to skip the Project
Navigator synthesis process and to start with the implementation processes.
 NGC/NGO: Select this option if you converted your design to this file type, for
example, using a synthesis tool. Using this file type allows you to skip the Project
Navigator synthesis process and start with the implementation processes.
3. Click Next.

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4. If you are creating an HDL or schematic project, skip to the next step. If you are
creating an EDIF or NGC/NGO project, do the following in the Import EDIF/NGC
Project page:
a) In the Input Design field, enter the name of the input design file, or browse to the
file and select it.
b) Select Copy the input design to the project directory to copy your file to the
project directory. If you do not select this option, your file is accessed from the remote
location.
c) In the Constraint File field, enter the name of the constraints file, or browse to the
file and select it.
d) Select Copy the constraints file to the project directory to copy your file to the
project directory. If you do not select this option, your file is accessed from the remote
location.
e) Click Next.
In the Device Properties page, set the following options. These settings affect
other project options, such as the types of processes that are available for your design.
 Product Category
 Family
 Device
 Package
 Speed
 Top-Level Source Type
 Synthesis Tool
Select one of the following synthesis tools and the HDL language for your project.
VHDL/Verilog is a mixed language flow. If you plan to run behavioural simulation,
your simulator must support multiple language simulation.
 XST (Xilinx® Synthesis Technology)
XST is available with ISE Foundation™ software installations. It supports
projects that include schematic design files and projects that include mixed language

33. 33
source files, such as VHDL and Verilog sources files in the same project. Simplify and
Simplify Pro (Simplicity®, Inc.).
The Simplify® software does not support projects that include mixed language
source files. The Simplify Pro® software supports projects that include mixed
language source files, such as VHDL and Verilog sources files in the same project.
The Simplify and Simplify Pro software do not support projects that include schematic
design files.
Precision(Mentor Graphics®, Inc.).
The Precision® software supports projects that include schematic design files and
projects that include mixed language source files, such as VHDL and Verilog sources
files in the same project.
 Simulator
Select one of the following simulators and the HDL language for simulation.
 ISE Simulator(Xilinx®, Inc.)
This simulator allows you to run integrated simulation processes as part of your ISE
design flow. For more information, see the ISE Simulator Help.
 ModelSim (Mentor Graphics®, Inc.)
You can run integrated simulation processes as part of your ISE design flow using any
of the following ModelSim® editions: ModelSim Xilinx Edition (MXE), ModelSim
MXE Starter, ModelSim PE, or ModelSim SE™. For more information on ModelSim,
including the differences between each edition, see Using the ModelSim Simulator.
 NC-Sim (Cadence®, Inc.)
The NC-Sim simulator is not integrated with ISE and must be run standalone. For
more information, see the documentation provided with the simulator.
 VCS (Synopsys®, Inc.)
The VCS® simulator is not integrated with ISE and must be run standalone. For more
information, see the documentation provided with the simulator.
 Other

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Select this option if you do not have ISE Simulator or ModelSim installed or if
you want to run simulation outside of Project Navigator. This instructs Project
Navigator to disable the integrated simulation processes for your project.
 Preferred Language
Select one of the following to set your preferred language. The Preferred
Language project property controls the default setting for process properties that
generate HDL output. If the Synthesis Tool and/or Simulator options are set to a
single-language tool, the default language for generated HDL output files will be
automatically chosen appropriately. If both the Synthesis Tool and Simulator options
are set to mixed-language (VHDL/Verilog) tools, you can use the Preferred Language
property to select the language in which generated HDL output will be created.
 Verilog
Select this option if both Synthesis Tool and Simulation are set to mixed-language
and you want the default language to be Verilog.
 VHDL
Select this option if both Synthesis Tool and Simulation are set to mixed-language
and you want the default language to be VHDL.
 N/A
This option will appear if both Synthesis Tool and Simulation are set to a single
language.
 Enable Enhanced Design Summary
Select this option to show the number of errors and warnings for each of the Detailed
Reports in the Design Summary.
Enable Message Filtering
Select this option to turn on Message Filtering.
Display Incremental Messages
Select this option to show the number of new messages for the most recent software
run in the Design Summary. You must enable this option and then run the software to
show the number of new messages.

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 If you are creating an EDIF or NGC/NGO project, skip to step 8. If you are
creating an HDL or schematic project,
 Click Next, and optionally, add existing source files to your project in the Add
Existing Sources page.
 Click Next to display the Project Summary page.
 Click Finish to create the project.
5.4.2 What to expect
Project Navigator creates the project file, project_name.ise, in the directory you
specified. All source files related to the project appear in the Project Navigator Sources
tab. Project Navigator manages your project based on the project properties (top-level
module type, device type, synthesis tool, and language) you selected when you created
the project. It organizes all the parts of your design and keeps track of the processes
necessary to move the design from design entry through implementation to programming
the targeted Xilinx device.
5.4.3 What to do next
You can perform any of the following:
 Create and add source files to your project.
 Add existing source files to your project.
 Run processes on your source files.
5.5 Using ISE example projects
To help familiarize you with the ISE™ software and with FPGA and CPLD
designs, a set of example designs is provided with Project Navigator. The examples show
different design techniques and source types, such as VHDL, Verilog, ABEL, schematic,
or EDIF, and include different constraints and stimulus files.
5.5.1 To open an example
1. Select File > Open Example.
2. In the Open Example Project dialog box, select the Sample Project Name that you
want to use.

36. 36
To help you choose an example project, the Project Description field describes each
project. In addition, you can scroll to the right to see additional fields, which provide
details about the project.
3. In the Destination Directory field, enter a directory name or browse to the
directory.
4. Click OK.
5.5.2 What to expect
The example project is placed in the directory you specified in the Destination
Directory field and is automatically opened in Project Navigator. You can then run
processes on the example project and save any changes.
5.5.3 Creating a source file
A source file is any file that contains information about a design. Project
Navigator provides a wizard to help you create new source files for your project.
5.5.4 What to do first
Open a project in Project Navigator.
5.5.5 To create a source file
1. Select Project > New Source.
2. In the New Source Wizard, select the type of source you want to create.
Different source types are available depending on your project properties (top-level
module type, device type, synthesis tool, and language). Some source types launch
additional tools to help you create the file, as described in Source File Types.
3. Enter a name for the new source file in the File Name field. Follow the naming
conventions described in File Naming Conventions.
4. In the Location field, enter the directory name or browse to the directory.
5. Select Add to Project to automatically add this source to the project.
6. Click Next.
7. If you are creating a source file that needs to be associated with an existing source
file, select the appropriate source file, and click Next. If this does not apply, skip to the
next step.

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8. In the New Source Wizard - Summary window, verify the information for the new
source, and click Finish.
5.5.6 What to expect
After you click Finish, the New Source wizard closes. In some cases, a related
tool is launched in which you can finish creating your file. After the source file is created,
it appears in the Project Navigator Sources tab. If you selected Add to Project when
creating the source file, the file is automatically added to the project.
5.5.7 Adding a source file to a project
Project Navigator allows you to add an existing source file to a project. The
source file can reside in the project directory or in a remote directory. If you generated
your source file using the New Source wizard and selected Add to Project, you do not
need to add the source file to your project; it is automatically part of your project.
5.5.8 What to do first
Open a project in Project Navigator.
5.5.9 To add a source file to a project
1. Select Project>Add Source.
2. In the Add Existing Sources dialog box, browse to the source file and select it.
3. Click Open.
5. In the Adding Source Files dialog box, select the Design View in which you want
the source file to appear.
6. Click OK.

38. 38
CHAPTER 6
VERILOG HDL
Verilog standardized as IEEE 1364, is a hardware description language (HDL)
used to model electronic systems. It is most commonly used in the design and verification
of digital circuits at the register-transfer level of abstraction. It is also used in the
verification of analog circuits and mixed-signal circuits.
6.1 Overview
Hardware description languages such as Verilog differ from software
programming languages because they include ways of describing the propagation of time
and signal dependencies (sensitivity). There are two assignment operators, a blocking
assignment (=), and a non-blocking (<=) assignment. The non blocking assignment
allows designers to describe a state-machine update without needing to declare and use
temporary storage variables. Since these concepts are part of Verilog's language
semantics, designers could quickly write descriptions of large circuits in a relatively
compact and concise form. At the time of Verilog’s introduction (1984), Verilog
represented a tremendous productivity improvement for circuit designers who were
already using graphical schematic capture software and specially written software
programs to document and simulate electronic circuits.
The designers of Verilog wanted a language with syntax similar to the C
programming language, which was already widely used in engineering software
development. Like C, Verilog is case-sensitive and has a basic preprocessor (though less
sophisticated than that of ANSI C/C++). Its control flow keywords (if/else, for, while,
case,etc.) are equivalent, and its operator precedence is compatible. Syntactic differences
include variable declaration (Verilog requires bit-widths on net/reg types), demarcation of
procedural blocks (begin/end instead of curly braces {}), and many other minor
differences.
A Verilog design consists of a hierarchy of modules. Modules encapsulate design
hierarchy, and communicate with other modules through a set of declared input, output,
and bidirectional ports. Internally, a module can contain any combination of the
following: net/variable declarations (wire, reg, integer, etc.), concurrent and sequential
statement blocks, and instances of other modules (sub-hierarchies). Sequential statements
are placed inside a begin/end block and executed in sequential order within the block.

39. 39
However, the blocks themselves are executed concurrently, making Verilog a dataflow
language.
Verilog's concept of 'wire' consists of both signal values (4-state: "1, 0, floating,
undefined") and strengths (strong, weak, etc.). This system allows abstract modeling of
shared signal lines, where multiple sources drive a common net. When a wire has
multiple drivers, the wire's (readable) value is resolved by a function of the source drivers
and their strengths. A subset of statements in the Verilog language is synthesizable.
Verilog modules that conform to a synthesizable coding style, known as RTL (register-
transfer level), can be physically realized by synthesis software. Synthesis software
algorithmically transforms the (abstract) Verilog source into a netlist, a logically
equivalent description consisting only of elementary logic primitives (AND, OR, NOT,
flip-flops, etc.) that are available in a specific FPGA or VLSI technology. Further
manipulations to the netlist ultimately lead to a circuit fabrication blueprint (such as a
photo mask set for an ASIC or a bit stream file for an FPGA).
6.2 History
6.2.1 Beginning
Verilog was the first modern hardware description language to be invented. It was
created by Phil Moorby and PrabhuGoel during the winter of 1983/1984. The wording for
this process was "Automated Integrated Design Systems" (later renamed to Gateway
Design Automation in 1985) as a hardware modeling language. Gateway Design
Automation was purchased by Cadence Design Systems in 1990. Cadence now has full
proprietary rights to Gateway's Verilog and the Verilog-XL, the HDL-simulator that
would become the de facto standard (of Verilog logic simulators) for the next decade.
Originally, Verilog was intended to describe and allow simulation; only afterwards was
support for synthesis added.
6.2.2 Verilog 2005
Not to be confused with SystemVerilog, Verilog 2005 (IEEE Standard 1364-
2005) consists of minor corrections, spec clarifications, and a few new language features
(such as the uwire keyword).A separate part of the Verilog standard, Verilog-AMS,
attempts to integrate analog and mixed signal modeling with traditional Verilog.

40. 40
6.3 Verilog simulators
Verilog simulators are software packages that emulate the Verilog hardware
description language. Verilog simulation software has come a long way since its early
origin as a single proprietary product offered by one company. Today, Verilog simulators
are available from many vendors, at all price points. For desktop/personal use, Aldec,
Mentor, LogicSim, SynaptiCAD, and others offer <$5000 USD tool-suites for the
Windows 2000/XP platform. The suites bundle the simulator engine with a complete
development environment: text editor, waveform viewer, and RTL-level browser.
Additionally, limited-functionality.
editions of the Aldec and ModelSim simulator are downloadable free of charge, from
their respective OEM partners (Actel, Altera, Lattice Semiconductor, Xilinx, etc.) For
those desiring open-source software, there is Icarus Verilog, among others.Beyond the
desktop level, enterprise-level simulators offer faster simulation runtime, more robust
support for mixed-language (VHDL and Verilog) simulation, and most importantly, are
validated for timing-accurate (SDF-annotated) gate-level simulation. The last point is
critical for the ASIC tape out process, when a design database is released to
manufacturing. (Semiconductor found riesstipulate the usage of tools chosen from an
approved list, in order for the customer's design to receive signoff status. Although the
customer is not required to perform any signoff checking, the tremendous cost of a wafer
order has generally ensured thorough design-validation on the part of the customer.) The
three major signoff-grade simulators include Cadence Incisive Enterprise Simulator,
Mentor ModelSim/SE, and Synopsys VCS. Pricing is not published publicly, but all three
vendors charge $25,000-$100,000 USD per seat, 1-year time-based license. FPGA
vendors do not require expensive enterprise simulators for their design flow. In fact, most
vendors include an OEM version of a third-party HDL simulator in their design suite. The
bundled simulator is taken from an entry-level or low-capacity edition, and bundled with
the FPGA vendor's device libraries. For designs target high capacity FPGA, a standalone
simulator recommended, as the OEM-version may lack the capacity or speed to
effectively handle large designs.
6.4 System Verilog
System Verilog is a superset of Verilog-2005, with many new features and
capabilities to aid design verification and design modeling. As of 2009, the System

41. 41
Verilog and Verilog language standards were merged into System Verilog 2009 (IEEE
Standard 1800-2009).
The advent of hardware verification languages such as OpenVera, and Verisity's e
language encouraged the development of Superlog by Co-Design Automation Inc. Co-
Design Automation Inc was later purchased by Synopsys. The foundations of Superlog
and Vera were donated to Accellera, which later became the IEEE standard P1800-2005:
SystemVerilog
6.4.1 Definition of constants
The definition of constants in Verilog supports the addition of a width parameter.
The basic syntax is:
<Width in bits>'<base letter><number>
Examples:
12'h123 - Hexadecimal 123 (using 12 bits)
20'd44 - Decimal 44 (using 20 bits - 0 extension is automatic)
4'b1010 - Binary 1010 (using 4 bits)
6'o77 - Octal 77 (using 6 bits)
6.4.2 Initial and always
There are two separate ways of declaring a Verilog process. These are the always
and the initial keywords. The always keyword indicates a free-running process. The initial
keyword indicates a process executes exactly once. Both constructs begin execution at
simulator time 0, and both execute until the end of the block. Once an always block has
reached its end, it is rescheduled (again). It is a common misconception to believe that an
initial block will execute before an always block. In fact, it is better to think of the initial-
block as a special-case of the always-block, one which terminates after it completes for
the first time.
//Examples:
initial
begin
a = 1; // Assign a value to reg a at time 0

42. 42
#1; // Wait 1 time unit
b = a; // Assign the value of reg a to reg b
end
always @(a or b) // Any time a or b CHANGE, run the process
begin
if (a)
c = b;
else
d = ~b;
end// Done with this block, now return to the top (i.e. the @ event-control)
always @(posedge a)// Run whenever reg a has a low to high change
a <= b;
These are the classic uses for these two keywords, but there are two significant
additional uses. The most common of these is an always keyword without the @(...)
sensitivity list. It is possible to use always as shown below:
always
begin// Always begins executing at time 0 and NEVER stops
clk = 0; // Set clk to 0
#1; // Wait for 1 time unit
clk = 1; // Set clk to 1
#1; // Wait 1 time unit
end// Keeps executing - so continue back at the top of the begin
The always keyword acts similar to the "C" construct while(1) {..} in the sense that it
will execute forever. The other interesting exception is the use of the initial keyword with
the addition of the forever keyword.
The example below is functionally identical to the always example above.
initial forever // Start at time 0 and repeat the begin/end forever

43. 43
begin
clk = 0; // Set clk to 0
#1; // Wait for 1 time unit
clk = 1; // Set clk to 1
#1; // Wait 1 time unit
End

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CHAPTER 7
ADVANTAGES AND APPLICATIONS
Advantages
 Delay will be reduced.
 Area Efficient adders.
 Low power adders.
Applications
 Digital systems designing
 Digital signal processing
 Multiplication and Accumulation
 Arithmetic and Logic Unit (ALU)
 Microprocessors

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CHAPTER 8
CONCLUSION
This brief presents an efficient implementation of a PASTA. Initially, the
theoretical foundation for a single-rail wave-pipelined adder is established.
Subsequently, the architectural design is presented. The design achieves a very simple
n-bit adder that is area and interconnection-wise equivalent to the simplest adder
namely the RCA. Moreover, the circuit work sin a parallel manner for independent
carry chains, and thus achieves logarithmic average time performance over random
input values. The completion detection unit for the proposed adder is also practical and
efficient. Simulation results are used to verify the advantages of the proposed
approach.

46. 46
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[1] D. Geer, “Is it time for clockless chips? [Asynchronous processor chips],” IEEE
Comput., vol. 38, no. 3, pp. 18–19,Mar. 2005.
[2] J. Sparsø and S. Furber, Principles of Asynchronous Circuit Design. Boston, MA, USA:
Kluwer Academic, 2001.
[3] P. Choudhury, S. Sahoo, and M. Chakraborty, “Implementation of basic arithmetic
operations using cellular automaton,” in Proc. ICIT, 2008,pp. 79–80.
[4] M. Z. Rahman and L. Kleeman, “A delay matched approach for the design of
asynchronous sequential circuits,” Dept. Comput. Syst.Technol., Univ. Malaya, Kuala
Lumpur, Malaysia, Tech. Rep. 05042013,2013.
[5] M. D. Riedel, “Cyclic combinational circuits,” Ph.D. dissertation, Dept. Comput. Sci.,
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[6] R. F. Tinder, Asynchronous Sequential Machine Design and Analysis: A
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Machines and Systems. San Mateo, CA, USA:Morgan, 2009.
[7] W. Liu, C. T. Gray, D. Fan, and W. J. Farlow, “A 250-MHz wave pipelined adder in 2-
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[8] F.-C. Cheng, S. H. Unger, and M. Theobald, “Self-timed carry look ahead adders,”
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49, no. 8, pp. 577–588,Aug. 2002.

47. 47
Ms. V. Pavani Sujata, Ms. M. Mounika, Ms. D. Vidya, P. Chendrashekar.
ProjectDetails:
Recursive Approach to the Design of Self Timed Adder using Verilog
Guide Name: Ms. M. Mounika
Batch no.: B3
Batch Members: Ms. D. Vidya (14C35A0409)
Ms. V. Pavani Sujatha (13C31A04A1)
Mr. P. Chendra Shekar (13C31A0471)

48. 48
APPENDIX
module recu_add(a,b,cin,sel,sum);
input cin,sel;
input [31:0]a,b;
output reg [32:0]sum;
reg [31:0]muxa,muxb,s;
reg [32:0]c;
integer i;
always@(posedge clk)
begin
for(i=0;i<32;i=i+1)
begin
c[0]<=cin;
muxa[i]<=mux(a[i],s[i],sel);
muxb[i]<=mux(b[i],c[i],sel);
$display("value of i",i);
$display("value of muxa[i]=",muxa[i]);
$display("value of muxb[i]=",muxb[i]);
s[i]<=muxa[i]^muxb[i];
c[i+1]<=muxa[i]&muxb[i];
$display("value of s[i]",s[i]);
$display("value of c[i+1]",c[i+1]);
end
sum={c[32],s};
end
function mux;

49. 49
input x,y,s;
begin
mux=(x&&~s)||(y&&s);
end
endfunction
endmodule
module tb;
// Inputs
reg [31:0] a;
reg [31:0] b;
reg cin;
reg sel;
reg clk;
// Outputs
wire [32:0] sum;
// Instantiate the Unit Under Test (UUT)
recu_add uut (
.a(a),
.b(b),
.cin(cin),
.sel(sel),
.sum(sum),
.clk(clk)
);

50. 50
initial
begin
clk = 1'b1;
cin = 1'b0;
sel = 1'b0;
a = 32'b00001110101010101010101010101100;
b = 32'b00100110000101010100000000000010;
#20 sel=1'b1;
end
always #5 clk=~clk;
endmodule