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RECURSIVE APPROACH TO THE
DESIGN OF A PARALLEL
SELF-TIMED ADDER
By
Ms. D.Vidya (14C35A0409)
Ms. V.Pavanisujatha (13C31A04A1)
Mr.P.Chendra shekar (13C31A0471)
Under the guidance of
Ms. M. Mounika
Assistant professor
BALAJI INSTITUTE OF TECHNOLOGYAND SCIENCE
NARSAMPET, WARANGAL – 506 331
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
CONTENT
• INTRODUCTION
• ABSTRACT
• DESIGN OF PASTA
• ARCHITECTURE OF PASTA
• STATE DIAGRAMS FOR PASTA
• FLOW CHART
• RECURSIVE FORMULA FOR BINARY ADDITION
• SIMULATION WAVE FORM FOR RECURSIVE ADDER
• SYNTHESIS REPORT FOR RECURSIVE ADDER
• APPLICATIONS
• ADVANTAGES
• CONCLUSION
INTRODUCTION
• Binary addition is the single most important operation that a
processor performs.
• Asynchronous circuits do not assume any quantization of
time.
• In principle, logic flow in asynchronous circuits is controlled
by a request-acknowledgment handshaking protocol to
establish a pipeline in the absence of clocks.
ABSTRACT
• It is based on a recursive formulation for performing multi-bit
binary addition.
• Do not need any carry chain propagation.
• Does not have any practical limitations of high fan-outs.
• A high fan-in gate is required though but this is unavoidable
for asynchronous logic and is managed by connecting the
transistors in parallel.
DESIGN OF PASTA
• The adder first accepts two input operands to perform half
additions for each bit.
• Subsequently, it iterates using earlier generated carry and sums
to perform half-additions repeatedly until all carry bits are
consumed and settled at zero level.
ARCHITECTURE OF PASTA
Cont….
• Initially it select the actual operands during SEL = 0 and
switch to feedback/carry paths for subsequent iterations using
SEL = 1.
• The feedback path from the HAs enables the multiple
iterations to continue until the completion when all carry
signals will assume zero values.
State Diagram for PASTA
Cont…..
• During the initial phase, the circuit merely works as a
combinational HA operating in fundamental mode.
• During the iterative phase (SEL = 1), the feedback path
through multiplexer block is activated.
• The carry transitions (Ci ) are allowed as many times as
needed to complete the recursion.
FLOW CHART
Recursive Formula for Binary Addition
• Sj
i and Cj
i+1 are the sum and carry for ith bit at the jth
iteration.
• The initial condition ( j = 0) for addition is formulated as
follows:
S0
I = ai ⊕ bi
C0
i+1= ai bi .
• The jth iteration for the recursive addition is formulated by
Sj
i = S j−1
i ⊕ C j−1
i , 0 ≤ i < n
C j
i+1 = S j−1
i C j−1
i , 0 ≤ i ≤ n.
• The recursion is terminated at kth iteration when the following
condition is met:
Ck
n + Ck
n−1+ ・・ ・+Ck
1= 0, 0 ≤ k ≤ n.
SIMULATION WAVE FORM FOR
RECURSIVE ADDER
SYNTHESIS REPORT FOR RECURSIVE
ADDER
APPLICATIONS
• Digital systems designing
• Digital signal processing
• Multiplication and Accumulation
• Arithmetic and Logic Unit (ALU)
• Microprocessors
ADVANTAGES
• Delay will be reduced.
• Area Efficient adders.
CONCLUSION
• The design achieves a very simple n-bit adder that is area and
interconnection-wise equivalent to the simplest adder namely
the RCA.
• Moreover, the circuit works in a parallel manner for
independent carry chains, and thus achieves logarithmic
average time performance over random input values.
• Simulation results are used to verify the advantages of the
proposed approach.
Any Queries??????
presentation on pasta

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presentation on pasta

  • 1. RECURSIVE APPROACH TO THE DESIGN OF A PARALLEL SELF-TIMED ADDER By Ms. D.Vidya (14C35A0409) Ms. V.Pavanisujatha (13C31A04A1) Mr.P.Chendra shekar (13C31A0471) Under the guidance of Ms. M. Mounika Assistant professor BALAJI INSTITUTE OF TECHNOLOGYAND SCIENCE NARSAMPET, WARANGAL – 506 331 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
  • 2. CONTENT • INTRODUCTION • ABSTRACT • DESIGN OF PASTA • ARCHITECTURE OF PASTA • STATE DIAGRAMS FOR PASTA • FLOW CHART • RECURSIVE FORMULA FOR BINARY ADDITION • SIMULATION WAVE FORM FOR RECURSIVE ADDER • SYNTHESIS REPORT FOR RECURSIVE ADDER • APPLICATIONS • ADVANTAGES • CONCLUSION
  • 3. INTRODUCTION • Binary addition is the single most important operation that a processor performs. • Asynchronous circuits do not assume any quantization of time. • In principle, logic flow in asynchronous circuits is controlled by a request-acknowledgment handshaking protocol to establish a pipeline in the absence of clocks.
  • 4. ABSTRACT • It is based on a recursive formulation for performing multi-bit binary addition. • Do not need any carry chain propagation. • Does not have any practical limitations of high fan-outs. • A high fan-in gate is required though but this is unavoidable for asynchronous logic and is managed by connecting the transistors in parallel.
  • 5. DESIGN OF PASTA • The adder first accepts two input operands to perform half additions for each bit. • Subsequently, it iterates using earlier generated carry and sums to perform half-additions repeatedly until all carry bits are consumed and settled at zero level.
  • 7. Cont…. • Initially it select the actual operands during SEL = 0 and switch to feedback/carry paths for subsequent iterations using SEL = 1. • The feedback path from the HAs enables the multiple iterations to continue until the completion when all carry signals will assume zero values.
  • 9. Cont….. • During the initial phase, the circuit merely works as a combinational HA operating in fundamental mode. • During the iterative phase (SEL = 1), the feedback path through multiplexer block is activated. • The carry transitions (Ci ) are allowed as many times as needed to complete the recursion.
  • 11. Recursive Formula for Binary Addition • Sj i and Cj i+1 are the sum and carry for ith bit at the jth iteration. • The initial condition ( j = 0) for addition is formulated as follows: S0 I = ai ⊕ bi C0 i+1= ai bi .
  • 12. • The jth iteration for the recursive addition is formulated by Sj i = S j−1 i ⊕ C j−1 i , 0 ≤ i < n C j i+1 = S j−1 i C j−1 i , 0 ≤ i ≤ n. • The recursion is terminated at kth iteration when the following condition is met: Ck n + Ck n−1+ ・・ ・+Ck 1= 0, 0 ≤ k ≤ n.
  • 13. SIMULATION WAVE FORM FOR RECURSIVE ADDER
  • 14. SYNTHESIS REPORT FOR RECURSIVE ADDER
  • 15. APPLICATIONS • Digital systems designing • Digital signal processing • Multiplication and Accumulation • Arithmetic and Logic Unit (ALU) • Microprocessors
  • 16. ADVANTAGES • Delay will be reduced. • Area Efficient adders.
  • 17. CONCLUSION • The design achieves a very simple n-bit adder that is area and interconnection-wise equivalent to the simplest adder namely the RCA. • Moreover, the circuit works in a parallel manner for independent carry chains, and thus achieves logarithmic average time performance over random input values. • Simulation results are used to verify the advantages of the proposed approach.