this is a documentation file for the project automation of railway gate using verilog

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CHAPTER 1
INTRODUCTION
There are many railway crossings which are unmanned due to lack of manpower, needed to fulfill the
demands. Hence, many accidents occur at such crossings, since there is no one to take care of the functioning
of the railway gate when a train approaches the crossing. The objective of this project is to manage the control
system of railway gate. The proposed model has been designed to avoid railway accidents occurring at
unattended railway gates, if implemented detection of train approaching can be sensed by means of sensor
placed on the gate.
Now a days, India is the country which having world’s largest railway network. Over hundreds of
railways running on track every day. As we know that it is surely impossible to stop, the running train at
instant is some critical situation or emergency arises. Train accidents having serious repercussio n in terms of
loss of human life, injury, damage to Railway property. These consequential train accidents – include
Collision, Derailments, Fire in Trains, and Collisions of trains at Level Crossings.
1.1 Problem Identification
The status of the present Indian Railway is as follows:
Presently railway-crossing gates are operated manually. At present scenario, in level crossings, a
gatekeeper operates the railway gate normally after receiving the information about the train’s arrival.
When a train starts to leave a station, stationmaster of the particular station delivers the information to the
nearby gate.
The above said procedures are followed for operating the railway gates.
Problems Faced:
 Sometimes the road traffic is so busy that it becomes impossible for the gatekeeper to shut down
the gates in correct time.
 In many remote areas, railway-crossing gates are open and no person is located for the operation of
gates and hence leading to accidents.
 Many times gates are shut down too early leading to wastage of time of people stuck at crossing.
 Presently as such no centralized system is there through which we can track the location
of trains from any center point.

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 As trains cannot be centrally located, often more than one train runs on the same track in opposite
direction leading to accidents.
 Presently in Indian Railway only semiautomatic railway gate operation is followed in
certain areas.
 Signals are located in the vicinity of the railway gate along with gate master board and a marker
light.
 If barriers remain closed for excessive periods on crossings carrying a high volume of road and rail
traffic, the build-up of road traffic will exceed the capacity of the crossing to safely discharge this
build-up before the next train arrival at the crossing.
 A number of train accidents happened due to a manual system of signals between stations.
 Presently signals are control by mean of interlocking system and for this system require regular
maintenance and upgrading.
1.1.1 Train Accident:
A classification of accidents by their effects (consequences); e.g., head-on collisions, rear-end
collisions, derailments. Head on collision; one type of train accident is when two trains collide front face with
each other or train colliding on the same track from opposite ends called head on collision. Rear end collision;
the other kind is when a train collides into the other that is in front of it, called a rear end collision.
Derailments plain track; a train may derail on a simply straight track that may cause the train accident.
Curves; derailment of a train is more common when there is a curve on the track causing an accident.
Junctions; a train may also get derailed on a junction, which is the place where two tracks converge into one,
or one diverges into two.
Accident contributors such as train visibility advance signs, active warning, driver behavior, driver
distraction and risk taking have been identified as common human factors contributors to vehicle train grade
crossing accident. Factor includes highway and railway characteristic are contributing factor to accident at
RLC.

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The environmental factors are snow, heavy rain, fog, or blowing snow, which collision the train. The three
main factors contributing to accidents at RLC is basic safety engineering studies, human factor, engineering
factor, and environment factor. The taxonomy of railway intersection accident contributors was created to
generate
Figure 1.1 Specific Cases and Common Patterns of Accident
1.2 PresentIndian RailwayTechnology:
The ministry of railways has taken steps to reduce the consequential train collision accidents and level
crossing accidents. Ministry of railways has invested several crore rupees for modernization and uplift nets of
the technologies used in Indian Railways. Presently Indian Railway provides some sign and signal to prevent
the train accident

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1.2.1 Warning Signs and Devices used in Indian Railway to Reduce the Level Crossing Advance
Warning Sign
Sign tells you to slow down, look and listen for the train, and be prepared to stop at the tracks if a train
is coming.
Figure 1.2 Advance Warning Sign
1.2.1a Cross-Bucks Sign:
Cross bucks are located at all grade crossings on both approaches to the crossing. Form an X via the
intersection of two 1200 mm x 200 mm retro-reflective pieces. A cross buck sign provides the last indication
to the driver where the crossing is located.
Figure 1.3 Cross buck Sign

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1.2.1b Multiple Track Signals
Multiple track signals are required when there is more than one track present and are attached below
the cross buck sign. A multiple track sign under the cross buck tells the driver the numb more than a single
track.
Figure 1.4 Multiple Track Signals
1.2.1c Whistle Indicator
The ‘W’ is a general whistle indicator while the ‘W/L’ stands for whistle for level crossing. ( ‘see/pha’
= ‘seeteebajao–phatak’).
Figure 1.5: Whistle Indicator

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1.2.1d Level Crossing Indicator
A square yellow board indicates approach to a level crossing.
Figure 1.6: Level Crossing Indicator
1.2.1e Stop Sign and Line
Minimum standard stop sign dimensions are 600 mm x 600 mm and sign shape is octagonal A stop line
painted across your lane of the road shows you where to stop and look for an approaching train. On a gravel
road with no marking, stop at least 15 feet from the railroad tracks.
Figure 1.7 Stop Sign and Line

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1.2.1f Roadway Pavement marking
Pavement markings are painted on the roadway just past the AWS and before a highway-railway
crossing. The pavements markings consist of a large “X” with a stroke width of 300 to 500 mm. dimensions
of the “X” are 6.0 m long and 2.5 m wide. Retro-reflective paint must be used and the “X” must be
incorporated on each side of the road before the railway gate.
Figure 1.8: Roadway Preventive Mark crossing
1.2.2 Manually Activated Signal
Manually Activated Signals are operated by level crossing staff, on instructions transmitted by
telephone or telegraph signal from the nearest station. Automatic Warning Signals need short track circuits or
markers which detect trains and activate warning indications at level crossings. These warning indications are
usually flashing lights, or sounds emitted by bells or claxons (horns), or a combination of these two.
1.2.3 Mechanical Crossing Barriers
Mechanical crossing barriers are operated by level crossing staff using hand or electrically powered
levers, winches or windlasses. In addition, mechanical barriers providing complete protection of level
crossings are connected to manually operate warning signals (Light and Sound).

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1.2.4 Technology Used to Reduce the Train Accidents
Walkie– Talkie Set of Crew
5 W walkie-talkie sets have been provided to drivers and guards of all the trains for communication in
static mode or at low speeds. 25W VHF sets have also been provided at stations on broad gauge double line /
multiple line sections so that train crew can communicate with the nearest station masters in the case of
emergencies. This is duplex communication wherein both the parties can talk simultaneously. The works for
provision of MTRC have been sanctioned on 2,415 km. It will be GSM based MTRC system with digital
technology, as being used by cellular networks worldwide.
1.3 Auxiliary Warning System
Automatic train protection and warning system provides audiovisual warning to the driver and prevents
him from passing signals at danger. Presently, an AWS is working on Mumbai suburban area of western and
central railways. AWS on 128 kms stretch of southern railway is in progress.
1.3.1 Railway Signal
Hand signals flags, lamps, bells, and whistles, all right signal, guard’s signals, all-ready signal. Hand
signals include signals given by hand, or by flags or lamps used by the signalman, drivers, guards, or station
staff. The all-right signal refers to the display of green flags by stationmasters (or other staff), line side
workers; level crossing gatekeepers, and others, to passing trains. The green flag is held in the left hand. The
red flag is kept ready to be displayed in case of a problem in the right hand. A steady green signal shown by
the guard is an indication that there is no problem (or no longer any problem) and that the train can continue
on its journey. A green flag or lamp waved violently up and down, however, is the signal that the train has
parted, and the driver should bring his portion of the train to a halt. The all-ready signal is given to indicate
that everything is ready and in order for the train movement for which it is given. It is given by 3 quick waves
a green flag horizontally followed by 2 quick waves vertically; at night, waves of a green lamp are used in
similar fashion.

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1.4ResearchWorks
1.4.1 Flasher Light
Aberg L. et.al Flasher lights have been provided on all 7000 locomotives to warn trains coming from
opposite direction, after a derailment on double line, and prevent such type of collisions. Automatic switching
“ON” of the flasher lights, not requiring the interference of drivers and becoming operational in case of
sudden need, have also been introduced. Automatic loco flasher lights are being progressively installed on
locomotives to
give indication to drivers of trains running from opposite direction in case of mishap for prevention of further
accidents.
1.4.2 Automatic Warning Signals
San Francisco’s et.al. Automatic Warning Signals need short track circuits or markers which detect
trains and activate warning indications at level crossings. These warning indications are usually flashing
lights, or sounds emitted by bells or claxons (horns), or a combination of these two.

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CHAPTER 2
IMPLEMENTAION
2.1 FSM
A finite-state machine (FSM) or finite-state automaton (plural: automata), or simply a state machine, is
a mathematical model of computation used to design both computer programs and sequential logic circuits. It
is conceived as an abstract machine that can be in one of a finite number of states. The machine is in only one
state at a time; the state it is in at any given time is called the current state. It can change from one state to
another when initiated by a triggering event or condition; this is called a transition. A particular FSM is
defined by a list of its states, and the triggering condition for each transition.
The behavior of state machines can be observed in many devices in modern society which perform a
predetermined sequence of actions depending on a sequence of events with which they are presented. Simple
examples are vending machines which dispense products when the proper combination of coins is deposited,
elevators which drop riders off at upper floors before going down, traffic lights which change sequence when
cars are waiting, and combination locks which require the input of combination numbers in the proper order.
Finite-state machines can model a large number of problems, among which are electronic design
automation, communication protocol design, language parsing and other engineering applications. In biology
and artificial intelligence research, state machines or hierarchies of state machines have been used to describe
neurological systems and in linguistics—to describe the grammars of natural languages.
Considered as an abstract model of computation, the finite state machine is weak; it has less
computational power than some other models of computation such as the Turing machine. That is, there are
tasks which no FSM can do, but some Turing machines can. This is because the FSM has limited memory.
The memory is limited by the number of states.
2.2 Moore Machine
In the theory of computation, a Moore machine is a finite-state machine whose output values are
determined solely by its current state. This is in contrast to a Mealy machine, whose output values are
determined both by its current state and by the values of its inputs.
Most digital electronic systems are designed as clocked sequential systems. Clocked sequential
systems are a restricted form of Moore machine where the state changes only when the global clock signal
changes. Typically the current state is stored in flip-flops, and a global clock signal is connected to the "clock"
input of the flip-flops. Clocked sequential systems are one way to solve meta stability problems. A typical
electronic Moore machine includes a combinational logic chain to decode the current state into the outputs

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(lambda). The instant the current state changes, those changes ripple through that chain, and almost
instantaneously the output gets updated. There are design techniques to ensure that no glitches occur on the
outputs during that brief period while those changes are rippling through the chain, but most systems are
designed so that glitches during that brief transition time are ignored or are irrelevant. The outputs then stay
the same indefinitely (LEDs stay bright, power stays connected to the motors, solenoids stay energized, etc.),
until the Moore machine changes state again.
FIGURE 2.1:Moore machine
2.3 Mealymachine
In the theory of computation, a Mealy machine is a finite-state machine whose output values are
determined both by its current state and the current inputs. (This is in contrast to a Moore machine, whose
output values are determined solely by its current state.) A Mealy machine is a deterministic finite state
transducer: for each state and input, at most one transition is possible.
A simple Mealy machine has one input and one output. Each transition edge is labeled with the value
of the input (shown in red) and the value of the output (shown in blue). The machine starts in state Si. (In this
example, the output is the exclusive-or of the two most-recent input values; thus, the machine implements an
edge detector, outputting a one every time the input flips and a zero otherwise.)

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Figure:2.2 state diagram
Mealy machines provide a rudimentary mathematical model for cipher machines. Considering the input
and output alphabet the Latin alphabet, for example, then a Mealy machine can be designed that given a string
of letters (a sequence of inputs) can process it into a ciphered string (a sequence of outputs). However,
although one could use a Mealy model to describe the Enigma, the state diagram would be too complex to
provide feasible means of designing complex ciphering machines.
2.4 OPERATION
Detection of train approaching the gate can be sensed by means of sensors R1, R2, R3&R4 placed on
either side of the gate. In particular direction of approach, R1 is used to sense the arrival; R3 is used to sense
the departure of the train. In the same way R2 & R4 senses arrival and departure in the other direction. The
sensors R1 & R4 are placed five kilometers before the gate and sensors R2 & R3 are placed one kilometer
before the gate. While either the sensor of R2 or R3 are activated, the counter will be down counted from
fifteen to zero. This counter is used to close the gate while train is arriving.

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Initially the road user signals are made GREEN so that they freely move through gate. Buzzer is OFF since
there is no approach of train and users need not be warned.
2.5 FlowchartAlgorithm
2.5.1a TRAIN ARRIVAL DETECTION
start
IR1 sensor
is activated
Train
Arrival
Is
detected
Buzzer buzzes &
yellow signal
IR2 activated
Red signal & buzzer
on
Gates close
end
yes
NO
Figure 2.2: Flow Chart-1

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• When the train arrival is sensed by the first sensor, the signal will be YELLOW and the buzzer will be
ON since there is approach of train and users need to be warned.
• After sensing the next sensor the gate is closed and signal for road users are made RED so that the
vehicles cannot pass through the gate.
2.5.1b TRAIN DEPARTURE DETECTION
start
IR3 sensor
is activated
Train
departure
Is
detected
Buzzer off & yellow
signal
IR4 activated
green signal &
Gates open
end
yes
NO
Figure 2.3: Flow Chart-2
• When the train departure is sensed by the third sensor , the signal will be YELLOW and the buzzer
will be OFF.
• When the train departure is sensed by the fourth sensor, the gates are opened.
• Once the gate is opened signal for road users are made GREEN so that the vehicles can pass through
the gate.

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2.6 Working
reset
light=green, count=0,light=yellow
count=0
count =15,
light=red.
Counter =15, light=yellow
Figure 2.4 State Diagram
 Initially, the light will be in green colour, and the four sensors will be in working state, waiting for the
train to which it will be activated.
 When train comes in ,the sensor1 and the alarm will be activated and light goes yellow.
 So, in this project ,15 clocks has been taken to activate while either the sensor2 or3 activated
according to train’s arrival.
 So, when the sensor 2 is activated, the counter will be activated and light goes red and gate will be
closed.
 when the sensor 3 is activated, the light goes yellow and the alarm will be off.
 When sensor4 is activated, the train departure over there and the gate goes up and light goes green.
Sensor1
Sensor2
Sensor3
Sensor4

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CHAPTER-3
VERILOG HDL
Verilog standardized as IEEE 1364, is a hardware description language (HDL) used to model
electronic systems. It is most commonly used in the design and verification of digital circuits at the register-
transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits.
3.1 OVERVIEW
Hardware description languages such as Verilog differ from software programming languages because
they include ways of describing the propagation of time and signal dependencies (sensitivity). There are two
assignment operators, a blocking assignment (=), and a non-blocking (<=) assignment. The non blocking
assignment allows designers to describe a state-machine update without needing to declare and use temporary
storage variables. Since these concepts are part of Verilog's language semantics, designers could quickly write
descriptions of large circuits in a relatively compact and concise form. At the time of Verilog’s introduction
(1984), Verilog represented a tremendous productivity improvement for circuit designers who were already
using graphical schematic capture software and specially written software programs to document and simulate
electronic circuits.
The designers of Verilog wanted a language with syntax similar to the C programming language,
which was already widely used in engineering software development. Like C, Verilog is case-sensitive and
has a basic preprocessor (though less sophisticated than that of ANSI C/C++). Its control flow keywords
(if/else, for, while, case,etc.) are equivalent, and its operator precedence is compatible. Syntactic differences
include variable declaration (Verilog requires bit-widths on net/reg types), demarcation of procedural blocks
(begin/end instead of curly braces {}), and many other minor differences.
A Verilog design consists of a hierarchy of modules. Modules encapsulate design hierarchy, and
communicate with other modules through a set of declared input, output, and bidirectional ports. Internally, a
module can contain any combination of the following: net/variable declarations (wire, reg, integer, etc.),
concurrent and sequential statement blocks, and instances of other modules (sub-hierarchies). Sequential
statements are placed inside a begin/end block and executed in sequential order within the block. However,
the blocks themselves are executed concurrently, making Verilog a dataflow language.

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Verilog's concept of 'wire' consists of both signal values (4-state: "1, 0, floating, undefined") and
strengths (strong, weak, etc.). This system allows abstract modeling of shared signal lines, where multiple
sources drive a common net. When a wire has multiple drivers, the wire's (readable) value is resolved by a
function of the source drivers and their strengths. A subset of statements in the Verilog language is
synthesizable. Verilog modules that conform to a synthesizable coding style, known as RTL (register-transfer
level), can be physically realized by synthesis software. Synthesis software algorithmically transforms the
(abstract) Verilog source into a netlist, a logically equivalent description consisting only of elementary logic
primitives (AND, OR, NOT, flip-flops, etc.) that are available in a specific FPGA or VLSI technology.
Further manipulations to the netlist ultimately lead to a circuit fabrication blueprint (such as a photo mask set
for an ASIC or a bitstream file for an FPGA).
3.2 HISTORY
3.2.1 Beginning
Verilog was the first modern hardware description language to be invented. It was created by Phil
Moorby and PrabhuGoel during the winter of 1983/1984. The wording for this process was "Automated
Integrated Design Systems" (later renamed to Gateway Design Automation in 1985) as a hardware modeling
language. Gateway Design Automation was purchased by Cadence Design Systems in 1990. Cadence now
has full proprietary rights to Gateway's Verilog and the Verilog-XL, the HDL-simulator that would become
the de facto standard (of Verilog logic simulators) for the next decade. Originally, Verilog was intended to
describe and allow simulation; only afterwards was support for synthesis added.
3.2.2 Verilog 2005
Not to be confused with SystemVerilog, Verilog 2005 (IEEE Standard 1364-2005) consists of minor
corrections, spec clarifications, and a few new language features (such as the uwire keyword).A separate part
of the Verilog standard, Verilog-AMS, attempts to integrate analog and mixed signal modeling with
traditional Verilog.
3.3 VERILOG SIMULATORS
Verilog simulators are software packages that emulate the Verilog hardware description language.
Verilog simulation software has come a long way since its early origin as a single proprietary product offered
by one company. Today, Verilog simulators are available from many vendors, at all price points. For
desktop/personal use, Aldec, Mentor, LogicSim, SynaptiCAD, and others offer <$5000 USD tool-suites for
the Windows 2000/XP platform. The suites bundle the simulator engine with a complete development
environment: text editor, waveform viewer, and RTL-level browser. Additionally, limited-functionality
editions of the Aldec and ModelSim simulator are downloadable free of charge, from their respective OEM

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partners (Actel, Altera, Lattice Semiconductor, Xilinx, etc.) For those desiring open-source software, there is
Icarus Verilog, among others.Beyond the desktop level, enterprise-level simulators offer faster simulation
runtime, more robust support for mixed-language (VHDL and Verilog) simulation, and most importantly, are
validated for timing-accurate (SDF-annotated) gate-level simulation. The last point is critical for the ASIC
tape out process, when a design database is released to manufacturing. (Semiconductor found riesstipulate the
usage of tools chosen from an approved list, in order for the customer's design to receive signoff status.
Although the customer is not required to perform any signoff checking, the tremendous cost of a wafer order
has generally ensured thorough design-validation on the part of the customer.) The three major signoff-grade
simulators include Cadence Incisive Enterprise Simulator, Mentor ModelSim/SE, and Synopsys VCS. Pricing
is not published publicly, but all three vendors charge $25,000-$100,000 USD per seat, 1-year time-based
license. FPGA vendors do not require expensive enterprise simulators for their design flow. In fact, most
vendors include an OEM version of a third-party HDL simulator in their design suite. The bundled simulator
is taken from an entry-level or low-capacity edition, and bundled with the FPGA vendor's device libraries. For
designs target high capacity FPGA, a standalone simulator recommended, as the OEM-version may lack the
capacity or speed to effectively handle large designs.
3.4 System Verilog
System Verilog is a superset of Verilog-2005, with many new features and capabilities to aid design
verification and design modeling. As of 2009, the System Verilog and Verilog language standards were
merged into System Verilog 2009 (IEEE Standard 1800-2009).
The advent of hardware verification languages such as OpenVera, and Verisity's e language
encouraged the development of Superlog by Co-Design Automation Inc. Co-Design Automation Inc was later
purchased by Synopsys. The foundations of Superlog and Vera were donated to Accellera, which later became
the IEEE standard P1800-2005: SystemVerilog
3.4a Definition of constants
The definition of constants in Verilog supports the addition of a width parameter. The basic syntax is:
<Width in bits>'<base letter><number>
Examples:
12'h123 - Hexadecimal 123 (using 12 bits)
20'd44 - Decimal 44 (using 20 bits - 0 extension is automatic)

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4'b1010 - Binary 1010 (using 4 bits)
6'o77 - Octal 77 (using 6 bits)
3.4b Initial and always
There are two separate ways of declaring a Verilog process. These are the always and the initial
keywords. The always keyword indicates a free-running process. The initial keyword indicates a process
executes exactly once. Both constructs begin execution at simulator time 0, and both execute until the end of
the block. Once an always block has reached its end, it is rescheduled (again). It is a common misconception
to believe that an initial block will execute before an always block. In fact, it is better to think of the initial-
block as a special-case of the always-block, one which terminates after it completes for the first time.
//Examples:
initial
begin
a = 1; // Assign a value to reg a at time 0
#1; // Wait 1 time unit
b = a; // Assign the value of reg a to reg b
end
always @(a or b) // Any time a or b CHANGE, run the process
begin
if (a)
c = b;
else
d = ~b;
end// Done with this block, now return to the top (i.e. the @ event-control)
always @(posedge a)// Run whenever reg a has a low to high change
a <= b;

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These are the classic uses for these two keywords, but there are two significant additional uses. The
most common of these is an always keyword without the @(...) sensitivity list. It is possible to use always as
shown below:
always
begin// Always begins executing at time 0 and NEVER stops
clk = 0; // Set clk to 0
#1; // Wait for 1 time unit
clk = 1; // Set clk to 1
#1; // Wait 1 time unit
end// Keeps executing - so continue back at the top of the begin
The always keyword acts similar to the "C" construct while(1) {..} in the sense that it will execute forever.
The other interesting exception is the use of the initial keyword with the addition of the forever keyword.
The example below is functionally identical to the always example above.
initial forever // Start at time 0 and repeat the begin/end forever
begin
clk = 0; // Set clk to 0
#1; // Wait for 1 time unit
clk = 1; // Set clk to 1
#1; // Wait 1 time unit
End

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CHAPTER 4
VLSI TECHNOLOGY
4.1 INTRODUCTIONOF VLSI
VLSI began in the 1970s when complex semiconductor and communication technologies were being
developed. The microprocessor is a VLSI device. The term is no longer as common as it once was, as chips
have increased in complexity into the hundreds of millions of transistors.
4.2 OVERVIEW
The first semiconductor chips held one transistor each. Subsequent advances added more and more
transistors, and, as a consequence, more individual functions or systems were integrated over time. The first
integrated circuits held only a few devices, perhaps as many as ten diodes, transistors, resistors and capacitors,
making it possible to fabricate one or more logic gates on a single device. Now known retrospectively as
"small-scale integration" (SSI), improvements in technique led to devices Very-large-scale integration (VLSI)
is the process of creating integrated circuits by combining thousands with hundreds of logic gates, known as
large-scale integration (LSI), i.e. systems with at least a thousand logic gates. Current technology has moved
far past this mark and today's microprocessors have many millions of gates and hundreds of millions of
individual transistors.
At one time, there was an effort to name and calibrate various levels of large-scale integration above
VLSI. Terms like Ultra-large-scale Integration (ULSI) were used. But the huge number of gates and
transistors available on common devices has rendered such fine distinctions moot. Terms suggesting greater
than VLSI levels of integration are no longer in widespread use. Even VLSI is now somewhat quaint, given
the common assumption that all microprocessors are VLSI or better.
As of early 2008, billion-transistor processors are commercially available, an example of which is
Intel's Montecito Itanium chip. This is expected to become more commonplace as semiconductor fabrication
moves from the current generation of 65 nm processes to the next 45 nm generations (while experiencing new
challenges such as increased variation across process corners). Another notable example is NVIDIA’s 280
series GPU.
This microprocessor is unique in the fact that its 1.4 Billion transistor count, capable of a teraflop of
performance, is almost entirely dedicated to logic (Itanium's transistor count is largely due to the 24MB L3

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cache). Current designs, as opposed to the earliest devices, use extensive design automation and automated
logic synthesis to lay out the transistors, enabling higher levels of complexity in the resulting logic
functionality. Certain high-performance logic blocks like the SRAM cell, however, are still designed by hand
to ensure the highest efficiency (sometimes by bending or breaking established design rules to obtain the last
bit of performance by trading stability).
4.3 WHAT IS VLSI
VLSI stands for "Very Large Scale Integration". This is the field which involves packing more and more
logic devices into smaller and smaller areas.
VLSI
1. Simply we say Integrated circuit is many transistors on one chip.
2. Design/manufacturing of extremely small, complex circuitry using modified semiconductor material
3. Integrated circuit (IC) may contain millions of transistors, each a few mm in size
4. Applications wide ranging: most electronic logic devices
4.4 HISTORY OF SCALE INTEGRATION
1. late 40s Transistor invented at Bell Labs
2. late 50s First IC (JK-FF by Jack Kilby at TI)
3. early 60s Small Scale Integration (SSI)
4. 10s of transistors on a chip
5. late 60s Medium Scale Integration (MSI)
6. 100s of transistors on a chip
7. early 70s Large Scale Integration (LSI)
8. 1000s of transistor on a chip
9. early 80s VLSI 10,000s of transistors on a
10. chip (later 100,000s & now 1,000,000s)
11. Ultra LSI is sometimes used for 1,000,000s
12. SSI - Small-Scale Integration (0-102)
13. MSI - Medium-Scale Integration (102-103)
14. LSI - Large-Scale Integration (103-105)
15. VLSI - Very Large-Scale Integration (105-107)
16. ULSI - Ultra Large-Scale Integration (>=107)

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4.5ADVANTAGES OF ICS OVER DISCRETECOMPONENTS
While we will concentrate on integrated circuits, the properties of integrated circuits-what we can and
cannot efficiently put in an integrated circuit-largely determine the architecture of the entire system.
Integrated circuits improve system characteristics in several critical ways. ICs have three key advantages over
digital circuits built from discrete component.
1. Size. Integrated circuits are much smaller-both transistors and wires are shrunk to micrometer sizes,
compared to the millimeter or centimeter scales of discrete components. Small size leads to advantages in
speed and power consumption, since smaller components have smaller parasitic resistances, capacitances, and
inductances.
2. Speed. Signals can be switched between logic 0 and logic 1 much quicker within a chip than they can
between chips. Communication within a chip can occur hundreds of times faster than communication between
chips on a printed circuit board. The high speed of circuit’s on-chip is due to their small size-smaller
components and wires have smaller parasitic capacitances to slow down the signal.
3. Power consumption. Logic operations within a chip also take much less power. Once again, lower power
consumption is largely due to the small size of circuits on the chip-smaller parasitic capacitances and
resistances require less power to drive them.
4.6 APPLICATIONS OF VLSI
Electronic systems now perform a wide variety of tasks in daily life. Electronic systems in
some cases have replaced mechanisms that operated mechanically, hydraulically, or by other means;
electronics are usually smaller, more flexible, and easier to service. In other cases electronic systems have
created totally new applications. Electronic systems perform a variety of tasks, some of them visible, some
more hidden:
1) Personal entertainment systems such as portable MP3 players and DVD players perform sophisticated
algorithms with remarkably little energy.
2) Electronic systems in cars operate stereo systems and displays; they also control fuel injection systems,
adjust suspensions to varying terrain, and perform the control functions required for anti-lock braking (ABS)
systems.

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3) Digital electronics compress and decompress video, even at high-definition data rates, on-the-fly in
consumer electronics.
4) Low-cost terminals for Web browsing still require sophisticated electronics, despite their dedicated
function.
5) Personal computers and workstations provide word-processing, financial analysis, and games. Computers
include both central processing units (CPUs) and special-purpose hardware for disk access, faster screen
display, etc.
6) Medical electronic systems measure bodily functions and perform complex processing algorithms to warn
about unusual conditions. The availability of these complex systems, far from overwhelming consumers, only
creates demand for even more complex systems.
7) Complex systems, far from overwhelming consumers, only creates demand for even more complex
systems.
8) The growing sophistication of applications continually pushes the design and manufacturing of integrated
circuits and electronic systems to new levels of complexity. And perhaps the most amazing characteristic of
this collection of systems is its variety-as systems become more complex, we build not a few general-purpose
computers but an ever wider
range of special-purpose systems. Our ability to do so is a testament to our growing mastery of both integrated
circuit manufacturing and design, but the increasing demands of customers continue to test the limits of
design and manufacturing.

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CHAPTER-5
SIMULATION TOOLS
5.1 Xilinx (ISE)
There are several EDA (Electronic Design Automation) tools available for circuit synthesis,
implementation, and simulation using VHDL. Other tools (synthesizers, for example), besides being ordered
as part of the design suites, can also be provided by specialized EDA companies (Mentor Graphics, Synopsis,
Simplicity, etc.). Examples of the latter group are Leonardo Spectrum (a synthesizer from Mentor Graphics),
Simplify (a synthesizer from Simplicity), and ModelSim (a simulator from Model Technology, a Mentor
Graphics company). The designs presented in the book were synthesized onto CPLD/FPGA devices
(appendix A) either from Altera or Xilinx.
The tools used were either ISE combined with ModelSim (for Xilinx chips—appendix B), Max Plus II
combined with Advanced Synthesis Software, or Quartus II. Leonardo Spectrum was also used occasionally.
Although different EDA tools were used to implement and test the examples presented in the design, we
decided to standardize the visual presentation of all simulation graphs. Due to its clean appearance, the
waveform editor of MaxPlus II was employed. However, newer simulators, like ISE þ ModelSim and Quartus
II, over a much broader set of features, which allow, for example, a more refined timing analysis. For tha t
reason, those tools were adopted when examining the fine details of each design.
The Xilinx Integrated Software Environment (ISE) is a powerful and complex set of tools. First, the
HDL files are synthesized. Synthesis is the process of converting behavioral HDL descriptions into a network
of logic gates. The synthesis engine takes as input the HDL design files and a library of primitives. Primitives
are not necessarily just simple logic gates like AND, OR gates and D-registers, but can also include more
complicated things such as shift registers and arithmetic units. Primitives also include specialized circuits such
as DLLs that cannot be inferred by behavioral HDL code and must be explicitly instantiated. The libraries
guide in the Xilinx documentation provides an complete description of every primitive available in the Xilinx
library. (Note that, while there are occasions when it is helpful or even necessary to explicitly instantiate
primitives, it is much better design practice to write behavioral code whenever possible.) We will be using the
Xilinx supplied synthesis engine known as XST. XST takes as input a verilog (.v) file and generates a .ngc
file. A synthesis report file (.srp) is also generated, which describes the logic inferred for each part of the HDL
file, and often includes helpful warning messages. The .ngc file is then converted to an .ngd file. (This step
mostly seems to be necessary to accommodate different design entry methods, such as third-part synthesis
tools or direct schematic entry. Whatever the design entry method, the result is an.ngd file).The .ngd file is

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essentially a net list of primitive gates, which could be implemented on any one of a number of types of
FPGA devices Xilinx manufacturers. The next step is to map the primitives onto the types of resources (logic
cells, i/o cells, etc.) available in the specific FPGA being targeted. The output of the Xilinx map tool is an .ncd
file. The design is then placed and routed, meaning that the resources described in the.ncd file are then
assigned specific locations on the FPGA, and the connections between the resources are mapped into the
FPGAs interconnect network. The delays associated with interconnect on a large FPGA can be quite
significant, so the place and route process has a large impact on the speed of the design. The place and route
engine attempts to honor timing constraints that have been added to the design, but if the constraints are too
tight, the engine will give up and generate an implementation that is functional, but not capable of operating
as fast as desired. Be careful not to assume that just because a design was successfully placed and routed, that
it will operate at the desired clock rate.
The output of the place and route engine is an updated .ncd file, which contains all the information
necessary to implement the design on the chosen FPGA. All that remains is to translate the .ncd file into a
configuration bit stream in the format recognized by the FPGA programming tools. Then the programmer is
used to download the design into the FPGA, or write the appropriate files to a compact flash card, which is
then used to configure the FPGA.
By itself, a Verilog model seldom captures all of the important attributes of a complete design. Details
such as i/o pin mappings and timing constraints can't be expressed in Verilog, but are nonetheless important
considerations when implementing the model on real hardware. The Xilinx tools allow these constraints to be
defined in several places, the two most notable being a separate "universal constraints file" (.ucf) and special
comments within the Verilog model. Xilinx has two main FPGA families: the high-performance vertex series
and the high-volume Spartan series, with a cheaper Easy Path option for ramping to volume production. It
also manufactures two CPLD lines, the Cool Runner and the 9500 series. Each model series has been released
in multiple generations since its launch.
The latest Virtex-6 and Spartan-6 FPGA families are said to consume 50 percent less power, cost 20
percent less, and have up to twice the logic capacity of previous generations of FPGAs.
5.2 DesignEntity
The basic architecture of the system is designed in this step which is coded in a Hardware description
Language like VERILOG or VHDL. A design is described in VHDL using the concept of a design module. A
design module is split into two parts, each of which is called a design unit in VERILOG. The module
declaration represents the external interface to the design module. The module internals represents the internal
description of the design module-its behavior, its structure, or a mixture of both. The BS-LFSR and Scan
Chain Ordering of S27 circuit in VHDL. It will

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5.3 BehavioralSimulation
After the design phase, create a test bench waveform containing input stimulus to verify the
functionality of the VHDL code module using a simulation software i.e. Xilinx ISE 12.3 for different inputs to
generate outputs and if it verifies then proceed further, otherwise modifications and necessary corrections will
be done in the HDL code. This is called as the behavioral simulation.
5.4 DesignSynthesis
After the correct simulations results, the design is then synthesized. During synthesis, the Xilinx ISE
tool does the following operations:
HDL Compilation: The tool compiles all the sub-modules in the main module if any and then checks the
syntax of the code written for the design.
Design Hierarchy Analysis: Analysis the hierarchy of the design.
5.5 HDL Synthesis
The process which translates VHDL or Verilog code into a device net list format, i.e. a complete
circuit with logical elements such as Multiplexer, Adder, substractor, counters, registers, flip flops Latches,
Comparators, XORs, Tristate buffers, decoders, etc. for the design. If the design contains more than one sub
designs, ex.to implement a processor, we need a CPU as one design element and RAM as another and so on,
and then the synthesis process generates net list for each design element. Synthesis process will check code
syntax and analyze the hierarchy of the design which ensures that the design is optimized for the design
architecture, the designer has selected. The resulting net list is saved to an NGC (Native Generic Circuit) file
(for Xilinx® Synthesis Technology (XST)).
5.6 Advanced HDL Synthesis
Low Level synthesis: The blocks synthesized in the HDL synthesis and the Advanced HDL synthesis
are further defined in terms of the low level blocks such as buffers, lookup tables. It also optimizes the logic
entities in the design by eliminating the redundant logic, if any. The tool then generates a „net list file (NGC
file) and then optimizes it. The final net list output file has an extension of.ngc. This NGC file contains both
the design data and the constraints. The optimization goal can be pre-specified to be the faster speed of
operation or the minimum area of implementation before running this process. The level optimization effort
can also be specified. The higher the effort, the more optimized is the design but higher effort requires larger

28. 28
CPU time (i.e. the design time) because multiple optimization algorithms are tried to get the best result for the
target architecture.
CHAPTER 6
APPLICATIONS
Figure 6.1: Track switching
1.Using the same principle as that for gate control, we have developed a concept of automatic track
switching. As train approaches the railway crossing from either side, the sensors placed at a certain distance
from the gate detects the approaching of train and the counter at second sensor will count
simultaneously and accordingly controls the operation of the gate. Also an indicator light has been provided to
alert the motorists about the approaching train.
2. Considering a situation where in an express train and a local train are traveling in opposite
directions on the same track then the sensors at either sides of the level crossing will down count at a time
which it indicates that two trains are arrival ling opposite on the same track such that the express train is
allowed to travel on the same track and the local train has to switch on to the other track; The track switching
is to be done.

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CHAPTER 7
SIMULATION RESULT

30. 30
CHAPTER 8
CONCLUSION
This work defines a automatic railway gate controller based on Verilog which is designed by following a Fsm
flow called mealy flow and simulated using Xilinx tool. In future this railway gate can be designed in backend
tools.

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CHAPTER 9
REFERENCES
1. Ramkumar, B. and Harish M Kittur,( 2012) “Low Power and Area Efficient Carry Select
Adder”,IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.
2. V.Vijayalakshmil, R.Seshadd, Dr.S.Ramakrishnan, (2013) Design and Implementation of 32
BitUnsigned Multiplier Using CLAA and CSLA 978-1-4673-5301-IEEE.
3. P. Asadi and K. Navi, "A novel highs-speed 54-54 bit multiplier",Am. J Applied Sci., vol. 4 (9), pp.
666-672. 2007.
4. W. Stallings, Computer Organization and Architecture Designing forPeljormance, 71h ed., Prentice
Hall, Pearson Education International,USA, 2006, ISBN: 0-13-185644-8.
5. F. Wakerly, Digital Design-Principles and Practices, 4th ed.,Pearson Prentice Hall, USA, 2006. ISBN:
0131733494.
6. Peter M.Nyasulu,Verilog HDL.