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# 5 digital datacomm

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### 5 digital datacomm

1. 1. Digital Data Communications Techniques Key point
2. 2. Asynchronous and Synchronous Transmission <ul><li>Timing problems require a mechanism to synchronize the transmitter and receiver </li></ul><ul><ul><li>Timing (rate, duration, spacing) must be same for transmitter and receiver. </li></ul></ul><ul><li>Two solutions </li></ul><ul><ul><li>Asynchronous </li></ul></ul><ul><ul><li>Synchronous </li></ul></ul>
3. 3. Asynchronous <ul><li>Data transmitted one character at a time </li></ul><ul><ul><li>5 to 8 bits </li></ul></ul><ul><li>Timing only needs maintaining within each character </li></ul><ul><li>Resynchronize with each character </li></ul>
4. 4. Asynchronous (diagram)
5. 5. Effect of timing error <ul><li>Assume a data rate of 10,000 bits per second (10kbps); therefore, each bit is of 0.1 millisecond (ms), or 100 us, duration. Assume that the receiver is fast by 6%, or 6 us per bit time. Thus the receiver samples the incoming character every 94 us (based on the transmitter’s clock). As can be seen, the last sample is erroneous. </li></ul>
6. 6. Asynchronous - Behavior <ul><li>In a steady stream, interval between characters is uniform (length of stop element) </li></ul><ul><li>In idle state, receiver looks for transition 1 to 0 </li></ul><ul><li>Then samples next seven intervals (char length) </li></ul><ul><li>Then looks for next 1 to 0 for next char </li></ul><ul><li>Simple </li></ul><ul><li>Cheap </li></ul>
7. 7. Synchronous - Bit Level <ul><li>Block of data transmitted without start or stop bits </li></ul><ul><li>To prevent timing drift between transmitter and receiver, their clocks must be synchronized </li></ul><ul><ul><li>Can use separate clock line between transmitter and receiver </li></ul></ul><ul><ul><ul><li>1 side eg. tramsmitter  pulses the line regularly one short pulse a time </li></ul></ul></ul><ul><ul><ul><li>Good over short distances </li></ul></ul></ul><ul><ul><ul><li>Subject to impairments (long distances) </li></ul></ul></ul><ul><ul><li>Embed clock signal in data </li></ul></ul><ul><ul><ul><li>Manchester encoding (digital signals) </li></ul></ul></ul><ul><ul><ul><li>Carrier frequency (analog) </li></ul></ul></ul><ul><ul><ul><ul><li>Synchronize receiver based on phase of carrier </li></ul></ul></ul></ul>
8. 8. Synchronous - Block Level <ul><li>Need to indicate start and end of block </li></ul><ul><li>Use preamble and postamble </li></ul><ul><li>More efficient than asynchronous </li></ul>
9. 9. Synchronous (diagram)
10. 10. Types of Error <ul><li>An error occurs when a bit is altered between transmission and reception </li></ul><ul><li>Two general types of error: </li></ul><ul><ul><li>Single bit errors </li></ul></ul><ul><ul><ul><li>One bit altered </li></ul></ul></ul><ul><ul><ul><li>Adjacent (nearby) bits not affected </li></ul></ul></ul><ul><ul><ul><li>White noise (eg) </li></ul></ul></ul><ul><ul><li>Burst errors </li></ul></ul><ul><ul><ul><li>Length B </li></ul></ul></ul><ul><ul><ul><li>Contiguous (adjacent) sequence of B bits in which first last and any number of intermediate bits in error </li></ul></ul></ul><ul><ul><ul><li>Impulse noise </li></ul></ul></ul><ul><ul><ul><li>Fading in wireless </li></ul></ul></ul><ul><ul><ul><li>Effect greater at higher data rates </li></ul></ul></ul><ul><ul><ul><ul><ul><li>(eg) </li></ul></ul></ul></ul></ul>
11. 11. Error Detection <ul><li>Additional bits added by transmitter for error detection code </li></ul><ul><li>Parity </li></ul><ul><ul><li>Value of parity bit is such that character has even (even parity) or odd (odd parity) number of ones </li></ul></ul><ul><ul><li>Even number of bit errors goes undetected </li></ul></ul><ul><ul><li>Example : odd parity </li></ul></ul><ul><ul><li>Tx = 1110001 + odd (1) = 11110001 Rx = 11110001 no error </li></ul></ul><ul><ul><li>Rx = 11100001 error </li></ul></ul>
12. 12. Cyclic Redundancy Check (CRC) <ul><li>For a block of k bits transmitter generates n bit sequence </li></ul><ul><li>Transmit k+n bits which is exactly divisible by some number </li></ul><ul><li>Receive divides frame by that number </li></ul><ul><ul><li>If no remainder, assume no error </li></ul></ul>
13. 13. CRC
14. 14. Binary Division / modulo 2 arithmetic <ul><li>At transmitter </li></ul><ul><li>String sent = data + CRC bits </li></ul><ul><li>At receiver </li></ul><ul><li>if remainder = 0  no error </li></ul><ul><li>If remainder not 0  error </li></ul>
15. 15. Error Correction <ul><li>Correction of detected errors usually requires data block to be retransmitted </li></ul><ul><li>Not appropriate for wireless applications </li></ul><ul><ul><li>Bit error rate is high </li></ul></ul><ul><ul><ul><li>Lots of retransmissions </li></ul></ul></ul><ul><ul><li>Propagation delay can be long (satellite) compared with one frame transmission time </li></ul></ul><ul><ul><ul><li>Would result in retransmission of frame in error plus many subsequent frames </li></ul></ul></ul><ul><li>Need to correct errors on basis of bits received </li></ul>
16. 16. Error correction k = message, FCS = frame check sequence,FEC=forward error correction n = total bit to be transmit (k+FCS or k + FEC)) On transmission end , each k bit block of data is mapped into an n-bit block (n> k ) called codeword, using FEC encoder, the codeword is then transmitted. Due to the impairments, which may produce bit errors in the signal, the block of data is passed through an FEC decoder with one of four possible outcome DIAGRAM
17. 17. FOUR POSSIBLE OUTCOME <ul><li>NO bit error </li></ul><ul><li>Detect and correct those errors </li></ul><ul><li>Detect but not correct errors </li></ul><ul><li>Error occur but Not detected and not correct errors </li></ul>
18. 18. Block Code Principles HAMMING DISTANCE = d( V1, V2 ) which v1 disagree v2 Rule = select lowest d(v1,v2) as original codeword example v1 = 011011 v2= 110001 , so d (v1,v2)= 3 Example For k =2 and n = 5 Data block codeword received codeword = 00100 00 00000 d(v1,v2) = 1 01 00111 d(v1,v2) = 2 10 11001 d(v1,v2)=3 11 11110 d(v1,v2)=4
19. 19. Block code principles
20. 20. ERROR CORRECTION PROCESS
21. 21. Key Point <ul><li>Synchronization </li></ul><ul><li>The receiver must know the rate at which bits are being received so that it can sample the line at appropriate intervals to determine the value of each received bit. </li></ul>