1. A
PRESENTATION
ON
VLSI DESIGN
(Industrial Training at MSME Tool Room Kolkata)

2. Presentation By:
Gokul Boro (Gau-C-10/L-321)
Bidu Bhushan Barman (Gau-C-10/L-324)
Mwnsuma Baro (Gau-C-10/L-329)
Nayan Jyoti Boro (Gau-C-10/L-334)
Tamash Khaklary (Gau-C-10/224)
Anupam Rajbongshi (Gau-C-10/260)
Dhireswar Barman (Gau-C-10/L-338)

3. Contents
1. MSME Tool Room Kolkata - A Brief Profile
2. Introduction to VLSI
3. Software used in VLSI Design
4. VLSI Design Hierarchy
5. Basic VHDL Code
6. Verilog Using Altera
7. Design using Microwind
8. Programmeable Logic Device (PLD)
9. Downloading process on PLD using XILINX
10. Conclusion

4. 1. MSME Tool Room Kolkata - A Brief Profile
It has been established under Technical Cooperation Programme between Governments of
India and Denmark.
Set up with a view to foster the growth of the
Small & Medium Enterprises (SME).
It provides invaluable technological support to
the Industry.

5. 2. Introduction to VLSI
Stands for Very Large Scale Integration.
Process of creating integrated circuits by
combining thousands of transistor-based circuits
into a single chip.
Design/Manufacturing of extremely small,
complex circuit modified semiconductor material.
Language used for designing VLSI circuit
 VHDL
 Verilog

6. Basic difference between VHDL and Verilog
VHDL
Verilog
1. Not Case Sensitive
1. Case sensitive
2. Difficult to learn
2. Easy to learn
3. Based on Pascal
3. Based on C

7. 3. Software Used in VLSI Design
 DSCH
 XILINX
 ALTERA
 MICROWIND

8. 3. Software Used in VLSI Design (Contd.)
Use of DSCH
Three types of designs:
Gate Level Design
Chip Level Design
CMOS Level Design

9. 3. Software Used in VLSI Design (Contd.)
USE OF XILINX AND ALTERA
Through VHDL and Verilog
 Data Flow
 Behavioural
 Structural

10. 3. Software Used in VLSI Design (Contd.)
USE OF MICROWIND
Microwind Software is used for layout
design of various circuits.

11. 4. VLSI Design Hierarchy
Specify what to design.
Specification
Design an Algorithm to
implement in software.
Algorithm design
Enter the design in
computer system, so that it
can be compiled by the
design software.
After completion of entry
into computer, simulate to
see the result.
Design Entry
Fundamental
simulation
Flow diagram

12. 5. Basic VHDL Code
Library declaration
Entity
Architecture
Configuration

13. 5. Basic VHDL Code (Contd.)
Library Declaration
Library Library_name;
Use library_name.package_name.package_parts;
For exampleLibrary ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;

14. 5. Basic VHDL Code (Contd.)
Entity & Port Declaration
Entity<entity_ name> is
Port (port_name:<direction><data_type>;
port_name:<direction><data_type>);
End<entity_name>;
For exampleEntity and_gate is
Port ( a, b : in std_logic;
y : out std_logic);
End and_gate;

15. 5. Basic VHDL Code (Contd.)
Architecture Declaration
Architecture< architecture_name> of <entity_name>
is
begin
.
.
.
.
.
.
.
.
end architecture_name

16. 5. Basic VHDL Code (Contd.)
Types of VHDL Architecture

Data flow
-It uses concurrent signal assignment statement.
- It describes the transfer of data from input to output
signals.
 Behavioral
- It is a high level description.
- It contains a set of assignment statement to represent behaviour.
 Structural
- Describe the circuit structure in terms of logic gates
- Interconnects wiring between logic gates to form a circuit net
list.

17. 6.Verilog using Altera:
• Dataflow:
syntax
module<module name>(port name);
input<input names>;
output<output names>;
{
program part
}
end module

18. 6.Verilog using Altera(contd.):
• Behavioral:
syntax:
module<module name>(port list);
input<input names>;
output<output names>;
Reg <output name>;
always@<input name>;
begin
{
program part
}
end
end module

19. 6.Verilog using Altera(contd.):
• Structural:
syntax:
module<module name>(port list);
input<input names>;
output<output names>;
wire <port name>;
<component name><level>(port mapping)
end module

20. 6.Verilog using Altera(contd.):
 Syntax for clock:
syntax:
module<module name>(port list);
input<input names>;
output<output names>;
Reg <output name>;
always@(posedge clk)
begin
{
program part
}
end module

21. 7.Design using Microwind
 Microwind is a windows tool for designing and
simulating
microelectronic circuits at layout
level.
 Process: diffusion, poly-sillicon, pads, deep
submicron CMOS design and n-well process.

22. 7.Design using Microwind(contd.)
Microwind Window

23. 7.Design using Microwind(contd.)
Microwind Design (For CMOS inverter)

24. 8.PROGRAMMABLE LOGIC DEVICE (PLD)
A PLD is used to build reconfiguration of
the digital circuits.
TYPES OF PLD
SIMPLE PROGRAMMABLE LOGIC DEVICE
(SPLD)
COMPLEX PROGRAMMABLE LOGIC DEVICE
(CPLD)
FIELD-PROGRAMMABLE GATE ARRAY (FPGA)

25. 9.DOWNLOADING PROCESS ON PLD USING
XILINX
Write your program.
 Then check the property of PLD.
Browse on user constraints and double
click on assign package pins.
Then give pin numbers as input and
output.
Then save it.

26. DOWNLOADING PROCESS ON PLD USING
XILINX (Contd.)
Then browse on generate programming file.
Double click on configure device.
Finish and ok.
Then select file and then open and then ok.
Right click on your Xilinx
and click on
program and then apply and then ok.

27. 10.Conclusion
 Learned the various technology, application and scope of
VLSI.
 Learned about the applications of VLSI design softwares
and programming languages .
 Downloading in PLD (Programmable Logic Device).
 Knew that there is tremendous scope and growth for those
who choose VLSI design as a career.