OVM Features Summary Prepared by: Amal Khailtash

Introduction What is OVM? SystemVerilog OOP and Classes Classes, Objects Syntax Method/Operator Overloading Abstract Classes and Polymorphism Parameterized Classes Factory Method Pattern Interfaces and Virtual Interfaces OVM Classes OVM Class Hierarchy UML Class Inheritance UML Diagrams Utility Classes Macros OVM Fundamentals OSCI TLM TLM Interfaces and Channels Ports, Exports and Implementation TLM Connections OVM Building Blocks Structure of OVM Test-Benches OVM Component Phases References and Examples Company Confidential. Distribution of this document is not permitted without written authorization.

What is OVM?

SystemVerilog OOP and Classes

Classes, Objects

Syntax

Method/Operator Overloading

Abstract Classes and Polymorphism

Parameterized Classes

Factory Method Pattern

Interfaces and Virtual Interfaces

OVM Classes

OVM Class Hierarchy

UML

Class Inheritance UML Diagrams

Utility Classes

Macros

OVM Fundamentals

OSCI TLM

TLM Interfaces and Channels

Ports, Exports and Implementation

TLM Connections

OVM Building Blocks

Structure of OVM Test-Benches

OVM Component Phases

References and Examples

SystemVerilog OOP and Classes Classes Parameterized (Similar C++ templates) Single Inheritance (extends) Encapsulate Data (Properties) and Behavior (Methods) Properties Access Restriction (local, protected, static) Can be Randomized Methods No Method Overloading in Same Class! Single Constructor (function new) No Destructor! Tasks (timed) or Functions (Untimed) Access Restrictions (local, protected, static) Static Methods Cannot be Virtual Can be Virtual (no implementation for methods) Polymorphism through Object Hierarchy and Virtual Classes/Methods Objects Classes Instances Object Handles are References (similar to Java/C++/C# references, pointers with automatic de-referencing and no delete) Company Confidential. Distribution of this document is not permitted without written authorization.

Classes

Parameterized (Similar C++ templates)

Single Inheritance (extends)

Encapsulate Data (Properties) and Behavior (Methods)

Properties

Access Restriction (local, protected, static)

Can be Randomized

Methods

No Method Overloading in Same Class!

Single Constructor (function new)

No Destructor!

Tasks (timed) or Functions (Untimed)

Access Restrictions (local, protected, static)

Static Methods Cannot be Virtual

Can be Virtual (no implementation for methods)

Polymorphism through Object Hierarchy and Virtual Classes/Methods

Objects

Classes Instances

Object Handles are References (similar to Java/C++/C# references, pointers with automatic de-referencing and no delete)

SystemVerilog OOP and Classes (continued…) Syntax Company Confidential. Distribution of this document is not permitted without written authorization. class Complex; real re; real im; function new( real r, real i ); this.re = r; this.im = i; endfunction : new function Complex add( Complex c ); Complex result; result.re = this.re+c.re; result.im = this.im+c.im; return result; endfunction : add function string toString; string s; $sformat( s, &quot;(%0.3f %s %0.3fj)&quot;, this.re, (this.im<0?&quot;-&quot;:&quot;+&quot;), (this.im<0?-this.im:this.im) ); return s; endfunction : toString endclass : Complex program test; initial begin Complex a = new(1.0,-1.0); Complex b = new(2.0,+1.0); $display( “a = %s&quot;, a.toString() ); $display( “b = %s&quot;, b.toString() ); Complex x = new(0.0,0.0); x = a.add( b ); $display( “x = %s&quot;, x.toString() ); end endprogram : test Output: # a = (1.000 - 1.000j) # b = (2.000 + 1.000j) # x = (3.000 + 0.000J) // Inheritance class SpecificComplex extends Complex; int flag; function new( real r, real i, bit f ); super.new( r, i ); this.flag = f; endfunction : new; endclass : SpecificComplex

Syntax

SystemVerilog OOP and Classes (continued…) Method Overloading Overloading is method functions and tasks with the same name, but different arguments and/or return types Method overloading is only allowed in subclasses Normal function/task overloading is not allowed!!! Overloaded methods can be virtual or non-virtual Operator Overloading Operators could be overloaded Company Confidential. Distribution of this document is not permitted without written authorization. // EBNF overload_declaration : ‘bind’ overload_operator ‘function’ data_type function_identifier ‘(‘ overload_proto_formals ‘)’ ‘;’ overload_operator : ‘+’ | ‘++’ | ‘–’ | ‘--’ | ‘*’ | ‘**’ | ‘/‘ | ‘%’ | ‘==‘ | ‘!=‘ | ‘<‘ | ‘<=‘ | ‘>’ | ‘>=‘ | ‘=‘ overload_proto_formals : data_type (‘,’ data_type)* // bind + operator to functions bind + function Complex cadd1(Complex, Complex); bind + function Complex cadd2(Complex, real); bind + function Complex cadd3(Complex, int); … … function Complex cadd1( Complex a, Complex b ); return a.add(b); endfunction cadd function Complex cadd2( Complex a, real r ); Complex b = new Complex( r, 0.0 ); return a.add(b); endfunction cadd function Complex cadd3( Complex a, int i ); Complex b = new Complex( real’(i), 0.0 ); return a.add(b); endfunction cadd

Method Overloading

Overloading is method functions and tasks with the same name, but different arguments and/or return types

Method overloading is only allowed in subclasses

Normal function/task overloading is not allowed!!!

Overloaded methods can be virtual or non-virtual

Operator Overloading

Operators could be overloaded

SystemVerilog OOP and Classes (continued…) Abstract Classes Are declared virtual Instances of abstract (virtual) classes cannot be created Are used for common, incomplete base (parent) classes (creating a template for children) Can contain method prototypes but no implementation Normal classes can have virtual methods Polymorphism To call the overridden method via a parent class object, the method needs to be declared virtual A virtual method overrides a method in all the base classes, whereas a normal method only overrides a method in that class and its descendants. If a method is declared virtual, it will be virtual throughout the class hierarchy (same prototype everywhere) Company Confidential. Distribution of this document is not permitted without written authorization. // Abstract Virtual Virtual class GenericPacket; virtual task Transmit(); // no implementation endclass : GenericPacket; class TCPPacket extends GenericPacket; // Transmit a TCP packet virtual task Transmit(); endtask : Transmit endclass : TCPPacket class UDPPacket extends GenericPacket; // Transmit a UDP Packet virtual task Transmit(); endtask : Transmit Endclass : UDPPacket GenericPacket gp; TCPPacket tp = new; // instance of TCPPacket UDPPakcet up = new; // instance of UDPPacket // ERROR: Cannot create and instance of virtual class! // gp = new; // ERROR: No implementation for Transmit in gp! // gp.Transmit(); // ERROR: Cannot assign base class object to child! // tp = gp; gp = tp; gp.Transmit(); // Sends a TCPPacket gp = up; gp.Transmit(); // Sends a UDPPacket

Abstract Classes

Are declared virtual

Instances of abstract (virtual) classes cannot be created

Are used for common, incomplete base (parent) classes (creating a template for children)

Can contain method prototypes but no implementation

Normal classes can have virtual methods

Polymorphism

To call the overridden method via a parent class object, the method needs to be declared virtual

A virtual method overrides a method in all the base classes, whereas a normal method only overrides a method in that class and its descendants.

If a method is declared virtual, it will be virtual throughout the class hierarchy (same prototype everywhere)

SystemVerilog OOP and Classes (continued…) Parameterized Classes Company Confidential. Distribution of this document is not permitted without written authorization. class stack #(type T = int); local T items[$]; task push( T a ); items.push_front(a); endtask : push task pop( ref T a ); a = items.pop_front(); endtask : pop endclass : stack program test; initial begin stack #(int) is = new; stack #(real) rs = new; for( int i=0; i<10; i++ ) begin $display( &quot;Pushed -> %0d : %0.3f&quot;, i, i*3.14 ); is.push( i ); rs.push( i*3.14 ); end $display( &quot;--------------------&quot; ); for( int i=0; i<10; i++ ) begin int x; real y; is.pop(x); rs.pop(y); $display( &quot;Popped -> %0d : %0.3f&quot;, x, y ); end end endprogram : test # Pushed -> 0 : 0.000 # Pushed -> 1 : 3.140 # Pushed -> 2 : 6.280 # Pushed -> 3 : 9.420 # Pushed -> 4 : 12.560 # Pushed -> 5 : 15.700 # Pushed -> 6 : 18.840 # Pushed -> 7 : 21.980 # Pushed -> 8 : 25.120 # Pushed -> 9 : 28.260 # -------------------- # Popped -> 9 : 28.260 # Popped -> 8 : 25.120 # Popped -> 7 : 21.980 # Popped -> 6 : 18.840 # Popped -> 5 : 15.700 # Popped -> 4 : 12.560 # Popped -> 3 : 9.420 # Popped -> 2 : 6.280 # Popped -> 1 : 3.140 # Popped -> 0 : 0.000

Parameterized Classes

SystemVerilog OOP and Classes (continued…) Factory Method Pattern An OOP Design pattern Deals with Creation of Objects (allow subclasses to choose which type of object to create) Type Overrides Instance Overrides virtual class shape; function new(); $display( “Cannot instantiate shape!” ); endfucntion : new virtual function area(); endfunction : area endclass shape; class square extends shape; real side; function new(real s); this.side=s; endfunction : new virtual function real area(); return side*side; endfucntion : area endclass : square class circle extends shape; real radius; function new(real r); this.radius=r; endfunction : new virtual function real area(); return 3.1415*radius*radius; endfucntion : area endclass : circle class factory; static function create_shape( string shape_name. real param ); case( shape_name ) “ circle” : begin circle sh; sh=new(param); return sh; end “ square” : begin squere sh; sh=new(param); return sh; end endcase endfunction : create_shape endclass : factory program top initial begin shape a = factory::create_shape(“square”, 10.0); shape b = factory::create_shape(“circle”, 10.0); $display( a.area() ); $display( b.area() ); end endprogram : top

Factory Method Pattern

An OOP Design pattern

Deals with Creation of Objects (allow subclasses to choose which type of object to create)

Type Overrides

Instance Overrides

SystemVerilog OOP and Classes (continued…) Interfaces Interfaces are like bundle of wires Individual elements can have directions (modport) Can include tasks and functions (BFM style) Can include assertions, cover and covergroups Virtual Interfaces Think of a virtual interface as a handle to a concrete interface (object). Similar to a class handle and the object referenced by that handle. One needs to assign an interface to a virtual interface somehow to be able to access that interface signals/tasks/functions, … In OVM, virtual interfaces are used inside Drivers/Monitors/… to connect to DUV’s interface Company Confidential. Distribution of this document is not permitted without written authorization. interface my_interface; … endinterface my_interface if; virtual my_interface vif; // if.??? works fine, but vif.??? does not work yet, unless you do: vif = if; // then you can access the members: vif.???

Interfaces

Interfaces are like bundle of wires

Individual elements can have directions (modport)

Can include tasks and functions (BFM style)

Can include assertions, cover and covergroups

Virtual Interfaces

Think of a virtual interface as a handle to a concrete interface (object). Similar to a class handle and the object referenced by that handle.

One needs to assign an interface to a virtual interface somehow to be able to access that interface signals/tasks/functions, …

In OVM, virtual interfaces are used inside Drivers/Monitors/… to connect to DUV’s interface

interface my_interface; … endinterface

my_interface if;

virtual my_interface vif;

// if.??? works fine, but vif.??? does not work yet, unless you do:

vif = if;

// then you can access the members: vif.???

What is OVM? Open Verification Methodology v1.0, v1.1, v2.0 Library of SystemVerilog OOP Classes Implements OOP Factory methodology Provides Base Classes for Various Components Components are Polymorphic Components Provide Various Interfaces: Hierarchy (Creation, Management, and Inspection) Configuration of Component Topology and Properties Phasing: Phased Build for Components (including the Environment, the Test) Factory: Component/Object Warehouse Type Overrides Instance Overrides Reporting: Unified Reporting and Messaging Transaction Recording (Transaction Database) Includes OSCI (Open System C Initiative) TLM (Transaction Level Modeling) v2.0 Uniform Connectivity of Components Defines Interfaces, Ports and Channels Company Confidential. Distribution of this document is not permitted without written authorization.

Open Verification Methodology

v1.0, v1.1, v2.0

Library of SystemVerilog OOP Classes

Implements OOP Factory methodology

Provides Base Classes for Various Components

Components are Polymorphic

Components Provide Various Interfaces:

Hierarchy (Creation, Management, and Inspection)

Configuration of Component Topology and Properties

Phasing: Phased Build for Components (including the Environment, the Test)

Factory: Component/Object Warehouse

Type Overrides

Instance Overrides

Reporting: Unified Reporting and Messaging

Transaction Recording (Transaction Database)

Includes OSCI (Open System C Initiative) TLM (Transaction Level Modeling) v2.0

Uniform Connectivity of Components

Defines Interfaces, Ports and Channels

OVM Classes (continued…) Most Classes Inherit Directly or Indirectly from ovm_void Allows Polymorphism for Most Objects Class Categories Base Component Hierarchy Reporting Factory Synchronization Policies Policy Knobs TLM Interfaces Ports and Exports Built-In TLM Channels Components Sequences Comparators Macros Utility Classes Company Confidential. Distribution of this document is not permitted without written authorization.

Most Classes Inherit Directly or Indirectly from ovm_void

Allows Polymorphism for Most Objects

Class Categories

Base

Component Hierarchy

Reporting

Factory

Synchronization

Policies

Policy Knobs

TLM Interfaces

Ports and Exports

Built-In TLM Channels

Components

Sequences

Comparators

Macros

Utility Classes

OVM Class Hierarchy UML Used to represent a system’s model graphically Structure Diagram (Class, Component, …) Behavior Diagram (Activity, State, Use Case) Interaction Diagram (Communication, Sequence, Timing, …) Used for representing OOP class relationship/hierarchy Company Confidential. Distribution of this document is not permitted without written authorization. Association Composition Aggregation Dependence Generalization (Inheritance) Association

UML

Used to represent a system’s model graphically

Structure Diagram (Class, Component, …)

Behavior Diagram (Activity, State, Use Case)

Interaction Diagram (Communication, Sequence, Timing, …)

Used for representing OOP class relationship/hierarchy

OVM Class Hierarchy (continued…) Company Confidential. Distribution of this document is not permitted without written authorization.

OVM Class Hierarchy (continued…) Base ovm_void ovm_object ovm_transaction Company Confidential. Distribution of this document is not permitted without written authorization.

Base

ovm_void

ovm_object

ovm_transaction

OVM Class Hierarchy (continued…) Component Hierarchy ovm_component ovm_phase ovm_root Company Confidential. Distribution of this document is not permitted without written authorization.

Component Hierarchy

ovm_component

ovm_phase

ovm_root

OVM Class Hierarchy (continued…) Reporting ovm_report_object ovm_reporter ovm_report_handler ovm_report_server Company Confidential. Distribution of this document is not permitted without written authorization.

Reporting

ovm_report_object

ovm_reporter

ovm_report_handler

ovm_report_server

OVM Class Hierarchy (continued…) Factory ovm_object_wrapper ovm_component_registry ovm_object_registry ovm_factory Company Confidential. Distribution of this document is not permitted without written authorization.

Factory

ovm_object_wrapper

ovm_component_registry

ovm_object_registry

ovm_factory

OVM Class Hierarchy (continued…) Synchronization ovm_event ovm_event_pool ovm_event_callback ovm_barrier ovm_barrier_pool Company Confidential. Distribution of this document is not permitted without written authorization.

Synchronization

ovm_event

ovm_event_pool

ovm_event_callback

ovm_barrier

ovm_barrier_pool

OVM Class Hierarchy (continued…) Policies ovm_comparer ovm_packer ovm_recorder ovm_printer Policy Knobs ovm_printer_knobs Company Confidential. Distribution of this document is not permitted without written authorization.

Policies

ovm_comparer

ovm_packer

ovm_recorder

ovm_printer

Policy Knobs

ovm_printer_knobs

OVM Class Hierarchy (continued…) TLM Interfaces tlm_if_base #( type T1=int, type T2=int ) Ports and Exports ovm_port_base #( type IF=ovm_object ) ovm_ uni-if _port #( type T=int ) ovm_ uni-if _export #(type T=int ) ovm_ uni-if _imp #(type T=int, type IMP=int ) ovm_ bi-if _port #( type REQ=int , type RSP=int ) ovm_ bi-if _export #(type REQ=int , type RSP=int) ovm_ bi-if _imp #(type REQ=int , type RSP=int, type IMP=int ) sqr_if_base #( type REQ=ovm_object, type RSP=REQ ) ovm_seq_item_pull_ port_type #( type REQ=int, type RSP=REQ ) ovm_seq_item_pull_ export_type #(type REQ=int, type RSP=REQ ) ovm_seq_item_pull_ imp_type #(type REQ=int, type RSP=REQ ) Built-In TLM Channels tlm_fifo #( type T=int ) tlm_analysis_fifo #( type T=int ) tlm_req_rsp_channel #( type REQ=int , type RSP=int ) tlm_transport_channel #( type REQ=int , type RSP=int ) Company Confidential. Distribution of this document is not permitted without written authorization.

TLM Interfaces

tlm_if_base #( type T1=int, type T2=int )

Ports and Exports

ovm_port_base #( type IF=ovm_object )

ovm_ uni-if _port #( type T=int )

ovm_ uni-if _export #(type T=int )

ovm_ uni-if _imp #(type T=int, type IMP=int )

ovm_ bi-if _port #( type REQ=int , type RSP=int )

ovm_ bi-if _export #(type REQ=int , type RSP=int)

ovm_ bi-if _imp #(type REQ=int , type RSP=int, type IMP=int )

sqr_if_base #( type REQ=ovm_object, type RSP=REQ )

ovm_seq_item_pull_ port_type #( type REQ=int, type RSP=REQ )

ovm_seq_item_pull_ export_type #(type REQ=int, type RSP=REQ )

ovm_seq_item_pull_ imp_type #(type REQ=int, type RSP=REQ )

Built-In TLM Channels

tlm_fifo #( type T=int )

tlm_analysis_fifo #( type T=int )

tlm_req_rsp_channel #( type REQ=int , type RSP=int )

tlm_transport_channel #( type REQ=int , type RSP=int )

OVM Class Hierarchy (continued…) TLM Interface TLM Ports/Exports TLM Built-In Channels Company Confidential. Distribution of this document is not permitted without written authorization.

TLM Interface

TLM Ports/Exports

TLM Built-In Channels

OVM Class Hierarchy (continued…) Components ovm_component ovm_test ovm_env ovm_agent (sequencer, driver, monitor) ovm_driver / ovm_push_driver omv_monitor ovm_subscriber ovm_scoreboard ovm_sequencer / ovm_virtual_sequencer ovm_random_stimulus Company Confidential. Distribution of this document is not permitted without written authorization.

Components

ovm_component

ovm_test

ovm_env

ovm_agent (sequencer, driver, monitor)

ovm_driver / ovm_push_driver

omv_monitor

ovm_subscriber

ovm_scoreboard

ovm_sequencer / ovm_virtual_sequencer

ovm_random_stimulus

OVM Class Hierarchy (continued…) Components Company Confidential. Distribution of this document is not permitted without written authorization.

Components

OVM Class Hierarchy (continued…) Sequences Company Confidential. Distribution of this document is not permitted without written authorization.

Sequences

OVM Class Hierarchy (continued…) Comparators ovm_in_order_comparator #(T, comp, convert, pair_type) ovm_in_order_built_in_comparator #(T) ovm_in_order_class_comparator #(T) ovm_algorithmic_comparator #(BEFORE,AFTER,TRANSFORMER) Company Confidential. Distribution of this document is not permitted without written authorization.

Comparators

ovm_in_order_comparator #(T, comp, convert, pair_type)

ovm_in_order_built_in_comparator #(T)

ovm_in_order_class_comparator #(T)

ovm_algorithmic_comparator #(BEFORE,AFTER,TRANSFORMER)

OVM Class Hierarchy (continued…) Utility Classes ovm_built_in_clone #(T) ovm_built_in_comp #(T) ovm_built_in_converter #(T) ovm_built_in_pair #(T1,T2) ovm_class_clone #(T) ovm_class_comp #(T) ovm_class_converter #(T) ovm_class_pair #(T1,T2) Company Confidential. Distribution of this document is not permitted without written authorization.

Utility Classes

ovm_built_in_clone #(T)

ovm_built_in_comp #(T)

ovm_built_in_converter #(T)

ovm_built_in_pair #(T1,T2)

ovm_class_clone #(T)

ovm_class_comp #(T)

ovm_class_converter #(T)

ovm_class_pair #(T1,T2)

OVM Class Hierarchy (continued…) Macros OVM Macros Make Concise Readable Code Easy Factory Registration Provide Common Methods for Various Elements create, get_type, get_type_name, copy , compare , pack , unpack , record , print , sprint, … Company Confidential. Distribution of this document is not permitted without written authorization.

Macros

OVM Macros Make Concise Readable Code

Easy Factory Registration

Provide Common Methods for Various Elements

create, get_type, get_type_name, copy , compare , pack , unpack , record , print , sprint, …

OVM Fundamentals OSCI TLM TLM Interfaces and Channels Ports, Exports and Implementation TLM Connections OVM Building Blocks Structure of OVM Test-Benches OVM Component Phases Examples

OSCI TLM

TLM Interfaces and Channels

Ports, Exports and Implementation

TLM Connections

OVM Building Blocks

Structure of OVM Test-Benches

OVM Component Phases

Examples

OSCI TLM Defines Semantics/Behaviors for Communicating Transactions between Components Provides Transfer of Transactions through Standard Interfaces Ports: Specify API Exports: Provide Implementation Imp: Provides the Implementations of the Methods in tlm_if_base to Ports and Exports that Require It. (Simulates Multiple Inheritance) Company Confidential. Distribution of this document is not permitted without written authorization.

Defines Semantics/Behaviors for Communicating Transactions between Components

Provides Transfer of Transactions through Standard Interfaces

Ports: Specify API

Exports: Provide Implementation

Imp: Provides the Implementations of the Methods in tlm_if_base to Ports and Exports that Require It. (Simulates Multiple Inheritance)

OSCI TLM (continued…) Uni-Directional Interfaces put, get, peek, get_peek, analysis Bi-Directional Interfaces master, slave, transport Channels tlm_fifo, tlm_analysis_fifo tlm_req_rsp_channel, tlm_transport_channel Company Confidential. Distribution of this document is not permitted without written authorization.

Uni-Directional Interfaces

put, get, peek, get_peek, analysis

Bi-Directional Interfaces

master, slave, transport

Channels

tlm_fifo, tlm_analysis_fifo

tlm_req_rsp_channel, tlm_transport_channel

OSCI TLM (continued…) Uni-Directional Interfaces class ovm_ uni-if _port #( type T = int ) class ovm_ uni-if _export #( type T = int ) class ovm_ uni-if _imp #( type T = int ) Company Confidential. Distribution of this document is not permitted without written authorization. uni-if blocking_put put(T) nonblocking_put try_put(T), can_put() put put(T), try_put(T), can_put() blocking_get get(T) nonblocking_get try_get(T), can_get() get get(T), try_get(T), can_get() blocking_peek peek(T) nonblocking_peek try_peek(T), can_peek() peek peek(T), try_peek(T), can_peek() blocking_get_peek get(T) peek(T) nonblocking_get_peek try_peek(T), can_peek() try_get(T), can_get() get_peek get(T), try_get(T), can_get() peek(T). try_peek(T), can_peek() analysis write(T)

Uni-Directional Interfaces

class ovm_ uni-if _port #( type T = int )

class ovm_ uni-if _export #( type T = int )

class ovm_ uni-if _imp #( type T = int )

OSCI TLM (continued…) Bi-Directional Interfaces class ovm_ bi-if _port #( type T = int ) class ovm_ bi-if _export #( type T = int ) class ovm_ bi-if _imp #( type T = int ) Company Confidential. Distribution of this document is not permitted without written authorization. bi-if blocking_master put(REQ) get(RSP) peek(RSP) nonblocking_master try_put(REQ), can_put() try_get(RSP), can_get() try_peek(RSP), can_peek() master put(REQ), try_put(REQ), can_put() get(RSP), try_get(RSP), can_get() peek(RSP), try_peek(RSP), can_peek() blocking_slave get(REQ) peek(REQ) put(RSP) nonblocking_slave try_get(REQ), can_get() try_peek(REQ), can_peek() try_put(RSP), can_put() slave get(REQ), try_get(REQ), can_get() peek(REQ), try_peek(REQ), can_peek() put(RSP), try_put(RSP), can_put() blocking_transport transport(REQ,RSP) nonblocking_transport nb_transport(REQ,RSP) transport transport(REQ,RSP) nb_transport(REQ,RSP)

Bi-Directional Interfaces

class ovm_ bi-if _port #( type T = int )

class ovm_ bi-if _export #( type T = int )

class ovm_ bi-if _imp #( type T = int )

Ports, Exports and Implementation Port / Analysis Port Inside initiator component to provide access to predefined method of transaction interface Export / Analysis Export Route transaction to other layers Implementation (IMP) Inside target component to provide implementation of predefined method of transaction interface Company Confidential. Distribution of this document is not permitted without written authorization. port analysis port port export implementation export

Port / Analysis Port

Inside initiator component to provide access to predefined method of transaction interface

Export / Analysis Export

Route transaction to other layers

Implementation (IMP)

Inside target component to provide implementation of predefined method of transaction interface

Ports, Exports and Implementation (continued…) Port / Export / Imp Connection Port -> Export (Imp) c1.port.connect( c2.export ) Port -> Port (going up the hierarchy) sub_c1.port.connect( port ) Export -> Export (going down the hierarchy) export.connect( sub_c2.export ) Company Confidential. Distribution of this document is not permitted without written authorization. put_export get_peek_export port export port imp get_port put_port tlm_fifo export port export put port put export put imp get_peek imp get_peek export get port put port I T T I I T T I a b c X y d e X.build() a.put_port.connect( b.put_export ); // p->e c.get_port.connect( b.get_peek_export); // p->e C.put_port.connect( x.port ); // p->p Y.build() y.export.connect( d.put_export ); // e->e e.get_port.connect( d.get_peek_export ); // p->e top.build() X.port.connect( y.export ); // p->e tlm_fifo

Port / Export / Imp Connection

Port -> Export (Imp)

c1.port.connect( c2.export )

Port -> Port (going up the hierarchy)

sub_c1.port.connect( port )

Export -> Export (going down the hierarchy)

export.connect( sub_c2.export )

X.build()

a.put_port.connect( b.put_export ); // p->e

c.get_port.connect( b.get_peek_export); // p->e

C.put_port.connect( x.port ); // p->p

Y.build()

y.export.connect( d.put_export ); // e->e

e.get_port.connect( d.get_peek_export ); // p->e

top.build()

X.port.connect( y.export ); // p->e

OVM Building Blocks ovm_transaction Encapsulation of data, unit of transaction (bus read/write, packet, block of data, …) Can be randomized and constrained Used to transfer information at various points in the environment ovm_sequence_item Inherits from ovm_transaction Adds a property (m_sequnce_id) other than the inherited one (m_transaction_id) to route responses to the original sequence Sequencers and Drivers use this ovm_driver / ovm_push_driver Embeds one (or more) SystemVerilog Interface(s) Gets transactions from a sequencer or other components Drives pins at DUV (using the interface) and based on the transaction received Company Confidential. Distribution of this document is not permitted without written authorization.

ovm_transaction

Encapsulation of data, unit of transaction (bus read/write, packet, block of data, …)

Can be randomized and constrained

Used to transfer information at various points in the environment

ovm_sequence_item

Inherits from ovm_transaction

Adds a property (m_sequnce_id) other than the inherited one (m_transaction_id) to route responses to the original sequence

Sequencers and Drivers use this

ovm_driver / ovm_push_driver

Embeds one (or more) SystemVerilog Interface(s)

Gets transactions from a sequencer or other components

Drives pins at DUV (using the interface) and based on the transaction received

OVM Building Blocks (continued…) ovm_monitor Embeds one (or more) SystemVerilog Interface(s) Monitors pins at DUV (using the interface) Checks for timing at pin level Creates a transaction based on pin wiggles, and sends it to other components (scoreboard, coverage collectors, …) Checks status information and events Can include coverage and protocol checkers ovm_sequencer Provides a sequence (ovm_sequence) of data (ovm_sequence_item) to the driver Data items can be randomized and are ordered Can be hierarchical and allows synchronization Company Confidential. Distribution of this document is not permitted without written authorization.

ovm_monitor

Embeds one (or more) SystemVerilog Interface(s)

Monitors pins at DUV (using the interface)

Checks for timing at pin level

Creates a transaction based on pin wiggles, and sends it to other components (scoreboard, coverage collectors, …)

Checks status information and events

Can include coverage and protocol checkers

ovm_sequencer

Provides a sequence (ovm_sequence) of data (ovm_sequence_item) to the driver

Data items can be randomized and are ordered

Can be hierarchical and allows synchronization

OVM Building Blocks (continued…) ovm_agent Encapsulates Sequencer, Driver, and Monitor Has an active mode and a passive mode (is_active) In passive mode, Sequencer and Driver are disabled Has configuration data to configure its components Company Confidential. Distribution of this document is not permitted without written authorization. agent DUV IF VIF config VIF analysis sequencer driver monitor

ovm_agent

Encapsulates Sequencer, Driver, and Monitor

Has an active mode and a passive mode (is_active)

In passive mode, Sequencer and Driver are disabled

Has configuration data to configure its components

OVM Building Blocks (continued…) ovm_subscriber (scoreboards, coverage collectors) Is a template for classes that have an analysis export that connect to analysis ports for collecting information (coverage, …) ovm_env An environment encapsulates a number of Agents, Drivers, Monitors, Scoreboards, … Has properties to customize its components’ topology and behavior Environments can be hierarchical and contain other environments Topmost environment could be considered a the test-bench for a number of interfaces Company Confidential. Distribution of this document is not permitted without written authorization.

ovm_subscriber (scoreboards, coverage collectors)

Is a template for classes that have an analysis export that connect to analysis ports for collecting information (coverage, …)

ovm_env

An environment encapsulates a number of Agents, Drivers, Monitors, Scoreboards, …

Has properties to customize its components’ topology and behavior

Environments can be hierarchical and contain other environments

Topmost environment could be considered a the test-bench for a number of interfaces

Structure of OVM Test-Benches ovm_test Individual test-cases inherit from this class Each test-case instantiates environments and configures them (topological changes or configuration changes) Test-Bench The top-level test-bench instantiates interfaces that connect to DUV. Instantiates DUV Calls run_test() (or run_test(“name”)) +OVM_TESTNAME=? select which ovm_test class to instantiate and run run_test() is a method in ovm_root that is automatically instantiated Company Confidential. Distribution of this document is not permitted without written authorization. Top test2 test1 DUV Clock/Reset IF IF IF VIF env1 VIF VIF env2 agent1 agent2 agent3

ovm_test

Individual test-cases inherit from this class

Each test-case instantiates environments and configures them (topological changes or configuration changes)

Test-Bench

The top-level test-bench instantiates interfaces that connect to DUV.

Instantiates DUV

Calls run_test() (or run_test(“name”))

+OVM_TESTNAME=? select which ovm_test class to instantiate and run

run_test() is a method in ovm_root that is automatically instantiated

OVM Component Phases A set of callback methods available to all components Used for synchronization in the environment Any subclass of ovm_component can implement any of these callbacks Child component instantiations is done in build phase Connect is used to connect child components Main functionality is placed in run phase Report simulation results. function report Check simulation results. function check Collect information from run phase. function extract This is where the main guts of a component functionality resides. It can consume time and can spawn other processes. Stops when global_stop_request is called. task run Called before start of simulation. Can be used for printing banners, initializing memories, … function start_of_simulation Final configuration, topology, connection and integrity checks function end_of_elaboration Used for connecting ports, exports and implementations function connect Used for creation of components and component hierarchies function build Descripton Type Phase

A set of callback methods available to all components

Used for synchronization in the environment

Any subclass of ovm_component can implement any of these callbacks

Child component instantiations is done in build phase

Connect is used to connect child components

Main functionality is placed in run phase

References and Examples OVMWorld OVM v2.0.0 Documentation Doulous : Getting Started with OVM http://www.doulos.com/knowhow/sysverilog/ovm/ Tutorial 0 - OVM Verification Primer Tutorial 1 - A First Example Tutorial 2 - Configurations and Sequences Mentor Graphics Mentor Verification Methodology Getting Started with the OVM 2.0: AVM Backward Compatibility and Migration Overview of Sequence Based Stimulus Generation in OVM 2.0 OVM v2.0 Examples Company Confidential. Distribution of this document is not permitted without written authorization.

OVMWorld

OVM v2.0.0 Documentation

Doulous : Getting Started with OVM

http://www.doulos.com/knowhow/sysverilog/ovm/

Tutorial 0 - OVM Verification Primer

Tutorial 1 - A First Example

Tutorial 2 - Configurations and Sequences

Mentor Graphics

Mentor Verification Methodology

Getting Started with the OVM 2.0: AVM Backward Compatibility and Migration

Overview of Sequence Based Stimulus Generation in OVM 2.0

OVM v2.0 Examples

References and Examples (continued…) Doulos Getting Started with OVM my_test my_env seq_item_export seq_item_port dut_if vif dut my_sequencer my_driver

Doulos Getting Started with OVM