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Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
Design considerations
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Design considerations

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The following presentation is a part of the level 4 module -- Digital Logic and Signal Principles. This resources is a part of the 2009/2010 Engineering (foundation degree, BEng and HN) courses from …

The following presentation is a part of the level 4 module -- Digital Logic and Signal Principles. This resources is a part of the 2009/2010 Engineering (foundation degree, BEng and HN) courses from University of Wales Newport (course codes H101, H691, H620, HH37 and 001H). This resource is a part of the core modules for the full time 1st year undergraduate programme.
The BEng & Foundation Degrees and HNC/D in Engineering are designed to meet the needs of employers by placing the emphasis on the theoretical, practical and vocational aspects of engineering within the workplace and beyond. Engineering is becoming more high profile, and therefore more in demand as a skill set, in today’s high-tech world. This course has been designed to provide you with knowledge, skills and practical experience encountered in everyday engineering environments.

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  • 1. Design Considerations Digital Logic and Software Applications Level 4 © University of Wales Newport 2009 This work is licensed under a Creative Commons Attribution 2.0 License .
  • 2. <ul><li>The following presentation is a part of the level 4 module -- Digital Logic and Signal Principles. This resources is a part of the 2009/2010 Engineering (foundation degree, BEng and HN) courses from University of Wales Newport (course codes H101, H691, H620, HH37 and 001H). This resource is a part of the core modules for the full time 1 st year undergraduate programme. </li></ul><ul><li>The BEng & Foundation Degrees and HNC/D in Engineering are designed to meet the needs of employers by placing the emphasis on the theoretical, practical and vocational aspects of engineering within the workplace and beyond. Engineering is becoming more high profile, and therefore more in demand as a skill set, in today’s high-tech world. This course has been designed to provide you with knowledge, skills and practical experience encountered in everyday engineering environments. </li></ul><ul><li>Contents </li></ul><ul><li>Hazards </li></ul><ul><li>Static Hazards </li></ul><ul><li>Dynamic Hazards </li></ul><ul><li>Function Hazards </li></ul><ul><li>The simplest example of this is the exclusive-OR function </li></ul><ul><li>Don’t Care </li></ul><ul><li>Example </li></ul><ul><li>Credits </li></ul><ul><li>In addition to the resource below, there are supporting documents which should be used in combination with this resource. Please see: </li></ul><ul><li>Holdsworth B, Digital Logic Design, Newnes 2002 </li></ul><ul><li>Crisp J, Introduction to Digital Systems, Newnes 2001 </li></ul>Stabilised Power Supplies
  • 3. Hazards <ul><li>What are Hazards ? </li></ul><ul><li>Hazards are changes in the output when changes should not logically occur. There are three types of hazard which can occur. </li></ul><ul><li>Static Hazards </li></ul><ul><li>Dynamic Hazards </li></ul><ul><li>Function Hazards </li></ul>Design Considerations
  • 4. Static Hazards <ul><li>A static hazard is the situation where, when one input variable changes, the output changes momentarily before stabilizing to the correct value. There are two types of static hazards: </li></ul><ul><li>Static-1 Hazard: the output is currently 1 and after the inputs change, the output momentarily changes to 0 before settling on 1 </li></ul><ul><li>Static-0 Hazard: the output is currently 0 and after the inputs change, the output momentarily changes to 1 before settling on 0 </li></ul><ul><li>* The above text is taken from http://en.wikipedia.org/wiki/Hazard_(logic) and is available under the Creative Commons Attribution-ShareAlike License . </li></ul>Design Considerations
  • 5. Static Hazards <ul><li>In properly formed two-level AND-OR logic based on a Sum Of Products expression, there will be no static-0 hazards. Conversely, there will be no static-1 hazards in an OR-AND implementation of a Product Of Sums expression. </li></ul><ul><li>The most commonly used method to eliminate static hazards is to add redundant logic (consensus terms in the logic expression). </li></ul><ul><li>  </li></ul><ul><li>* The above text is taken from http://en.wikipedia.org/wiki/Hazard_(logic) and is available under the Creative Commons Attribution-ShareAlike License . </li></ul>Design Considerations
  • 6. A B C D Y 1 2 3 4 5 This particular type of hazard is usually due to a NOT gate within the logic. We can see the effects of the delay in the circuit. Design Considerations Static-1 Hazard:
  • 7. <ul><li>What is the equation for the circuit? </li></ul><ul><li>What is the output when the inputs equal: </li></ul><ul><li>A = 1 B = 1 C = 1 D = 1 </li></ul><ul><li>What is the output when the inputs equal: </li></ul><ul><li>A = 1 B = 1 C = 0 D = 1 </li></ul><ul><li>What happens as C changes from 1 to 0? </li></ul>Design Considerations
  • 8. INPUT C AND 3 O/P NOT 5 O/P AND 2 O/P OR O/P Design Considerations
  • 9. INPUT C AND 3 O/P NOT 5 O/P AND 2 O/P OR O/P Design Considerations
  • 10. INPUT C AND 3 O/P NOT 5 O/P AND 2 O/P OR O/P Design Considerations
  • 11. INPUT C AND 3 O/P NOT 5 O/P AND 2 O/P OR O/P Design Considerations
  • 12. INPUT C AND 3 O/P NOT 5 O/P AND 2 O/P OR O/P GLITCH Design Considerations
  • 13. <ul><li>The hazard can be dealt with in two ways: </li></ul><ul><li>Either match the delay causing the hazard with another delay by adding a buffer gate which delays a path without changing the state. </li></ul><ul><li>Ensure that the hazard does not change the output by forcing the output to stay on using and additional function which is not effected by the input state. </li></ul><ul><li>The first option is often the simplest and therefore is most often implemented but it can lead to problems as delays can never be absolutely matched. </li></ul><ul><li>'Huffman' discovered that a hazard can be removed by: </li></ul><ul><li>“ The insertion of a redundant loop can eliminate a static hazard.” </li></ul>Design Considerations
  • 14. <ul><li>The glitch is due to gates delays and should not happen logically. </li></ul>Does it occur as C changes from 0 to 1? No – as gate 3 turns on before gate 2 turns off. How do we recognise where hazards occur? Look at the Karnaugh Map. HAZARDS 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 0 0 0 1 1 C D B   Y   1 1 0 0 A Design Considerations
  • 15. <ul><li>A hazard will occur where we have two groups that are next to each other vertically or horizontally which do not overlap. </li></ul>1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 0 0 0 1 1 C D B   Y   1 1 0 0 A What we do is to add redundant groups to “cover” the change that produces the hazard. The solution requires two more three-input AND gates and a six-input OR rather than a four-input – but the solution is “hazard-free”. Design Considerations
  • 16. Dynamic Hazards <ul><li>A dynamic hazard is the possibility of an output changing more than once as a result of a single input change. Dynamic hazards often occur in larger logic circuits where there are different routes to the output (from the input). If each route has a different delay, then it quickly becomes clear that there is the potential for changing output values that differ from the required / expected output. e.g. A logic circuit is meant to change output state from 1 to 0 , but instead changes from 1 to 0 then 1 and finally rests at the correct value 0 . This is a dynamic hazard. </li></ul><ul><li>* The above text is taken from http://en.wikipedia.org/wiki/Hazard_(logic) and is available under the Creative Commons Attribution-ShareAlike License . </li></ul>Design Considerations
  • 17. Dynamic Hazards <ul><li>As a rule, dynamic hazards are more complex to resolve, but note that if all static hazards have been eliminated from a circuit, then dynamic hazards cannot occur. </li></ul><ul><li>* The above text is taken from http://en.wikipedia.org/wiki/Hazard_(logic) and is available under the Creative Commons Attribution-ShareAlike License . </li></ul><ul><li>e.g. A given logic circuit has been design to change output state from ‘0' to ‘1‘ when a certain chane in input occurs, but instead changes from ‘0' to ‘1' then back to ‘0‘ before finally coming to rest at the correct value ‘1'. This is a dynamic hazard. </li></ul>Design Considerations
  • 18. <ul><li>As we shall see, dynamic hazards require a more complex method to resolve (we shall not cover in detail). </li></ul>Consider all inputs at logic 0 then B changes to logic 1 Design Considerations A C B 1 2 3 4 5 6 7
  • 19. 0 0 0 0 1 0 1 1 1 1 Design Considerations A C B 1 2 3 4 5 6 7
  • 20. 00 01 00 00 11 00 11 11 11 11 Design Considerations A C B 1 2 3 4 5 6 7
  • 21. 000 011 000 001 110 000 111 111 111 111 Design Considerations A C B 1 2 3 4 5 6 7
  • 22. 0000 0111 0000 0011 1100 0001 1110 1111 1111 1110 Design Considerations A C B 1 2 3 4 5 6 7
  • 23. 00000 01111 00000 00111 11000 00010 11100 11111 11111 11100 Design Considerations A C B 1 2 3 4 5 6 7
  • 24. 000000 011111 000000 001111 110000 000100 111000 111110 111111 111000 Design Considerations A C B 1 2 3 4 5 6 7
  • 25. <ul><li>What can be seen is that when B changes from 0 to 1 there is a sequence of changes within the gates which leads to the output changing from 1 to 0 – which is correct. </li></ul><ul><li>At one point gates 2 and 7 change simultaneously – </li></ul><ul><li>Gate 2 goes from 0 to 1 </li></ul><ul><li>Gate 7 goes from 1 to 0 </li></ul><ul><li>Which keeps the output at 1 </li></ul>Design Considerations
  • 26. 0000 0111 0000 0011 1100 0001 1110 1111 1111 1110 Design Considerations A C B 1 2 3 4 5 6 7
  • 27. <ul><li>If the AND gate 7 changed just before the AND gate 2 then the OR gate 5 would see two 0’s on its input driving its output low before gate 2 turned on. </li></ul><ul><li>This would have the following effect: </li></ul><ul><li>This is a dynamic hazard. </li></ul>Design Considerations
  • 28. Function Hazards <ul><li>Function hazards are non-solvable hazards which occur when more than one input variable changes at the same time. Hazards such as function hazards can not be logically eliminated as the problem lies with actual specification of the circuit. The only real way to avoid such problems is to restrict the changing of input variables so that only one input should change at any given time. </li></ul><ul><li>Restrictions are not always possible, for instance let us imagine some logic circuit that has two inputs. One input is used for a clock signal, and the other is connected to a random noise source that we wish to measure. It should be clear that restrictions in this case would not be an effective solution. </li></ul>Design Considerations
  • 29. The simplest example of this is the exclusive-OR function If both inputs are at 0 then the output is 0 – if they both then change to 1 simultaneously then the output should stay at 0 but delays may cause a short time when the output goes to 1. * The above text is taken from http://en.wikipedia.org/wiki/Hazard_(logic) and is available under the Creative Commons Attribution-ShareAlike License .
  • 30. Don’t Care <ul><li>A logic circuit with N inputs will have will have 2 N possible input combinations. For a number of reasons some of these combinations may never exist, in fact in some applications the majority may not exist. </li></ul><ul><li>How do we deal with combinations that cannot occur on the input? </li></ul><ul><li>We treat them as don’t cares when simplifying the logic expressions. What we mean is that the output can be 1 or 0 as the input will never occur to generate the output. </li></ul><ul><li>On the Karnaugh Map, a don’t care input is indicated by an X. </li></ul>Design Considerations
  • 31. <ul><li>The following rules are applied when grouping: </li></ul><ul><li>X’s do not need to be grouped </li></ul><ul><li>If a smaller group can be made bigger by including X’s – do so. </li></ul><ul><li>If a group consists only of X’s remove it </li></ul><ul><li>If we are looking for a hazard free solution then if we have an identified hazard point and one of the points of contact is an X – the hazard will not occur so ignore it. </li></ul>Design Considerations
  • 32. Example 1 2 3 4 5 6 7 8 9 0 A B C D The numerical pad is used to send information to a logic circuit. The pad has an encoder which converts the number pushed into a 4-bit binary number. A is the most significant bit and D the least. A logic circuit must recognise if one of the following buttons has been pressed: 2, 3, 4, 7 or 8. Design a logic circuit to do this. Design Considerations
  • 33. 0 1 1 1 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 0 0 1 0 1 0 0 1 1 0 0 0 1 0 0 0 Y 0 1 1 0 C D B 0 0 0 0 0 1 1 0 0 A Y D C B A Design Considerations
  • 34. 0 1 1 1 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 0 0 1 0 1 0 0 1 1 0 0 0 1 0 0 0 Y 0 1 1 0 C D B 0 0 0 0 0 1 1 0 0 A Y D C B A Expression Design Considerations
  • 35. <ul><li>This is a complicated expression and does not take into account the fact that six of the sixteen input combinations can never exist, as they are never generated. These are 1010 to 1111. </li></ul><ul><li>If we regenerate the Karnaugh Map with X’s in these positions we will have: </li></ul>Design Considerations
  • 36. X 1 1 1 1 X 0 1 1 1 X 1 0 1 1 X 0 0 1 1 X 1 1 0 1 X 0 1 0 1 0 1 0 0 1 1 0 0 0 1 X X 1 1 0 1 1 1 1 0 0 0 1 1 0 X X 1 1 1 1 0 1 0 1 0 1 0 0 1 0 X 0 1 1 1 1 0 0 1 0 1 0 0 1 X 1 0 0 0 1 0 0 0 Y 0 1 1 0 C D B 0 0 0 0 0 1 1 0 0 A Y D C B A Design Considerations
  • 37. X 1 1 1 1 X 0 1 1 1 X 1 0 1 1 X 0 0 1 1 X 1 1 0 1 X 0 1 0 1 0 1 0 0 1 1 0 0 0 1 X X 1 1 0 1 1 1 1 0 0 0 1 1 0 X X 1 1 1 1 0 1 0 1 0 1 0 0 1 0 X 0 1 1 1 1 0 0 1 0 1 0 0 1 X 1 0 0 0 1 0 0 0 Y 0 1 1 0 C D B 0 0 0 0 0 1 1 0 0 A Y D C B A Expression Design Considerations
  • 38. <ul><li>Notes. </li></ul><ul><li>Not all X’s are grouped – this is fine. </li></ul><ul><li>There is a potential hazard in this solution but it cannot possibly occur. </li></ul><ul><li>Compare expressions </li></ul>Design Considerations
  • 39. This resource was created by the University of Wales Newport and released as an open educational resource through the Open Engineering Resources project of the HE Academy Engineering Subject Centre. The Open Engineering Resources project was funded by HEFCE and part of the JISC/HE Academy UKOER programme. © 2009 University of Wales Newport This work is licensed under a Creative Commons Attribution 2.0 License . The JISC logo is licensed under the terms of the Creative Commons Attribution-Non-Commercial-No Derivative Works 2.0 UK: England & Wales Licence.  All reproductions must comply with the terms of that licence. The HEA logo is owned by the Higher Education Academy Limited may be freely distributed and copied for educational purposes only, provided that appropriate acknowledgement is given to the Higher Education Academy as the copyright holder and original publisher. The name and logo of University of Wales Newport is a trade mark and all rights in it are reserved. The name and logo should not be reproduced without the express authorisation of the University. Design Considerations

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