The following presentation is a part of the level 4 module -- Digital Logic and Signal Principles. This resources is a part of the 2009/2010 Engineering (foundation degree, BEng and HN) courses from University of Wales Newport (course codes H101, H691, H620, HH37 and 001H). This resource is a part of the core modules for the full time 1st year undergraduate programme. The BEng & Foundation Degrees and HNC/D in Engineering are designed to meet the needs of employers by placing the emphasis on the theoretical, practical and vocational aspects of engineering within the workplace and beyond. Engineering is becoming more high profile, and therefore more in demand as a skill set, in today’s high-tech world. This course has been designed to provide you with knowledge, skills and practical experience encountered in everyday engineering environments.

1. Design Considerations Digital Logic and Software Applications Level 4 © University of Wales Newport 2009 This work is licensed under a Creative Commons Attribution 2.0 License .

6. A B C D Y 1 2 3 4 5 This particular type of hazard is usually due to a NOT gate within the logic. We can see the effects of the delay in the circuit. Design Considerations Static-1 Hazard:

8. INPUT C AND 3 O/P NOT 5 O/P AND 2 O/P OR O/P Design Considerations

9. INPUT C AND 3 O/P NOT 5 O/P AND 2 O/P OR O/P Design Considerations

10. INPUT C AND 3 O/P NOT 5 O/P AND 2 O/P OR O/P Design Considerations

11. INPUT C AND 3 O/P NOT 5 O/P AND 2 O/P OR O/P Design Considerations

12. INPUT C AND 3 O/P NOT 5 O/P AND 2 O/P OR O/P GLITCH Design Considerations

19. 0 0 0 0 1 0 1 1 1 1 Design Considerations A C B 1 2 3 4 5 6 7

20. 00 01 00 00 11 00 11 11 11 11 Design Considerations A C B 1 2 3 4 5 6 7

21. 000 011 000 001 110 000 111 111 111 111 Design Considerations A C B 1 2 3 4 5 6 7

22. 0000 0111 0000 0011 1100 0001 1110 1111 1111 1110 Design Considerations A C B 1 2 3 4 5 6 7

23. 00000 01111 00000 00111 11000 00010 11100 11111 11111 11100 Design Considerations A C B 1 2 3 4 5 6 7

24. 000000 011111 000000 001111 110000 000100 111000 111110 111111 111000 Design Considerations A C B 1 2 3 4 5 6 7

26. 0000 0111 0000 0011 1100 0001 1110 1111 1111 1110 Design Considerations A C B 1 2 3 4 5 6 7

29. The simplest example of this is the exclusive-OR function If both inputs are at 0 then the output is 0 – if they both then change to 1 simultaneously then the output should stay at 0 but delays may cause a short time when the output goes to 1. * The above text is taken from http://en.wikipedia.org/wiki/Hazard_(logic) and is available under the Creative Commons Attribution-ShareAlike License .

32. Example 1 2 3 4 5 6 7 8 9 0 A B C D The numerical pad is used to send information to a logic circuit. The pad has an encoder which converts the number pushed into a 4-bit binary number. A is the most significant bit and D the least. A logic circuit must recognise if one of the following buttons has been pressed: 2, 3, 4, 7 or 8. Design a logic circuit to do this. Design Considerations

33. 0 1 1 1 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 0 0 1 0 1 0 0 1 1 0 0 0 1 0 0 0 Y 0 1 1 0 C D B 0 0 0 0 0 1 1 0 0 A Y D C B A Design Considerations

34. 0 1 1 1 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 0 0 1 0 1 0 0 1 1 0 0 0 1 0 0 0 Y 0 1 1 0 C D B 0 0 0 0 0 1 1 0 0 A Y D C B A Expression Design Considerations

36. X 1 1 1 1 X 0 1 1 1 X 1 0 1 1 X 0 0 1 1 X 1 1 0 1 X 0 1 0 1 0 1 0 0 1 1 0 0 0 1 X X 1 1 0 1 1 1 1 0 0 0 1 1 0 X X 1 1 1 1 0 1 0 1 0 1 0 0 1 0 X 0 1 1 1 1 0 0 1 0 1 0 0 1 X 1 0 0 0 1 0 0 0 Y 0 1 1 0 C D B 0 0 0 0 0 1 1 0 0 A Y D C B A Design Considerations

37. X 1 1 1 1 X 0 1 1 1 X 1 0 1 1 X 0 0 1 1 X 1 1 0 1 X 0 1 0 1 0 1 0 0 1 1 0 0 0 1 X X 1 1 0 1 1 1 1 0 0 0 1 1 0 X X 1 1 1 1 0 1 0 1 0 1 0 0 1 0 X 0 1 1 1 1 0 0 1 0 1 0 0 1 X 1 0 0 0 1 0 0 0 Y 0 1 1 0 C D B 0 0 0 0 0 1 1 0 0 A Y D C B A Expression Design Considerations

39. This resource was created by the University of Wales Newport and released as an open educational resource through the Open Engineering Resources project of the HE Academy Engineering Subject Centre. The Open Engineering Resources project was funded by HEFCE and part of the JISC/HE Academy UKOER programme. © 2009 University of Wales Newport This work is licensed under a Creative Commons Attribution 2.0 License . The JISC logo is licensed under the terms of the Creative Commons Attribution-Non-Commercial-No Derivative Works 2.0 UK: England & Wales Licence. All reproductions must comply with the terms of that licence. The HEA logo is owned by the Higher Education Academy Limited may be freely distributed and copied for educational purposes only, provided that appropriate acknowledgement is given to the Higher Education Academy as the copyright holder and original publisher. The name and logo of University of Wales Newport is a trade mark and all rights in it are reserved. The name and logo should not be reproduced without the express authorisation of the University. Design Considerations