Vtoibuffer Cdr Ym
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This document summarizes the design of a V to I buffer for bias reference currents. The buffer is designed to operate between 3.0V and 3.6V with a reference voltage of 500mV over a temperature range of -40C to 150C. Simulation results show good regulation and stability over process and temperature variations with a low quiescent current between 35uA to 80uA. PSRR is measured to be around -47dB up to 200kHz and -39dB up to 6MHz. Transient analysis shows smooth transitions on the buffer output with no ringing in response to a pulse on the reference voltage node.
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https://authelectronic.com/original-n-channel-mosfet-mmf60r360pth-60r360-11a-600v-to-220f-new
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This document provides information on a digital audio MOSFET in a TO-220 Full-Pak 5 pin package designed for class D audio amplifier applications. The MOSFET integrates two power switches in a half-bridge configuration to reduce part count. Key parameters like low RDS(on), Qg, Qsw, and Qrr are optimized to improve efficiency, THD, and reduce EMI. Figures and tables of electrical characteristics like breakdown voltage, on-resistance, gate charge, and switching performance are provided. The document also includes test circuits and considerations for evaluating the MOSFET.
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Vtoibuffer Cdr Ym
- 1. V to I Buffer for Bias Reference Currents Yusuf Matcheswala May 08, 2009
- 3. Device Parameters File: top_params.pdf REF node Voltage at this node tracks REF node Matched
- 4. Buffer File: amp_params.pdf Input Level Shifters Folded cascode Common source output stage Bias stage Tail current sink Miller compensation NMOS load
- 5. Current Mirror File: bias_params.pdf Cascode device Bias device
- 6. Current source for buffer File: cs_params.pdf Iptat
- 7. DC analysis
- 8. Simulation setup (mos=ss, bipolar=s res=s, -40C, 3.0V) File:top_ssss_m40C_3p0.pdf 6uA 3uA 501.6mV 500mV
- 9. Buffer (mos=ss, bipolar=s res=s, -40C, 3.0V) File:amp_ssss_m40C_3p0.pdf 1.5uA 6uA 2.3uA
- 10. Current mirror (mos=ss, bip=s res=s, -40C, 3.0V) File:bias_ssss_m40C_3p0.pdf 6uA 3uA
- 11. Current source for buffer (mos=ss, bipolar=s, res=s, -40C, 3.0V) File:cs_ssss_m40C_3p0.pdf 4.7uA 4.8uA
- 13. Stability summary 37.8 86.9 MOS ff, Bipolar=f, Resistor ff, 150C, VDD=3.0V 25.4 116.0 Nominal 16.4 101.2 MOS ss, Bipolar s, Resistor ss, -40C, VDD=3.0V GM(dB) PM
- 14. Stability response File:loopgain.pdf miller compensation cap adds a zero.
- 17. Pulse on Vref node File:trans.pdf No ringing, smooth transitions on buffer output
- 19. End of main presentation
- 21. Simulation setup (mos=ff, bip=f res=f, 150C, 3.0V) Iin=20.18uA Iref1=10.1uA Vfb=499.76mV Vref1=500.76mV File:top_ffff_150_3p0.pdf
- 22. V to I Buffer (mos=ff, bip=f res=f, 150C, 3.0V) File:amp_ffff_150_3p0.pdf
- 23. Current mirror (mos=ff, bip=f res=f, 150C, 3.0V) File:bias_ffff_150_3p0.pdf
- 24. Current source for buffer (mos=ff, bip=f res=f, 150C, 3.0V) Iin=20.72uA Iptat=11.25uA File:cs_ffff_150_3p0.pdf
- 25. V to I buffer (mos=sf, bipolar=s res=s, -40C, 3.0V) File:amp_sfss_m40C_3p0.pdf
Editor's Notes
- Wide swing topology used, with two current sources. Also known as Sooch current mirror.
- Bipolar frontend gives better gm than if FETs were used.
- Accurately mirrors Iin to Iout. Because vds of both devices close Bias devices (closer to supply rail) primary devices that control accuracy of mirrored current. Moderate W (10um), large L (12um) chosen for good matching. Gives small aspect ratio. Comparartively higher Vdsat (~300mV nominal). Cascode devices small vdsat required, hence need large aspect ratio, minimum L (0.35um) chosen to give large aspect ratio. Vdsat ~80mV nominal. Improves Ro due to cascoding of mirrored pair. Unit devices chosen for all devices in bias group and cascode group and required aspect ratio achieved by varying fingers.