Projects
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The document outlines Preetham Kumar Duggishetti's Masters projects in electrical engineering focusing on circuit design, including projects developing a Phase Locked Loop at 1.6GHz, a low power 32-bit ALU, an oversampling Sigma Delta ADC for WLAN systems, and more. The projects involved designing circuits in Cadence and developing behavioral models in VerilogA and MATLAB to meet various power, speed, and dynamic range requirements. Preetham's work demonstrates expertise in analog and mixed-signal circuit design.
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Projects
Preetham Kumar Duggishetti's projects include the design of circuits such as a Phase Locked Loop in 0.18um technology achieving a 300ns lock time and 82ps of jitter, a low power 32-bit ALU consuming 8.65pJ of power, and a programmable Sigma Delta Analog to Digital Converter achieving 14-bit and 12-bit resolutions for cellular and cordless phones respectively using Matlab/Simulink tools. The document provides details on the technologies, tools, and goals of several circuit design projects completed by Preetham Kumar Duggishetti as part of his Masters in Electrical Engineering degree.
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Projects
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Exploring strategies to deploy and adapt custom hardware such as Google Tensor Processing Units and Xilinx Deep-learning Processing Units to obtain high-performance and energy-efficient AI.
The Implementing AI: Hardware Challenges, hosted by KTN and eFutures, is the first event of the Implementing AI webinar series to address the challenges and opportunities that realising AI for hardware present.
There will be presentations from hardware organisations and from solution providers in the morning; followed by Q&A. The afternoon session will consist of virtual breakout rooms, where challenges raised in the morning session can be workshopped.
Artificial Intelligence now impacts every aspect of modern life and is key to the generation of valuable business insights.
Implementing AI webinar series is designed for people involved in the management and implementation of AI based solutions – from developers to CTOs.
Find out more: https://ktn-uk.co.uk/news/just-launched-implementing-ai-webinar-series
Thesis presentation
The document summarizes the design, analysis, and simulation of a Schottky diode-based sampling circuit for a 40 Gbps electronic time-division demultiplexer. The circuit uses a double diode configuration for sampling and undersampling theory to demultiplex the input signal. Bandwidth optimization is performed through analytic calculations and simulations. Layout design achieves 55 GHz bandwidth with a distance of 250 um between the capacitor and diode. Flip-chip bonding affects performance above 50 GHz. Future work includes using diodes with lower capacitance and compensating for flip-chip effects above 40 Gbps.
Presentation2
The document describes the design and simulation of various digital logic circuits in 180nm CMOS technology. A CMOS inverter was designed with aspect ratios of W/L=10 for NMOS and W/L=2.5 for PMOS. A 10-transistor full adder cell was implemented with a maximum delay of 98.727ps. A 4x4 Vedic multiplier was also designed using the full adder cells, achieving a maximum delay of 454ps and operating at 2.2 billion multiplications/second. The circuits were simulated in transient analysis to obtain their performance parameters.
Professional Profile
Sriram Sundararajah's professional profile includes a Master's degree in Electrical Engineering from Arizona State University and a Bachelor's degree in Electronics & Communication Engineering from Anna University, India. He has worked as a volunteer research assistant at ASU and as an intern at Foveon, Inc. His previous experience includes working as an assistant systems engineer at Tata Consultancy Services. His projects include designing and simulating pipelined ADCs, PLLs, current references, and amplifiers using Cadence tools.
A low cost low-power ring oscillator-based truly random number generator for ...
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Sushant
1. FinFETs allow for independent control of transistor gates, enabling new low-power circuit techniques like unusual logic styles and dual-Vdd circuits.
2. Simulation shows these FinFET circuit techniques can reduce total power consumption in ISCAS'85 benchmarks by up to 80% compared to traditional static CMOS designs.
3. FinFETs also enable architectural optimizations like variation-tolerant SRAM and novel non-volatile reconfigurable logic that could provide over an order of magnitude improvements in density and performance.
20614-38948-1-PB.pdf
In this research, we present a low phase noise (PN) and wide tuning range 175 GHz inductors and capacitors (LC) voltage-controlled oscillator (VCO) based on a differential Colpitts oscillator that was designed using a 0.13 μm bipolar complementary metal oxide semiconductor (BiCMOS) and simulated. The square of the tank Q-factor and the square of the oscillation amplitude were both maximized to reduce PN. With an extensive examination of parasitic, mathematical analysis of load impedances, and implementation of differential design, the PN was reduced, and the output power was enhanced. Using a supply voltage of 1.6 V, the VCO consumes 41.9 mA, resulting in a total power usage of 67 mW to prevent undesirable PN deterioration, an inter-stage LC filter at the VCO-buffer interface increases the swing at the buffer input. To make a better output, a buffer is used to isolate the load from the VCO core. In addition, the VCO has a high linearity and the overall, the VCO presented in this study demonstrates excellent performance and has the potential to be used in a wide range of applications that require a high-performance, low-power VCO.
4---glynn-and-devlin---an-x-band-gan-pa-mmic-for-p.pdf
This document describes an X-band GaN MMIC power amplifier for use in phased array radar applications. The amplifier operates from 9-11.5 GHz with an output power of 7W and power added efficiency of 42% when driven with 29dBm of input power. The small die size of 1.5mm x 2mm allows for high density packaging, with around 2,300 amplifiers fitting on a single 4-inch wafer. Measurement results show good agreement with simulations and confirm the MMIC meets requirements for use in active phased array radars.
Performance Analysis of Encoder in Different Logic Techniques for High-Speed ...
In designing a system, we can replace cell components by appropriate technique based cell so that the noise margin of overall circuit is improved. In future we can also implement some techniques for sequential circuits.
CMOS Analog IC design by Dr GS Javed - Refresher Course - Batch 1
Topics covered in the course
1. DC Biasing of the circuits
2. Circuits for reference voltage and current generation
-Voltage Regulator
-BGR
-LDO
-V-to-I
3. Precision Current References
4. Opamp design for Analog to digital converters
- OTA
- Buffer
- Unity Feedback OTA
- Layout design strategies – 2stage opamp + CMFB
5. Sense and Return mechanisms in Feedback circuits
- Current and Voltage circuits
6. Sub-Threshold Conduction
- Low voltage Operation
7. ADC Design and Simulation
-Near Nyquist performance of Opamp for ADC Circuits
-Spectral Analysis and No. of FFT Points for simulation
-Simulation time for performance
-Resistors – their variation and Calibration
-Switch design for S/H
-CDAC
8. On-Chip Inductors
Project_Kaveh & Mohammad
This document presents the design of a high performance folded cascade OTA and sample and hold circuit. The OTA is designed to achieve 10-bit resolution while operating at a 28 MHz sampling frequency. Simulation results show the OTA achieves a high open loop gain of 72 dB and bandwidth of 112 MHz, with a phase margin of 73 degrees. A low resistance transmission gate switch is designed to reduce charge injection and clock feedthrough effects during sampling. The circuit is implemented in a 130 nm CMOS technology.
Challenges of Parallel Simulation of Power Systems_english
This document discusses the challenges of parallel power system simulation. It outlines key challenges including simulating large networks, high switching frequencies for power electronics, and interfacing with physical controllers in real-time. It proposes solutions such as using FPGAs to offload computations and meet tight timing requirements. Case studies demonstrate simulating large systems like HVDC transmission lines in parallel across CPUs and FPGAs with perfect matching to offline simulations.
Devyani 1st Ext. Presentation
The document presents a dissertation on the design of a low-voltage low-dropout regulator using a current splitting technique in 90nm CMOS technology. It outlines the objectives of power management and discusses conventional power converters including linear regulators and switching regulators. It then examines issues in low-dropout regulator design such as the pass transistor, error amplifier, and stability. Existing techniques to improve power supply rejection are analyzed along with their pros and cons. The problem statement and objectives of the proposed work are given as designing a regulator with a 1V input, 0.85-0.5V output, 60uA quiescent current, and 0.0041mm^2 area using a current splitting error amplifier technique. The tool, block
IEEE CASE 2011, Italy - Conference Paper Presentation
The document describes a system for tumor detection using low transient ultrasound pulses. It summarizes that breast cancer is a leading cause of cancer deaths in women. The system aims to detect tumors early using an FPGA/DSP-based ultrasound imaging technology. It generates short ultrasound pulses using an FPGA to improve resolution. The DSP processes received signals to detect tumor size and location. The document provides details on the system design, implementation of pulse generation and signal processing on the FPGA and DSP, and analysis of results on tumor phantom samples.
Semiconductor overview
The document provides an overview of the history and evolution of semiconductors and integrated circuits from 1947 to present. It discusses key inventions and milestones such as the transistor in 1947, the integrated circuit in 1961, and Moore's Law predicting transistor doubling every two years. It also covers different chip design approaches including full custom, standard cell, gate arrays, and FPGAs, along with their relative costs, performance, and design complexities.
Linkmeup v23-compass-eos
The document discusses optical interconnect technology for routers. It describes how conventional copper interconnects have limitations like power consumption and distance, while optical interconnects using fibers can transfer data over longer distances with lower power. The D-chip is presented as the first commercial router product using optical interconnect between silicon chips. It provides over 1 terabit per second bandwidth density and can scale to support future networking needs. The document also outlines how an output queued router architecture using optical interconnects between line cards improves performance for multicast traffic compared to a conventional router design.
Development of a Single Stage C-Band Pulsed Power Amplifier for RADAR Transmi...
Abstract— This paper presents the design and development of
a single stage solid state pulse power amplifier(SS-PPA)
working at 7.23 GHz ± 100 MHz frequency by using hybrid technology. The amplifier is designed to achieve maximum
power gain with medium output power by adopting
simultaneous conjugate matching procedure. Commercial
available packaged pseudomorphic high electron mobility
transistor (pHEMT) FPD6836P70 (from RFMD) is used for
designing the amplifier. A pulse aggregate card has been developed to provide pulse bias. Plated through hole (PTH)
technique is used for good high frequency grounding. At room
ambient temperature, the measured peak output power from
the prototype amplifier is 18.31 dBm for 8 dBm input driving
power, measuring 10.31 dB gain. We present a description of
the design of the amplifier, its simulated and measured results
and their comparison with desired specifications.
Similar to Projects (20)
Efficient signal acquisition in multi channel neural systems
Efficient signal acquisition in multi channel neural systems
Implementing AI: Hardware Challenges: Heterogeneous and Adaptive Computing fo...
Implementing AI: Hardware Challenges: Heterogeneous and Adaptive Computing fo...
A low cost low-power ring oscillator-based truly random number generator for ...
A low cost low-power ring oscillator-based truly random number generator for ...
4---glynn-and-devlin---an-x-band-gan-pa-mmic-for-p.pdf
4---glynn-and-devlin---an-x-band-gan-pa-mmic-for-p.pdf
Performance Analysis of Encoder in Different Logic Techniques for High-Speed ...
Performance Analysis of Encoder in Different Logic Techniques for High-Speed ...
CMOS Analog IC design by Dr GS Javed - Refresher Course - Batch 1
CMOS Analog IC design by Dr GS Javed - Refresher Course - Batch 1
Challenges of Parallel Simulation of Power Systems_english
Challenges of Parallel Simulation of Power Systems_english
IEEE CASE 2011, Italy - Conference Paper Presentation
IEEE CASE 2011, Italy - Conference Paper Presentation
Development of a Single Stage C-Band Pulsed Power Amplifier for RADAR Transmi...
Development of a Single Stage C-Band Pulsed Power Amplifier for RADAR Transmi...
Projects
- 1. Project Works Preetham Kumar Duggishetti Masters in Electrical Engineering Electronics and Mixed Signal Circuit Design Arizona State University pduggish@asu.edu preetham463@gmail.com
- 3. Cadence (Spectre ) , VerilogA, MATLAB.
- 4. Generated 4 equally spaced clocks at 1.6GHz with CMOS full-swing (1.8V), achieved 300ns lock time for 1.6GHz oscillation.
- 7. Requirement : Power consumption to be least with a delay constraint of 10 nS, output transition time lower than 200pS with a load of 30 fF at the -10%Vdd and Slow-Slow Design corner.
- 8. Understood various design techniques for Low Power and procedures to choose the right logic style.
- 10. Cadence (Spectre ) , MATLAB/SIMULINK, VerilogA .
- 13. Dc gain > 50dB, Ft = 70MHz with CL = 1pF, Tail current source < 110uA.
- 15. Cadence (Spectre ) .
- 16. Understood IC biasing circuits and their variations with supply and temperature.
- 18. Cadence (Spectre , Virtuso Layout Editor )
- 19. High gain, UGF of 25 MHz with 15pF capacitive load, input referred noise of 10nV/sqHz, Quiescent Power dissipation of 1.2mW, Slew rate of 10V/usec with 5pF cap load, PSRR and CMRR of 55dB at 10 KHz and Phase margin of 60 degrees with 5pF capacitive load.
- 21. Matlab/Simulink tools were used and a resolution of 14 bit and 12 bit respectively were achieved.