International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Novel Approach for Evaluating Video Transmission using Combined Scalable Vide...IJECEIAES
One of the main problems in video transmission is the bandwidth fluctuation in wireless channel. Therefore, there is an urgent need to find an efficient bandwidth utilization and method. This research utilizes the Combined Scalable Video Coding (CSVC) which comes from Joint Scalable Video Model (JSVM). In the combined scalable video coding, we implement Coarse Grain Scalability (CGS) and Medium Grain Scalability (MGS). We propose a new scheme in which it can be implemented on Network Simulator II (NS-2) over wireless broadband network. The advantages of this new scheme over the other schemes are more realistic and based on open source program. The result shows that CSVC implementation on MGS mode outperforms CGS mode.
Performance evaluation of the IEEE 802.11n random topology WLAN with QoS appl...IJECEIAES
The IEEE 802.11n supports high data rate transmissions due its physical layer Multiple Input Multiple Output (MIMO) advanced antenna system and MAC layer enhancement features (frame aggregation and block acknowledgement). As a result this standard is very suitable for multimedia services through its Enhanced Distributed Channel Access (EDCA). This paper focuses on evaluating the Quality of Service (QoS) application on the performance of the IEEE 802.11n random topology WLAN. Three different number of nodes (3, 9 and 18) random topology with one access point are modeled and simulated by using the Riverbed OPNET 17.5 Modular to investigate the Wireless Local Area Network (WLAN) performance for different spatial streams. The result clarified the impact of QoS application and showed that its effect is best at the 18 node number topology. For a 4x4 MIMO, when QoS is applied and with respect to the no QoS application case, simulation results show a maximum improvement of 86.4%, 33.9%, 52.2% and 68.9% for throughput, delay, data drop and retransmission attempts, respectively.
The paper presents a technique called as Mobility-enabled Multi Level Optimization (MeMLO) that addressing the existing problem of clustering in wireless sensor net-work (WSN). The technique enables selection of aggregator node based on multiple optimi-zation attribute which gives better decision capability to the clustering mechanism by choosing the best aggregator node. The outcome of the study shows MeMLO is highly capable of minimizing the halt time of mobile node that significantly lowers the transmit power of aggregator node. The simulation outcome shows negligible computational com-plexity, faster response time, and highly energy efficient for large scale WSN for longer simulation rounds as compared to conventional LEACH algorithm.
REUSABILITY-AWARE ROUTING WITH ENHANCED SECURE DATA TRANSMISSION USING HOP-BY...AM Publications,India
Recent developments made in wireless environment attract several users for transmitting their data in secured manner. In order to transact the data in lesser time, an optimized and shortest route should be selected by the source node. Though there are several protocols exist, this issue is not yet resolved. In this paper, we have proposed a novel routing protocol, SSAAR that provide an end –to –end throughput between the source node and the destination node. The authentication is provided using Elliptical curves. Every user in the wireless network generates public key and secret key. The secret key is further furnished and verified by our routing protocols that ensures the security and reliability of the proposed system. An experimental result proves the effectiveness of the proposed protocols.
Checkpoint and recovery protocols are commonly used in distributed applications for providing fault
tolerance. A distributed system may require taking checkpoints from time to time to keep it free of arbitrary
failures. In case of failure, the system will rollback to checkpoints where global consistency is preserved.
Checkpointing is one of the fault-tolerant techniques to restore faults and to restart job fast. The algorithms
for checkpointing on distributed systems have been under study for years.
It is known that checkpointing and rollback recovery are widely used techniques that allow a distributed
computing to progress inspite of a failure.There are two fundamental approaches for checkpointing and
recovery.One is asynchronus approach, process take their checkpoints independenty.So,taking checkpoints
is very simple but due to absence of a recent consistent global checkpoint which may cause a rollback of
computation.Synchronus checkpointing approach assumes that a single process other than the application
process invokes the checkpointing algorithm periodically to determine a consistent global checkpoint.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Novel Approach for Evaluating Video Transmission using Combined Scalable Vide...IJECEIAES
One of the main problems in video transmission is the bandwidth fluctuation in wireless channel. Therefore, there is an urgent need to find an efficient bandwidth utilization and method. This research utilizes the Combined Scalable Video Coding (CSVC) which comes from Joint Scalable Video Model (JSVM). In the combined scalable video coding, we implement Coarse Grain Scalability (CGS) and Medium Grain Scalability (MGS). We propose a new scheme in which it can be implemented on Network Simulator II (NS-2) over wireless broadband network. The advantages of this new scheme over the other schemes are more realistic and based on open source program. The result shows that CSVC implementation on MGS mode outperforms CGS mode.
Performance evaluation of the IEEE 802.11n random topology WLAN with QoS appl...IJECEIAES
The IEEE 802.11n supports high data rate transmissions due its physical layer Multiple Input Multiple Output (MIMO) advanced antenna system and MAC layer enhancement features (frame aggregation and block acknowledgement). As a result this standard is very suitable for multimedia services through its Enhanced Distributed Channel Access (EDCA). This paper focuses on evaluating the Quality of Service (QoS) application on the performance of the IEEE 802.11n random topology WLAN. Three different number of nodes (3, 9 and 18) random topology with one access point are modeled and simulated by using the Riverbed OPNET 17.5 Modular to investigate the Wireless Local Area Network (WLAN) performance for different spatial streams. The result clarified the impact of QoS application and showed that its effect is best at the 18 node number topology. For a 4x4 MIMO, when QoS is applied and with respect to the no QoS application case, simulation results show a maximum improvement of 86.4%, 33.9%, 52.2% and 68.9% for throughput, delay, data drop and retransmission attempts, respectively.
The paper presents a technique called as Mobility-enabled Multi Level Optimization (MeMLO) that addressing the existing problem of clustering in wireless sensor net-work (WSN). The technique enables selection of aggregator node based on multiple optimi-zation attribute which gives better decision capability to the clustering mechanism by choosing the best aggregator node. The outcome of the study shows MeMLO is highly capable of minimizing the halt time of mobile node that significantly lowers the transmit power of aggregator node. The simulation outcome shows negligible computational com-plexity, faster response time, and highly energy efficient for large scale WSN for longer simulation rounds as compared to conventional LEACH algorithm.
REUSABILITY-AWARE ROUTING WITH ENHANCED SECURE DATA TRANSMISSION USING HOP-BY...AM Publications,India
Recent developments made in wireless environment attract several users for transmitting their data in secured manner. In order to transact the data in lesser time, an optimized and shortest route should be selected by the source node. Though there are several protocols exist, this issue is not yet resolved. In this paper, we have proposed a novel routing protocol, SSAAR that provide an end –to –end throughput between the source node and the destination node. The authentication is provided using Elliptical curves. Every user in the wireless network generates public key and secret key. The secret key is further furnished and verified by our routing protocols that ensures the security and reliability of the proposed system. An experimental result proves the effectiveness of the proposed protocols.
Checkpoint and recovery protocols are commonly used in distributed applications for providing fault
tolerance. A distributed system may require taking checkpoints from time to time to keep it free of arbitrary
failures. In case of failure, the system will rollback to checkpoints where global consistency is preserved.
Checkpointing is one of the fault-tolerant techniques to restore faults and to restart job fast. The algorithms
for checkpointing on distributed systems have been under study for years.
It is known that checkpointing and rollback recovery are widely used techniques that allow a distributed
computing to progress inspite of a failure.There are two fundamental approaches for checkpointing and
recovery.One is asynchronus approach, process take their checkpoints independenty.So,taking checkpoints
is very simple but due to absence of a recent consistent global checkpoint which may cause a rollback of
computation.Synchronus checkpointing approach assumes that a single process other than the application
process invokes the checkpointing algorithm periodically to determine a consistent global checkpoint.
Advanced Verification Methodology for Complex System on Chip VerificationVLSICS Design
Verification remains the most significant challenge in getting advanced SOC devices in market. The
important challenge to be solved in the Semiconductor industry is the growing complexity of SOCs.
Industry experts consider that the verification effort is almost 70% to 75% of the overall design effort.
Verification language cannot alone increase verification productivity but it must be accompanied by a
methodology to facilitate reuse to the maximum extent under different design IP configurations. This
Advanced reusable test bench development will decrease the time to market for a chip. It will help in code
reuse so that the same code used in sub-block level can be used in block level and top level as well that
helps in saving cost for a tape-out of a chip. This test bench development technique will help us to achieve
faster time to market and will help reducing the cost for the chip up to a large extent.
UVM BASED REUSABLE VERIFICATION IP FOR WISHBONE COMPLIANT SPI MASTER COREVLSICS Design
The System on Chip design industry relies heavily on functional verification to ensure that the designs are bug-free. As design engineers are coming up with increasingly dense chips with much functionality, the functional verification field has advanced to provide modern verification techniques. In this paper, we
present verification of a wishbone compliant Serial Peripheral Interface (SPI) Master core using a System Verilog based standard verification methodology, the Universal Verification Methodology (UVM). The reason for using UVM factory pattern with parameterized classes is to develop a robust and reusable
verification IP. SPI is a full duplex communication protocol used to interface components most likely in embedded systems. We have verified an SPI Master IP core design that is wishbone compliant and compatible with SPI protocol and bus and furnished the results of our verification. We have used
QuestaSim for simulation and analysis of waveforms, Integrated Metrics Center, Cadence for coverage analysis. We also propose interesting future directions for this work in developing reliable systems.
UVM BASED REUSABLE VERIFICATION IP FOR WISHBONE COMPLIANT SPI MASTER COREVLSICS Design
The System on Chip design industry relies heavily on functional verification to ensure that the designs are bug-free. As design engineers are coming up with increasingly dense chips with much functionality, the functional verification field has advanced to provide modern verification techniques. In this paper, we present verification of a wishbone compliant Serial Peripheral Interface (SPI) Master core using a System Verilog based standard verification methodology, the Universal Verification Methodology (UVM). The reason for using UVM factory pattern with parameterized classes is to develop a robust and reusable verification IP. SPI is a full duplex communication protocol used to interface components most likely in embedded systems. We have verified an SPI Master IP core design that is wishbone compliant and compatible with SPI protocol and bus and furnished the results of our verification. We have used QuestaSim for simulation and analysis of waveforms, Integrated Metrics Center, Cadence for coverage analysis. We also propose interesting future directions for this work in developing reliable systems.
UVM BASED REUSABLE VERIFICATION IP FOR WISHBONE COMPLIANT SPI MASTER COREVLSICS Design
The System on Chip design industry relies heavily on functional verification to ensure that the designs are bug-free. As design engineers are coming up with increasingly dense chips with much functionality, the functional verification field has advanced to provide modern verification techniques. In this paper, we
present verification of a wishbone compliant Serial Peripheral Interface (SPI) Master core using a System Verilog based standard verification methodology, the Universal Verification Methodology (UVM). The reason for using UVM factory pattern with parameterized classes is to develop a robust and reusable
verification IP. SPI is a full duplex communication protocol used to interface components most likely in embedded systems. We have verified an SPI Master IP core design that is wishbone compliant and compatible with SPI protocol and bus and furnished the results of our verification. We have used
QuestaSim for simulation and analysis of waveforms, Integrated Metrics Center, Cadence for coverage analysis. We also propose interesting future directions for this work in developing reliable systems.
VERIFICATION OF DRIVER LOGIC USING AMBAAXI UVMVLSICS Design
Advanced Extensible Interface (AXI) is the most commonly used bus protocols in the day-to-day because of its high performance and high-frequency operation without using complex bridges. AXI is also backwardcompatible
with existing AHB and APB interfaces. So verification of driver logic using AMBA-AXI UVM is presented in this paper. The AXI is used for multiple outstanding operations which is only possible in the other protocol but it is possible in AXI because it contains different write address and data channels and AXI also supports out of order transfer based on the transaction ID which is generated at the start of the transfer. The driver logic for the AXI has been designed and implemented using the Universal Verification Methodology (UVM).The signaling of the five channels such as write address, write data, write response, read address, read data channel of AXI protocol are considered for verification. According to the AXI protocol,the signals of these channels are driven to the interconnect and results are observed for single master and single slave. The driver logic has been implemented and verified successfully according to AXI protocol using the Rivera Pro. The results observed for single master and single slave have shown the correctness of AMBA-AXI design in Verilog.
The System Verilog UVM promises to improve verification productivity while enabling teams to share tests and test benches between projects and divisions. This promise can be achieved; the UVM is a powerful methodology for using constrained randomization to reach higher functional coverage goals and to explore combinations of tests without having to write each one individually. Unfortunately the UVM promise can be hard to reach without training, practice and some significant expertise. Verification is one of the most important activities in the flow of ASIC/VLSI design. Verification consumes large amount of design flow cycle & efforts to ensure design is bug free. Hence it becomes intense requirement for powerful and reusable methodology for verification.
A Survey of functional verification techniquesIJSRD
In this paper, we present a survey of various techniques used in functional verification of industry hardware designs. Although the use of formal verification techniques has been increasing over time, there is still a need for an immediate practical solution resulting in an increased interest in hybrid verification techniques. Hybrid techniques combine formal and informal (traditional simulation based) techniques to take the advantage of both the worlds. A typical hybrid technique aims to address the verification bottleneck by enhancing the state space coverage.
October 2020: Top Read Articles in VLSI design & Communication Systems - Arti...VLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
December 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
November 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
March 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
A Unique Test Bench for Various System-on-a-Chip IJECEIAES
This paper discusses a standard flow on how an automated test bench environment which is randomized with constraints can verify a SOC efficiently for its functionality and coverage. Today, in the time of multimillion gate ASICs, reusable intellectual property (IP), and system-ona-chip (SoC) designs, verification consumes about 70 % of the design effort. Automation means a machine completes a task autonomously, quicker and with predictable results. Automation requires standard processes with welldefined inputs and outputs. By using this efficient methodology it is possible to provide a general purpose automation solution for verification, given today’s technology. Tools automating various portions of the verification process are being introduced. Here, we have Communication based SOC The content of the paper discusses about the methodology used to verify such a SOC-based environment. Cadence Efficient Verification Methodology libraries are explored for the solution of this problem. We can take this as a state of art approach in verifying SOC environments. The goal of this paper is to emphasize the unique testbench for different SOC using Efficient Verification Constructs implemented in system verilog for SOC verification.
September 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
Top Trending Article in Academia! - VLSI design & Communication Systems (VLSI...VLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
August 2021 -Top 10 Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
Research on UVM Verification Platform Based on AXI4 Protocol Intellectual Pro...IJRESJOURNAL
ABSTRACT: As the improvement of the status of verification and the verification technology in IC and SoC, this paper designs a verification platform based on Universal Verification Methodology (UVM) and finish the verification of a IP core based on AXI4 protocol ,which Combines the technology of Assert.This platform adopts a VIP RAM IP core based on AXI4 protocol as the Design Under Test(DUT),which takes advantage of the inheritance and reuse of UVM class to build the Universal Verification Component(UVC) and the tree of UVM.It designs transaction of UVM platform as the constrained random excitation,which completes the system verification toward the DUT.At last,the Simulation shows that the UVM platform finishes the verification of the DUT,which reaches the functional coverage on 100%.In addition, instead of the traditional simple testbench, the UVM verification platform in this paper shows the better reusability and portability by the use of the reusability of the UVC,which can be used to verify the other DUT on AXI4 protocol.
June 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
Top Trending Articles - International Journal of VLSI design & Communication ...VLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Generating a custom Ruby SDK for your web service or Rails API using Smithyg2nightmarescribd
Have you ever wanted a Ruby client API to communicate with your web service? Smithy is a protocol-agnostic language for defining services and SDKs. Smithy Ruby is an implementation of Smithy that generates a Ruby SDK using a Smithy model. In this talk, we will explore Smithy and Smithy Ruby to learn how to generate custom feature-rich SDKs that can communicate with any web service, such as a Rails JSON API.
Advanced Verification Methodology for Complex System on Chip VerificationVLSICS Design
Verification remains the most significant challenge in getting advanced SOC devices in market. The
important challenge to be solved in the Semiconductor industry is the growing complexity of SOCs.
Industry experts consider that the verification effort is almost 70% to 75% of the overall design effort.
Verification language cannot alone increase verification productivity but it must be accompanied by a
methodology to facilitate reuse to the maximum extent under different design IP configurations. This
Advanced reusable test bench development will decrease the time to market for a chip. It will help in code
reuse so that the same code used in sub-block level can be used in block level and top level as well that
helps in saving cost for a tape-out of a chip. This test bench development technique will help us to achieve
faster time to market and will help reducing the cost for the chip up to a large extent.
UVM BASED REUSABLE VERIFICATION IP FOR WISHBONE COMPLIANT SPI MASTER COREVLSICS Design
The System on Chip design industry relies heavily on functional verification to ensure that the designs are bug-free. As design engineers are coming up with increasingly dense chips with much functionality, the functional verification field has advanced to provide modern verification techniques. In this paper, we
present verification of a wishbone compliant Serial Peripheral Interface (SPI) Master core using a System Verilog based standard verification methodology, the Universal Verification Methodology (UVM). The reason for using UVM factory pattern with parameterized classes is to develop a robust and reusable
verification IP. SPI is a full duplex communication protocol used to interface components most likely in embedded systems. We have verified an SPI Master IP core design that is wishbone compliant and compatible with SPI protocol and bus and furnished the results of our verification. We have used
QuestaSim for simulation and analysis of waveforms, Integrated Metrics Center, Cadence for coverage analysis. We also propose interesting future directions for this work in developing reliable systems.
UVM BASED REUSABLE VERIFICATION IP FOR WISHBONE COMPLIANT SPI MASTER COREVLSICS Design
The System on Chip design industry relies heavily on functional verification to ensure that the designs are bug-free. As design engineers are coming up with increasingly dense chips with much functionality, the functional verification field has advanced to provide modern verification techniques. In this paper, we present verification of a wishbone compliant Serial Peripheral Interface (SPI) Master core using a System Verilog based standard verification methodology, the Universal Verification Methodology (UVM). The reason for using UVM factory pattern with parameterized classes is to develop a robust and reusable verification IP. SPI is a full duplex communication protocol used to interface components most likely in embedded systems. We have verified an SPI Master IP core design that is wishbone compliant and compatible with SPI protocol and bus and furnished the results of our verification. We have used QuestaSim for simulation and analysis of waveforms, Integrated Metrics Center, Cadence for coverage analysis. We also propose interesting future directions for this work in developing reliable systems.
UVM BASED REUSABLE VERIFICATION IP FOR WISHBONE COMPLIANT SPI MASTER COREVLSICS Design
The System on Chip design industry relies heavily on functional verification to ensure that the designs are bug-free. As design engineers are coming up with increasingly dense chips with much functionality, the functional verification field has advanced to provide modern verification techniques. In this paper, we
present verification of a wishbone compliant Serial Peripheral Interface (SPI) Master core using a System Verilog based standard verification methodology, the Universal Verification Methodology (UVM). The reason for using UVM factory pattern with parameterized classes is to develop a robust and reusable
verification IP. SPI is a full duplex communication protocol used to interface components most likely in embedded systems. We have verified an SPI Master IP core design that is wishbone compliant and compatible with SPI protocol and bus and furnished the results of our verification. We have used
QuestaSim for simulation and analysis of waveforms, Integrated Metrics Center, Cadence for coverage analysis. We also propose interesting future directions for this work in developing reliable systems.
VERIFICATION OF DRIVER LOGIC USING AMBAAXI UVMVLSICS Design
Advanced Extensible Interface (AXI) is the most commonly used bus protocols in the day-to-day because of its high performance and high-frequency operation without using complex bridges. AXI is also backwardcompatible
with existing AHB and APB interfaces. So verification of driver logic using AMBA-AXI UVM is presented in this paper. The AXI is used for multiple outstanding operations which is only possible in the other protocol but it is possible in AXI because it contains different write address and data channels and AXI also supports out of order transfer based on the transaction ID which is generated at the start of the transfer. The driver logic for the AXI has been designed and implemented using the Universal Verification Methodology (UVM).The signaling of the five channels such as write address, write data, write response, read address, read data channel of AXI protocol are considered for verification. According to the AXI protocol,the signals of these channels are driven to the interconnect and results are observed for single master and single slave. The driver logic has been implemented and verified successfully according to AXI protocol using the Rivera Pro. The results observed for single master and single slave have shown the correctness of AMBA-AXI design in Verilog.
The System Verilog UVM promises to improve verification productivity while enabling teams to share tests and test benches between projects and divisions. This promise can be achieved; the UVM is a powerful methodology for using constrained randomization to reach higher functional coverage goals and to explore combinations of tests without having to write each one individually. Unfortunately the UVM promise can be hard to reach without training, practice and some significant expertise. Verification is one of the most important activities in the flow of ASIC/VLSI design. Verification consumes large amount of design flow cycle & efforts to ensure design is bug free. Hence it becomes intense requirement for powerful and reusable methodology for verification.
A Survey of functional verification techniquesIJSRD
In this paper, we present a survey of various techniques used in functional verification of industry hardware designs. Although the use of formal verification techniques has been increasing over time, there is still a need for an immediate practical solution resulting in an increased interest in hybrid verification techniques. Hybrid techniques combine formal and informal (traditional simulation based) techniques to take the advantage of both the worlds. A typical hybrid technique aims to address the verification bottleneck by enhancing the state space coverage.
October 2020: Top Read Articles in VLSI design & Communication Systems - Arti...VLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
December 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
November 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
March 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
A Unique Test Bench for Various System-on-a-Chip IJECEIAES
This paper discusses a standard flow on how an automated test bench environment which is randomized with constraints can verify a SOC efficiently for its functionality and coverage. Today, in the time of multimillion gate ASICs, reusable intellectual property (IP), and system-ona-chip (SoC) designs, verification consumes about 70 % of the design effort. Automation means a machine completes a task autonomously, quicker and with predictable results. Automation requires standard processes with welldefined inputs and outputs. By using this efficient methodology it is possible to provide a general purpose automation solution for verification, given today’s technology. Tools automating various portions of the verification process are being introduced. Here, we have Communication based SOC The content of the paper discusses about the methodology used to verify such a SOC-based environment. Cadence Efficient Verification Methodology libraries are explored for the solution of this problem. We can take this as a state of art approach in verifying SOC environments. The goal of this paper is to emphasize the unique testbench for different SOC using Efficient Verification Constructs implemented in system verilog for SOC verification.
September 2021: Top Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
Top Trending Article in Academia! - VLSI design & Communication Systems (VLSI...VLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
August 2021 -Top 10 Read Articles in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
Research on UVM Verification Platform Based on AXI4 Protocol Intellectual Pro...IJRESJOURNAL
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Epistemic Interaction - tuning interfaces to provide information for AI support
H04402052057
1. ISSN (e): 2250 – 3005 || Vol, 04 || Issue, 4 || April – 2014 ||
International Journal of Computational Engineering Research (IJCER)
www.ijceronline.com Open Access Journal Page 52
Reusability of test bench of UVM for Bidirectional router and
AXI bus
Manjushree.k.chavan1,
Yogeshwary.B.H2
1 4th sem, M.Tech (VLSI Design & Embedded systems), RIT, Hassan,
2 Assistant professor. Dept of ECE, RIT, Hassan, Karnataka.
I. INTRODUCTION
The process of demonstrating the functionality of the design has become one of the major tasks in
today’s era of multi-million gate ASICs and FPGAs. Verification consumes about 70% of the design effort. The
number of verification engineer is more than the design engineers so the challenge of verifying a large design is
growing exponentially. There is a need to define new methods that makes functional verification easy. Several
strategies in the recent years have been proposed to achieve good functional verification with less effort. The
recent advancement is to develop a methodology to reduce the time taken for verification. The advancement in
the verification environment should be such that it reduces the re-spin of the ASIC design due to functional bugs
and thus reducing the time to market.
This project helps one to understand about the latest verification methodologies, programming concepts like
Object Oriented Programming of Hardware Verification Languages for the high quality verification with automation. This
project is intended in building the reusability of test bench for the designed bidirectional network on chip router through
virtual channel regulator and the AXI bus using the latest UVM verification methodologies.
II. MOTIVATION FOR THE WORK
The process of modernizing the verification methodology to reduce the time taken for verification can
be accomplished by using the latest universal verification methodology (UVM). UVM is a combined effort of
designers and tool vendors, based on the successful OVM and VMM methodologies. Its main promise is to
improve test bench reuse, make verification code more portable and thus create a new market. The reusability of
this verification environment is demonstrated by designing a bidirectional network on chip router through
virtual channel regulator along with the shortest path algorithm for routing and also designing the AXI bus.
III. LITERATURE SURVEY
Chow.K.W.Y., (1994) mentioned in his paper that the early stages of design was verified by design engineer
only using Verilog tasks and functions due to which all the test cases was not met and also time to market was
not able to reach efficiently. Lot of time was spent in verification rather than design [1].
ABSTRACT:
The predictive analysis of the design to ensure that, it will perform the given I/O function is performed
through functional verification. Verification has become the dominant cost in any of the design process.
The modernization of functional verification has become necessary task in verifying a large design. The
project focuses on designing the Bidirectional network on chip router through virtual channel regulator
and then AXI bus and thus developing the common verification environment for both the designs to
show the reusability of test bench. The bidirectional network on chip router is implemented with unified
buffer structure called the dynamic virtual channel regulator. The project also aims to develop a
shortest path algorithm when a packet of data is to be transmitted as many paths are available thus by
designing two routers. The functionality of the design is verified by using the latest Universal
verification methodologies (UVM) further with the employment of reusable test benches of UVM for
both the designs. The Verification goes on with which it finds functional coverage, state coverage, code
coverage and toggle coverage of the Network on Chip Router by using Questa-Sim/cadence NC
simulator and the synthesis is done by using Xilinx ISE 14.3i EDA Tools.
KEYWORDS: Universal verification methodologies, virtual channel regulator, Open verification
methodology, verification methodology module, AXI interconnect.
2. Reusability of test bench of UVM for Bidirectional router and AXI bus
www.ijceronline.com Open Access Journal Page 53
Few years later the System Verilog language was introduced by Accellera in 2002 and as IEEE
Standard 1800-2005 in 2005. In 2009, the standard was merged with the base Verilog (IEEE 1364-2005)
standard, creating IEEE Standard 1800-2009. The current version is IEEE standard 1800-2012. It is the first
hardware verification language.
Moorby.P., (2004) in 17th International conference proposed the several aspects of this new language
and how they form a critical part in the new design for verification paradigm [2].
McMahon, Anthony , O'Keeffe, Niall, Keane Kevin ,O'Reilly, James., (2008) presented a paper on
System Verilog Verification Methodology Manual (VMM) was the first successful and widely implemented set
of practices for creation of reusable verification environments in System Verilog, created by Synopsys, one of the
strong proponents of System Verilog[3].
S. Iman., (2008) published a paper on "Step-by-step functional verification with System Verilog and OVM", with
the new verification methodology named OVM. OVM is the library of objects and procedures for stimulus generation, data
collection and control of verification process. It is available in System Verilog and System C [4].
Jae-Beom Kim, Nam-Do Kim, Byeong Min., (2011) published a paper on Universal verification
methodologies (UVM), which is considered to be the common verification methodology [5].
T Lakshmi Priyanka, G. Deepthi, B. Sunil Kumar., (2013) Proposed the concept of reusability of test
benches with the latest verification methodology i.e. UVM with the design of a router for network on chip
communication in the paper “Reusable test bench for network on chip router using advanced verification
methodologies. The paper explains about the perl script to provide automation in verification [6].
M. Bechtel Brabi and Dr. A. Rajalingam., (2012) illustrated in their paper “Recent survey for Bi-
Directional network on chip pipelined architecture” that bidirectional network on chip router is more efficient
than the conventional architecture. The paper also evidenced about the reduced latency & buffer size, increase in
bandwidth and also indicated that pipelined architecture is more useful than the parallel architecture [7].
Ying-CherngLan, Hsiao-An Lin, Shih-HsinLo , Yu Hen Hu, Sao-Jie Chen.,(2011) published paper on “
A Bidirectional NOC architecture with dynamic self-reconfigurable channel”, in this paper they explained the
concept of dynamic self-reconfigurable channel using an (CDC) channel direction control algorithm to avoid
deadlock and starvation conditions. These results exhibit consistent and significant performance advantage over
conventional NoC equipped with hard-wired unidirectional channels [8].
Mr. Ashish Khodwe , Prof. C.N. Bhoyar., (2013) published a paper on Bidirectional Network on chip
Router through Virtual Channel Regulator, which dynamically allocates virtual channel and buffer resources
according to network traffic conditions [9].
Baoxian Zhang, JieHao, and Hussein T. Mouftah., (2012) published a paper on “Bidirectional Multi-
Constrained Routing Algorithms” in order to demonstrate an algorithm to find the shortest path of transfer of
packets whenever many routing paths are available or when an congestion occurs [10].
Xu Chen, Zheng Xi, and Xin-An Wang., (2013) presented a paper on “Development of verification
environment for AXI Bus using system Verilog”. The paper explained about the methodology of verifying an
AXI bus using system Verilog [11].
Pan Guoteng, Luo Li, OuGuodong, Fu Qingchao, Bai Han., (2013) proposed a paper on “ Design and verification
of a MAC controller based on AXI bus” this paper explained about the verification of AXI bus using an VMM [12]. The
literature survey performed in this section specifies the researches carried out on the various verification methodologies and
also on the design of the router which is considered to be the fundamental unit in an NOC. The related problem definition,
objectives and methodology has been explained in next section.
3.1. Problem formulation
During the recent years modernization of verification methodologies has become major criteria in order to reduce
the time taken for verification and to reduce time to market. From the literature survey it is understood that even
though the System Verilog is standard hardware description language.
There should be common verification methodologies because in reality most of the procedure in the test bench will
be same for different project.
The design of a generic or conventional router with statistically allocated buffer can cause the Head-of-Line
blocking problem. In order to improve the performance and thus reducing the queue blocking, the dynamic buffer
allocation significantly increases buffer usage.
The methodology for developing the verification environment for AXI bus in proposed only by using system
Verilog or by VMM, it is necessary to upgrade the verification of AXI bus using UVM.
3. Reusability of test bench of UVM for Bidirectional router and AXI bus
www.ijceronline.com Open Access Journal Page 54
3.2. Aim of the project
The aim of this paper is the design and implementation of Bidirectional network on chip router through
virtual channel regulator with the shortest path algorithm and AXI bus. The designed system is verified using
the latest verification methodologies i.e., the standard is Universal verification methodologies (UVM), which
supports all of Verilog, system Verilog syntax along with automation techniques and thus observing the code
coverage and functional coverage and thus signifying the reusability of the test bench for the bidirectional router
and AXI bus.
IV. METHODOLOGY
The need for modernized common verification environment called UVM thus used the concept of
reusability of test bench. In this paper to show the reusability of test bench two stages of design is being
performed. First is designing the proposed bidirectional router with virtual channel regulator and the second is
designing AXI interconnect. Both of these designs are verified under common verification environment called
UVM thus showing the reusability of test bench.
V. DESIGN FLOW
The design flow of the project involves two stages, first is the design and implementation of Bidirectional
network on chip router through virtual channel regulator and AXI bus demonstrated in block below. The second
stage is developing a common verification environment called (UVM) and thus checking the reusability of test
benches for both the designs.
Figure 1. Flow diagram of Bidirectional routers with verification environment
The Figure.1 is the flow diagram of designing two bidirectional routers with the virtual channel regulator and
the shortest path algorithm is implemented when many numbers of paths are available. The two interfaces are
virtual interfaces and the packet transfer occurs through dynamic buffer allocation.
4. Reusability of test bench of UVM for Bidirectional router and AXI bus
www.ijceronline.com Open Access Journal Page 55
Figure 2. Flow diagram of design of each router
The Figure.2 is the flow diagram of design of each of the router. The router consists of register, FSM
controller and the FIFOs where the input and output blocks are connected to the virtual interfaces. Arbiter is
used in order to resolve the conflict when two or more packets of data makes a request to transmit a data in the
same channel, in such case arbiter makes decision depending on the priority. The designed system is connected
to the verification environment to check the functionality of the design.
Figure 3. Flow diagram of designing AXI Bus interconnects.
The Figure.3 is the flow diagram of designing AXI Bus interconnects is the second part of the design. The AXI
master and slave performs the read and write data depending on the request and grants. It is connected to the
verification environment to check the intent of the design.
5. Reusability of test bench of UVM for Bidirectional router and AXI bus
www.ijceronline.com Open Access Journal Page 56
Figure 4. UVM Verification Environment
5. Results & Discussion
Figure.5. Simulated waveform of design of four nodes
The Figure.5 is the simulated waveform of design of the four node obtained in modelsim with the design of arbiter
called round robin arbiter with APB bus. Further design is continued with the implementation of many such nodes for two
routers and then designing & implementation of shortest path algorithm and then following the switch design.
VI. CONCLUSION AND FUTURE WORK
6.1. Conclusion
The result above is for generating a packet of data by creating four nodes and thus designing the round robin
arbiter with APB bus. The UVM drives the input to these nodes for further verification process.
6.2. Future work
The above result is continued with the design and implementation of many such nodes with the shortest path
algorithm to transmit the data packet to the other router.
The second stage is designing the AXI interconnect with the packet data transferred from AXI master
and AXI slave by reading the data from the memory.
The third and the final stage is verification of these two designs by using the common verification
environment with the reusable test bench and thus showing the reusability of test bench.
6. Reusability of test bench of UVM for Bidirectional router and AXI bus
www.ijceronline.com Open Access Journal Page 57
REFERENCES
[1] Chow.K.W.Y., “Fully specified verification simulation”, Published in: Verilog HDL Conference, 1994., International, pages 22-
28, Print ISBN:0-8186-5655-7.
[2] Moorby, P., “Design for verification with System Verilog”, Published in: VLSI Design, 2004. Proceedings, 17th International
Conference, Print ISBN: 0-7695-2072-3.
[3] McMahon, Anthony , O'Keeffe, Niall, Keane Kevin ,O'Reilly, James., “The development of advanced verification environments
using System Verilog “Published in: Signals and Systems Conference, 208. (ISSC 2008). IET Irish, page(s) 325-330, print ISBN:
978-0-86341-931-7
[4] S. Iman., "Step-by-step functional verification with SystemVerilog and OVM", Hansen Brown Publishing, ISBN-10: 0-9816562-
1-8, May 2008.
[5] Jae-Beom Kim, Nam-Do Kim, Byeong Min., “Beyond UVM for practical SoC verification” soc design conference (isocc), 2011
international conference, page 158-162, E-ISBN: 978-1-4577-0710-0
[6] T Lakshmi Priyanka, G .Deepthi, B. Sunil Kumar., “Reusable Test bench for Network on Chip Router using Advanced
VerificationMethodologies” International Journal of Science and Modern Engineering (IJISME) ISSN: 2319-6386, Volume-1,
Issue-9, August 2013.
[7] M. Bechtel Brabi and Dr. A. Rajalingam., ” Recent survey for Bi-Directional network on chip pipelined architecture”
International journal of Advanced Research in computer science and Software Engineering, Volume-2, issue-12.
[8] Ying-CherngLan, Hsiao-An Lin, Shih-Hsin Lo , Yu Hen Hu, Sao-Jie Chen., “A Bidirectional NOC architecture with dynamic
self-reconfigurable channel”, Page(s): 266 – 275, E-ISBN : 978-1-4244-4143-3, Print ISBN: 978-1-4244-4142-6
[9] Mr. Ashish Khodwe , Prof. C.N. Bhoyar., “Efficient FPGA Based Bidirectional Network on Chip Router through Virtual
Channel reulator” Proceedings of 2nd
International Conference on Emerging Trends in Engineering and Management , ICETEM
2013.
[10] Baoxian Zhang, JieHao, and Hussein T. Mouftah., “Bidirectional Multi-Constrained Routing Algorithms”, ISSN :0018-9340,
Date of Publication :07 March 2013.
[11] Xu Chen, Zheng Xi, and Xin-An Wang., “Development of verification environment for AXI Bus using system Verilog”,
International Journal of Electronics and Electrical Engineering, Vol. 1, No. 2, pp. 112-114, June 2013. doi:
10.12720/ijeee.1.2.112-114.
[12] Pan Guoteng, Luo Li, OuGuodong, Fu Qingchao, Bai Han., “ Design and verification of a MAC controller based on AXI bus”,
Page(s):558 – 562, Print ISBN:978-1-4673-4893-5