Karthik Vathool Jambunatha Ramani is pursuing a Master's degree in Electrical Engineering from the University of Maryland with a focus on microelectronics. He has over 3 years of experience as a Product Engineer at Cypress Semiconductor Corporation in India where he led projects involving product engineering, failure analysis, and characterization. He is skilled in languages like C, Python, Verilog HDL and has experience with chip design platforms, testing equipment, and software packages like Cadence, LabView and MATLAB.

1. KARTHIK VATHOOL JAMBUNATHA RAMANI
📧 jrkarthik.91@gmail.com || 📱 (240) 535-1474 || linkedin.com/in/jrkv13
Education
University of Maryland College Park, MD
Master’s Degree, Electrical Engineering – [Microelectronics] [CGPA - 3.85/4.0] Expected May ‘17
Courses: Semiconductor Device Modelling and Fabrication, Computer Architecture, Digital and Analog IC Design,
and High-Performance Electronic Package Design.
National Institute Of Technology Trichy, India
Bachelor’s Degree, Electronics & Communication Engineering [CGPA - 8.94/10] June ‘09– May ‘13
Courses: VLSI Design, Device Physics, and Electronic Packaging.
Technical Skills
Computer Languages : C, Python, PERL, Verilog HDL, X86 assembly
Tester platform : Versatest V3300, Nextest Magnum
Chip Platforms : Programmable SoC, SRAM, CMOS Image Processors
Lab skills : Micro-Probing, Soldering, PCB Design, Device Characterization
Software Packages : LabView, Cadence PSPICE, JMP, Microsoft Office, ModelSim, MATLAB
Experience
Failure Analysis Intern June ‘16– Aug ‘16
ON Semiconductor San Jose, CA
● Performed Optical, Physical and Electrical Failure Analysis for 10+ Customer Returns of image sensors products.
Identified the Root Cause of the Failure and implemented corrective actions.
Product Engineer June ‘13– July ‘15
Cypress Semiconductor Corporation Bangalore, India
● Product owner for 7 Programmable SoC products; Optimized production loss through Back-End Process
monitoring, Implemented Production Test programs, improved Yield (~4%)and Average Outgoing Quality(AOQ).
● Project owner for Automotive grade IC Qualification of a SoC product. Planned and executed all stages of Product
Engineering, from Fabrication to Product Change Notice (PCN).
● Debug Owner for 50+ Customer Failure Analysis cases. Performed Electrical Fault isolation (D.O.E) and
implementing of Root Cause Corrective Actions (RCCA) in time bound manner (Avg EFA cycle time <2 weeks).
● Lead Characterizing Engineer for 2 SoC products. Designed and Automated bench/ATE set-ups for characterizing
complete datasheet parameters (Timing, Functional Validation, and Parametric).
● Implemented statistical quality enhancement technique “Part Average Testing (AEC-Q001)” for 7 Automotive
SoC products at wafer level testing, to reject abnormal dies for improving chip reliability.
● Developed “Self-Monitored Intelligent Burn-In” for electrical stressing of all components of the chip, to
accelerate silicon failures. Implemented test programs to identify and remove ‘weaker’ ICs before shipment.
SoC Design Intern May ‘12– June ‘12
Morphing Machines (P) LTD Bangalore, India
● Designed a 163 bit ASIC Encryption co-processor in HDL which executed Elliptic Curve Cryptography
operations in a secure and efficient manner. Developed optimized hardware algorithms and validated the design.
Technical Projects
Analog IC Design of Pattern Recognizing Chip Jan ‘16– May ‘16
● Independently designed a complete Analog Chip in low power mode, which can “learn” signal patterns in a set of
noisy analog channels, and detect the same with high accuracy (100%) with least power (450µW).
Investigation on Embedded Die Packaging Sep ‘15– Dec ‘15
● Analyzed various Embedded Die Package designs, with emphasis on design merits, manufacturing challenges,
process flow, reliability, current applications, and future trends in Embedded Packaging.
Hardware Assisted Hardware Simulation Jan ‘13– May ‘13
● Developed a software module in CUDA to emulate the electrical characteristics of asynchronous circuits in GP-
GPU. Proved that computational efficiency of electrical simulation could be exponentially increased (>2000x) by
exploiting the massive parallel computing power of GPUs.
Honors and Awards
● Graduate Teaching Assistant, Department of Physics, UMD ‘16
● Graduate Research Assistant, Semiconductor Device Research Laboratory, UMD ‘15
● Best New College Graduate group, Cypress Semiconductor ‘14
● Organizing head, All India Inter NIT Sports Meet, NIT-T ‘13
● University Badminton Champion and Team Captain, NIT-T ‘12, ‘13
● A.I.E.E.E Merit scholarship, Ministry of Education, Govt. of India ‘09, ‘10, ‘11