- Graphene was synthesized on copper foil using chemical vapor deposition. Wet transfer methods leave behind metal impurities and unintentionally dope the graphene, reducing its mobility. - The Standard Clean 2 (SC2) solution, which is an acidified hydrogen peroxide solution, was developed to transfer graphene. It efficiently etches away metal impurities, resulting in higher quality graphene with low doping. - Raman spectroscopy analysis of graphene transferred with SC2 and a standard wet transfer method showed SC2 yielded lower defect density graphene. However, further electrical characterization of the graphene in transistors is needed to determine which method provides higher carrier mobility.

1. SC2 Transfer of Chemical Vapor Deposition Single Layer Graphene
Pradeepkumar Govindaswamy, Dr. Ji Ung Lee
SUNY College of Nanoscale Science and Engineering, Albany NY-12203
Abstract
• Wet transferring is currently the most effective method of
transferring graphene from Cu foil to SiO2.
• It achieves a clean and efficient transfer of graphene
without degrading the quality of graphene, however, it
leaves metal impurities and unintentionally p-type doping
which cause a considerable change in the mobility of the
graphene.
• The Standard Clean 2 (SC2) solution is an acidified
Hydrogen Peroxide solution, which is a mixture of Hydrogen
Peroxide, Hydrochloric Acid and Water and has the ability to
protonate all metals thereby efficiently etching them which
will result in higher quality graphene with exceptionally low
metal impurities and p-type doping..
• The SC2 transfer was developed with different ratios of SC2
concentration and the quality of the graphene was analyzed
by optical microscope and Raman spectroscopy.
Growth Process Overview
Raman Spectroscopy
Procedure for SC2 Transfer
Fig 1: Copper
pocket in CVD tool
Fig 2: Optical image
of Single layer
graphene on baked
Copper foil
(x50)
Graphene
CuO
Graphene Transistor Fabrication
References
Graphene
Copper
Graphene
Graphene
Copper
Graphene
PMMA Backside
Graphene etch –
O2 Plasma for 15
sec, 30W RF
Power
Graphene
Copper
PMMA
Summary
Graphene
Copper
PMMA
Thermal Tape
Graphene
Copper
PMMA
Thermal Tape
SC2 Etching Solution
Remove and
place it back
to get rid of
the bubbles
formed.
(X5)
Graphene
PMMA
Thermal Tape
DI Water rinse
and transfer to
SiO2 Substrate
Graphene
SiO2
PMMA
Thermal Tape
Si
Graphene
SiO2
PMMA
Si
Graphene
SiO2
Si
Heat to 200o C Soak in acetone
for 20 minutes
Spin coat PMMA
for 1 min with
2500 rpm
Bake at 75o C for
5 min
0
200
400
600
800
1000
1300 1800 2300 2800
Intensity(a.u.)
Raman shift (cm^-1)
SC2 Transfer
0
200
400
600
800
1000
1300 1800 2300 2800
Intensity(a.u.)
Raman shift (cm^-1)
APS Transfer
SC2 etch at 0 sec SC2 etch at 60 sec
APS transfer on SiO2
Substrate
SC2 transfer on SiO2
Substrate
• Raman Spectroscopy is an
important tool in measuring
the quality of a graphene
layer as well as the number
of graphene layers on a
substrate.
• The graphene layer absorbs
laser photons emitted by the
Raman spectrometer and re-
emits at a certain amount of
energy.
• D peak at ~1360 cm-1
denotes a defect density.
• G-2D ratio is suggestive of
the number of layers in the
flakes.
GGD
2D 2D
D
• Graphene was synthesized on
polycrystalline Copper foil in a
Chemical Vapor deposition tool
(CVD) tool.
• Due to the low solubility of carbon
in copper, the number of layers on
the copper foil can be easily
controlled [2]
• The Cu foil was soaked in acetic
acid for 2 hours or more to etch
away the copper oxide formed on
the surface.
• The foil was then washed with DI
water then with IPA and Acetone
solutions.
• A pocket was prepared and the
edges of the pocket were pressed
down with pliers.
• The Annealing step is crucial which
prepares the surface of the copper
foil for graphene growth by
drastically reducing the number of
nucleation sites for graphene
synthesis to take place.
• Graphene is a single layer two-
dimensional material arranged in a
honeycomb lattice and provides the
feature of having channels that are
just one atomic layer thick for use
in transistors and it has a high
carrier mobility making it one of
the most ideal candidate for next
generation FETs.[1]
(x50)(x50)
Acknowledgement
• A ratio of 1:1:20 of H2O2: HCl: H2O was optimized to get efficient
transfer without graphene degradation.
• The optical data of the transferred SC2 and APS etch single layer
graphene, promises the possibility of utilizing the SC2 transfer
method.
• Different optimization experiment was run by changing the first
exposure time and development time to optimize the fabrication
with AZ5206 photoresist.
1. Schwierz, F. (2010). Graphene transistors. Nature Nanotechnology,
5(7), 487–496-487–496. doi:10.1038/nnano.2010.89
2. Yang, X., Peng, H., Xie, Q., Zhou, Y., & Liu, Z. (n.d.). Clean and
efficient transfer of CVD-grown graphene by electrochemical
etching of metal substrate. Journal of Electroanalytical Chemistry,
688, 243-248. doi:10.1016/j.jelechem.2012.09.025
3. Schmidt, H., Rode, J., Smirnov, D., & Haug, R. (2014). Superlattice
structures in twisted bilayers of folded graphene. Nature
Communications Nat Comms, 5742-5742.
• Raman spectroscopy analysis is not enough to
distinguish which transfer method yields more
quality graphene. Therefore the transferred
graphene have to be electrical characterized, where
the data will be used to calculate carrier mobility of
the graphene sheets.
• This requires graphene sheet to be fabricated into
rectangular transistors and the width and the
biasing voltage can be used to calculate the carrier
mobility.
• For the fabrication process, first mark aligners are
patterned with contact aligner and Ti/Au is deposited
with 5nm/60nm thickness with E-beam evaporator.
Mask for electrodes (4 probe
measurement)
Mask for electrodes (2 probe
measurement)
Electrode Patterning
with AZ5206
Electrode Patterning
with AZ5212
• Graphene is transferred on to the fabricated mark
aligners with the appropriate transfer process. Then it is
patterned and etched with oxygen plasma into strips of
graphene. Lastly, the electrodes are patterned and
deposited with Ti/Au.
• Image reversal process is used to fabricate the transistor
with the AZ5206 and AZ5214 photoresist.
• P-20 primer and Photoresist were spincoated and soft
baked at 100oC for 60sec. Then for the first exposure, the
substrates were exposed for 8sec with UV light and hard
baked for 120sec at 127oC for the image reversal.
• Then the substrate was flood exposed for 60 seconds and
developed in MIF 300 for 15 seconds.
Dr. Ji Ung Lee lab, Pratik Agnihotri, Prathamesh Dhakras, Zhenjun
Zhang and Suhasini Gattu