The document provides an overview of pass transistor concepts, discussing how nMOS and pMOS transistors function as switches, details on designing logic gates with pass transistors, and the characteristics of inverters using nMOS and CMOS technology. Additionally, it describes the challenges of latch-up in CMOS circuits, outlining the conditions that lead to low-impedance paths between power and ground resulting in excessive current flows. Various technical parameters and operational conditions are analyzed to ensure proper functioning and minimize issues in transistor designs.

1. Pass Transistor

2. Introduction:
• The Pass Transistor concept is based on the use
of relay switches.
• A number of inputs are connected to switches
and only one of the switches is chosen to be
transferred to the output.
• In essence, we have created a Multiplexer

3. Cont….
• MOSFET Acts as Switch
OFF→cut-off Region when 𝑉𝐺𝑆<𝑉𝑡
ON→ Linear(or) Saturation Region when 𝑉𝐺𝑆>𝑉
• MOSFET ON-OFF conditions are used as “Switch”
• Pass Transistor uses a n MOS or p MOS Transistor to
from input node to output node ,under the control of g
output remains in high impedance state when voltage
• The process of transferring the charge from the input n
under the control of gate voltage is called charge steer

4. Cont…
nMOS pass transistor
• The n MOS transistor as shown in figure
• n MOS turns “ON” for high input at the gate
terminal and produces “strong 0” at the drain output.
• nMOS transistor pass a strong 0 but a weak 1

5. Cont…..
P MOS Pass transistor
• The p MOS transistor as shown in figure
• p MOS turns “ON” for low input at the gate
terminal and produces “strong 1” at the drain output.
• p MOS transistor pass a weak 0 but a strong 1

6. Cont….
• Realization of logic gates using pass transistor logic(PTL)
(1).Design of 2 input AND gate using PTL.
(2).Design of 2 input OR gate using PTL.

7. Cont…
3.Design of 2 input XOR gate using PTL.
• It is an array of MOS transistor which are connected in
series and passes /carries logic levels. For example below is
a pass transistor which implement ‘AND’ opearion and
passes logic ‘1’information

8. nMOS Inverter

9. Introduction:
• Generally inverters are basic components for fabricating large
circuits.
• In circuit if we consider
logic ‘1’ means High voltage VDD
logic ‘0’ means low voltage ground (0 volts)
• Voltage transfer characteristics of ideal inverter as shown in figure

10. nMOS Inverter:
• nMOS inverter with resistive load circuit as shown in figure
• This basic inverter requires a transistor with ‘source’
Connected to ground and drain connected to load
‘V𝐷𝐷’ Via a load resistor.
• Here the resistor act as pull up device and N MOS Device act as
pull-down device.
(i) When 𝑉𝑖𝑛=0v,E-NMOSFET is OFF but there is
a conducting path (short circuit path)Between 𝑉𝐷𝐷 and 𝑉𝑜𝑢𝑡
∴ 𝑉𝑜𝑢𝑡= 𝑉𝐷𝐷
(ii)When 𝑉𝑖𝑛= 𝑉𝐷𝐷. E-NMOSFET is ON and there is a
Conducting path between 𝑉𝑜𝑢𝑡and ground.
𝑉𝑜𝑢𝑡= 𝑉𝐷𝐷- 𝐼𝑑𝑠𝑅𝑙
• But fabrication of resistor on ‘si’ substrate is not
Convenient because it occupies large substrate area and results in large am
dissipation.

11. Cont…
• So to solve this problem we use FETS as loads to drive invertors .
(i) When 𝑉𝑖𝑛=0v,E-NMOSFET is OFF but there is
a conducting path (short circuit path)Between
𝑉𝐷𝐷 and 𝑉𝑜𝑢𝑡
∴ 𝑉𝑜𝑢𝑡= 𝑉𝐷𝐷
(ii)When 𝑉𝑖𝑛= 𝑉𝐷𝐷. E-NMOSFET is ON and there is a
Conducting path between 𝑉𝑜𝑢𝑡and ground.
𝑉𝑜𝑢𝑡= 𝑉𝐷𝐷- 𝐼𝑑𝑠𝑅𝑑𝑠
• If input is lower voltage (logic 0 )then inversion layer not get formed, so
zero
• If input is higher voltage(Logic 1),then inversion layer will get formed,
increses,which will decreases output to logic 0

12. Cont….
• Voltage transfer characteristics of nMOS invertor as s
• If input is lower voltage (logic 0) then inversion layer
so drain current will be zero

13. Cont.….
• The 𝑉𝑜𝑢𝑡 vs vin NMOS transfer characteristics are sho
• Note that whenever vin of E-NMOS exceeds its 𝑉𝑡, 𝑉𝑜
• Gain =
𝜕𝑉𝑜𝑢𝑡
𝜕𝑉𝑖𝑛
=
𝜕(𝑉𝐷𝐷−𝐼𝐷𝑅𝐿)
𝜕𝑉𝐺𝑆
=-𝑅𝐿
𝜕𝐼𝐷
𝜕𝑉𝐺𝑆
Gain =-𝑅𝐿𝑔𝑚
We know that 𝑔𝑚 =
𝜕𝐼𝐷𝑆
𝜕𝑉𝐺𝑆
| 𝑉𝐷𝑆=constant
We know that ∴ 𝑔𝑚 =
𝜕𝐼𝐷𝑆
𝜕𝑉𝐺𝑆
=
µ ε𝑖𝑛𝑠 ε0
𝐷
.
𝑊(𝑉𝐺𝑆−𝑉𝑡)
𝐿
𝐼𝑑𝑠 = 𝑘
𝑤
𝐿
𝑣𝑔𝑠 − 𝑣𝑡
2
2

14. Determination of pull-up to pull-down rat
for NMOS inverter driven by another NM

15. Introduction :
• Consider arrangement as shown below in which an in
from the output of another similar inverter.
• When cascading logic devices care must be taken to p
of logic levels i.e design circuit so that 𝑉𝑜𝑢𝑡= 𝑉𝑖𝑛=𝑉𝑖𝑛
Depletion mode transistor 𝑉𝐺𝑆=0v under all conditions

16. Cont….
• Depletion NMOS as a load and enhancement mode N
driver i.eNMOS inverter.
• Assume equal margins around inverter:𝑉𝑖𝑛=𝑉𝑜𝑢𝑡=𝑉𝑖𝑛𝑣
• Both transistor of NMOS inverter are in saturation
𝐼𝑑𝑠 = 𝑘
𝑤
𝐿
𝑣𝑔𝑠 − 𝑣𝑡
2
2
For depletion mode transistor 𝑉 =0v,𝑉 =𝑉

17. Cont….
• ∴ 𝐼𝑑𝑠 = 𝑘
𝑊𝑃.𝑈
𝐿𝑃.𝑈
−𝑉𝑡𝑑
2
2
……………….(1)
• For enhancement mode transistor 𝑉
𝑔𝑠=𝑉𝑖𝑛𝑣
∴ 𝐼𝑑𝑠 = 𝑘
𝑊𝑃.𝑑
𝐿𝑃.𝑑
𝑉𝑖𝑛𝑣 −𝑣𝑡 2
2
……..(2)
Since currents are equal then
𝑘
𝑊𝑃.𝑈
𝐿𝑃.𝑈
−𝑉𝑡𝑑
2
2
= 𝑘
𝑊𝑃.𝑑
𝐿𝑃.𝑑
𝑉𝑖𝑛𝑣 −𝑣𝑡 2
2
[convention Z=
𝐿
𝑊
]
1
𝑧𝑃.𝑈
.
−𝑉𝑡𝑑
2
2
=
1
𝑧𝑃.𝐷
.
𝑉𝑖𝑛𝑣 −𝑣𝑡 2
2
𝑉𝑡𝑑

18. Cont….
• Substitute in typical values
𝑉𝑡=0.2 𝑉𝐷𝐷, 𝑉𝑡𝑑=-0.6 𝑉𝐷𝐷, 𝑉𝑖𝑛𝑣 = 0.5 𝑉𝐷𝐷
∴ 0.5 =0.2+
0.6
𝑧𝑃.𝑈
𝑧𝑃.𝐷
𝑧𝑃.𝑈
𝑧𝑃.𝐷
=2
𝑧𝑃.𝑈
𝑧𝑃.𝐷
=
4
1
• An inverter driven from the output of another should h

19. Determination of pull-up to pull-down ratio for an
NMOS inverter driven through one or more pass
transistor

20.  Determination of pull-up to pull-down ratio for an
NMOS inverter driven through one or more pass
transistor
• It is often the case that two inverters are connected v
switches(pass transistors)
• We are connected that connection of transistors in se
the logic levels into inverter 2
Consider the arrangement shown below. all pass tran
connected to 𝑉𝐷𝐷 so there is a loss of 𝑉𝑡𝑝i.e vin2=𝑉𝐷𝐷
transistor 𝑉𝑡)

21. Cont….
• With input 𝑉𝐷𝐷 if it is at 𝑉𝐷𝐷 then pull-down transisto
but with a low voltage across it.
• It is in its resistive region represented by 𝑅1. mean wh
transistor is in saturation and is represented by curren

22. Cont…
• Consider inverter 1:
Case1:pull up Transistor ,it is a D-NMOSFET where vg
operated directly in saturation region.
𝐼𝑑𝑠 = 𝑘
𝑤
𝐿
𝑣𝑔𝑠 − 𝑣𝑡
2
2
• For depletion mode transistor 𝑉
𝑔𝑠=0v,𝑉𝑡=𝑉𝑡𝑑
• ∴ 𝐼1 = 𝐼𝑑𝑠= 𝑘
𝑊𝑃.𝑈1
𝐿𝑃.𝑈1
−𝑉𝑡𝑑
2
2
• 𝐼1 = 𝐼𝑑𝑠= 𝑘
1
𝑍𝑃.𝑈1
−𝑉𝑡𝑑
2
2
……………….(1)
Case 2: Pull down Transistor ,it is a E-NMOSFET wher

23. Cont…
• ∴ 𝐼𝑑𝑠 = 𝐼1= 𝑘
𝑊𝑃.𝑑1
𝐿𝑃.𝑑1
[(𝑉𝐷𝐷-𝑉𝑡 )𝑉𝑑𝑠1 -
𝑉𝑑𝑠1
2
2
]
𝑅1 =
𝑉𝑑𝑠1
𝐼1
=
1
𝑘
𝑍𝑃.𝐷1
1
[(𝑉𝐷𝐷 −𝑉𝑡 ) −𝑉𝑑𝑠1
2
]
Note:𝑉𝑑𝑠1 is small so ignore
𝑉𝑑𝑠1
2
𝑅1 =
𝑉𝑑𝑠1
𝐼1
=
1
𝑘
𝑍𝑃.𝐷1
1
[(𝑉𝐷𝐷 −𝑉𝑡 )]
…….(2)
• The output of the inverter 1 i.e equations (1) and (2) s
equation
𝑉𝑜𝑢𝑡1=𝐼1.𝑅1=𝑘
1
𝑍𝑃.𝑈1
−𝑉𝑡𝑑
2
2
.
1
𝑘
𝑍𝑃.𝐷1
1
[(𝑉𝐷𝐷 −𝑉𝑡 )]

24. Cont…..
• Consider inverter 2:
Case1:pull up Transistor ,it is a D-NMOSFET where vgs=0
directly in saturation region.
𝐼𝑑𝑠 = 𝑘
𝑤
𝐿
𝑣𝑔𝑠 − 𝑣𝑡
2
2
• For depletion mode transistor 𝑉
𝑔𝑠=0v,𝑉𝑡=𝑉𝑡𝑑
• ∴ 𝐼2 = 𝐼𝑑𝑠= 𝑘
𝑊𝑃.𝑈2
𝐿𝑃.𝑈2
−𝑉𝑡𝑑
2
2
• 𝐼1 = 𝐼𝑑𝑠= 𝑘
1
𝑍𝑃.𝑈2
−𝑉𝑡𝑑
2
2
……………….(4)
Case 2: Pull down Transistor ,it is a E-NMOSFET where
Input=𝑉𝐷𝐷-𝑉𝑡𝑃 first operated in resistive region where
𝑉 <𝑉 -𝑉

25. Cont…
• 𝐼𝑑𝑠 = 𝐼1= 𝑘
𝑊𝑃.𝑑2
𝐿𝑃.𝑑2
[(𝑉𝐷𝐷-𝑉𝑡 )𝑉𝑑𝑠1 -
𝑉𝑑𝑠1
2
2
]
• But 𝑉𝐷𝐷 =𝑉𝐷𝐷-𝑉𝑡𝑃
• 𝐼𝑑𝑠 = 𝐼1= 𝑘
𝑊𝑃.𝑑2
𝐿𝑃.𝑑2
[(𝑉𝐷𝐷-𝑉𝑡𝑃-𝑉𝑡 )𝑉𝑑𝑠2 -
𝑉𝑑𝑠2
2
2
]
𝑅2 =
𝑉𝑑𝑠2
𝐼2
=
1
𝑘
𝑍𝑃.𝐷2
1
[(𝑉𝐷𝐷− 𝑉𝑡𝑃−𝑉𝑡 ) −𝑉𝑑𝑠2
2
]
Note:𝑉𝑑𝑠2 is small so ignore
𝑉𝑑𝑠2
2
• 𝑅1 =
𝑉𝑑𝑠1
𝐼1
=
1
𝑘
𝑍𝑃.𝐷1
1
[(𝑉𝐷𝐷− 𝑉𝑡𝑃−𝑉𝑡 )]
…….(5)
• The output of the inverter 1 i.e equations (4) and (5) s
equation

26. Cont…
• 𝑉𝑜𝑢𝑡2=𝐼2.𝑅2=
𝑍𝑃.𝐷2
𝑍𝑃.𝑈2
.
1
[(𝑉𝐷𝐷− 𝑉𝑡𝑃−𝑉𝑡 )]
.
−𝑉𝑡𝑑
2
2
……(6)
• 𝑉𝑜𝑢𝑡1 = 𝑉𝑜𝑢𝑡2
•
𝑍𝑃.𝐷1
𝑍𝑃.𝑈1
.
1
[(𝑉𝐷𝐷 −𝑉𝑡 )]
.
−𝑉𝑡𝑑
2
2
=
𝑍𝑃.𝐷1
𝑍𝑃.𝑈2
.
1
[(𝑉𝐷𝐷− 𝑉𝑡𝑃−𝑉𝑡 )]
.
−𝑉𝑡𝑑
2
2
𝑍𝑃.𝑈1
𝑍𝑃.𝐷1
(𝑉𝐷𝐷 −𝑉𝑡 )=
𝑍𝑃.𝑈2
𝑍𝑃.𝐷2
(𝑉𝐷𝐷− 𝑉𝑡𝑃−𝑉𝑡 )
• Typical values 𝑉𝑡 =0.2𝑉𝐷𝐷 and 𝑉𝑡𝑃= 0.3𝑉𝐷𝐷
•
𝑍𝑃.𝑈1
𝑍𝑃.𝐷1
(𝑉𝐷𝐷 −0.2 𝑉𝐷𝐷)=
𝑍𝑃.𝑈2
𝑍𝑃.𝐷2
(𝑉𝐷𝐷−0.3 𝑉𝐷𝐷−0.2 𝑉𝐷𝐷)
𝑍𝑃.𝑈1
𝑍𝑃.𝐷1
(0.8 𝑉𝐷𝐷)=
𝑍𝑃.𝑈2
𝑍𝑃.𝐷2
(0.5 𝑉𝐷𝐷)

27. Cont…
∴
𝑍𝑃.𝑈2
𝑍𝑃.𝐷2
=
𝑍𝑃.𝑈1
𝑍𝑃.𝐷1
0.8 𝑉𝐷𝐷
0.5 𝑉𝐷𝐷
𝑍𝑃.𝑈2
𝑍𝑃.𝐷2
=
𝑍𝑃.𝑈1
𝑍𝑃.𝐷1
(1.6)=
𝑍𝑃.𝑈1
𝑍𝑃.𝐷1
(2)
•
𝑍𝑃.𝑈2
𝑍𝑃.𝐷2
=
4
1
(2)
•
𝑍𝑃.𝑈2
𝑍𝑃.𝐷2
=
8
1
• An inverter driven through one or more pass transisto
8

28. CMOS Inverter

29. Introduction:
• Case(1) when 𝑉𝑖𝑛 = o V
NMOS Transistor is OFF
PMOS Transistor is ON
And there is conducting path between 𝑉𝐷𝐷and 𝑉𝑜𝑢𝑡
• Case(2) when 𝑉𝑖𝑛 = 𝑉𝐷𝐷
NMOS Transistor is ON
PMOS Transistor is OFF
And there is conducting path between 𝑉𝑜𝑢𝑡 and ground.
• We have seen that ,the current /voltage relation ships f
MOSFET may
Be written as
• 𝐼 in Linear region

30. Cont…
• 𝐼𝑑𝑠 in saturation Region
𝐼𝑑𝑠= 𝑘
𝑤
𝐿
𝑣𝑔𝑠 − 𝑣𝑡
2
2
• In both case ‘k’ is a technology dependent parameter s
k=
ε0 ε𝑖𝑛𝑠.µ
𝐷
• The factor
𝑤
𝐿
contributes by the geometry of the MOSF
common practice we write β=k
𝑤
𝐿
=
ε0 ε𝑖𝑛𝑠.µ
𝐷
.
𝑤
𝐿
Where ‘β’ for both NMOSFET,PMOSFET are follows
β𝑛
=
ε0 ε𝑖𝑛𝑠µ𝑛
𝐷
.
𝑤𝑛
𝐿𝑛
β𝑝
=
ε0 ε𝑖𝑛𝑠µ𝑝
𝐷
.
𝑤𝑝
𝐿𝑝
s

31. Cont….
• The CMOS Inverter has ‘5’Different Regions of operatio
Region 1:this is the region at which
𝑉𝑖𝑛=0 (logic 0)
NMOS Transistor is OFF
PMOS Transistor is ON
𝑉𝑜𝑢𝑡=𝑉𝐷𝐷 (logic1)
Region 5:this is the region at which
𝑉𝑖𝑛=𝑉𝐷𝐷 (logic 1)
NMOS Transistor is ON
PMOS Transistor is OFF
𝑉𝑜𝑢𝑡=0(logic0)

32. Cont…
• Region 2:In this region the input voltage has
increased to a level which just more than the
threshold voltage of mosfet.
• The N-MOSFET conducts and has a large
voltage between source and drain.so it is in
saturation and acts as current source.
• The P-MOSFET also conducts but with only
a small voltage across it. and is operated in resistive
region .

33. Cont….
• A small current now flows through the inverter from
• Region 4.This is similar to region2 but the roles of ‘PM
MOSFET’ are reversed .
• Small currents flows through inverter from 𝑉𝐷𝐷 to gro

34. Cont…
• Region 3.this is the region at which both MOSFTs are
• The currents in each FET must be same since
FETS are in series so
• 𝐼𝑑𝑠𝑝= −𝐼𝑑𝑠𝑛

35. Cont….
Where
𝐼𝑑𝑠𝑝= 𝛽𝑝
𝑣𝑖𝑛−𝑣𝐷𝐷−𝑣𝑡𝑝 2
2
, 𝐼𝑑𝑠𝑛=𝛽𝑝
𝑣𝑖𝑛−𝑣𝑡𝑛 2
2
• We know that 𝐼𝑑𝑠𝑝= −𝐼𝑑𝑠𝑛
𝛽𝑝
2
. 𝑉𝑖𝑛 −𝑉𝐷𝐷 −𝑉𝑡𝑝 2
=-
𝛽𝑛
2
. 𝑉𝑖𝑛 − 𝑉𝑡𝑛 2
𝑉𝑖𝑛 −𝑣𝐷𝐷 −𝑉𝑡𝑝 =−
𝛽𝑛
𝛽𝑝
𝑉𝑖𝑛 − 𝑉𝑡𝑛
𝑉𝑖𝑛+
𝛽𝑛
𝛽𝑝
𝑉𝑖𝑛 =𝑣𝐷𝐷 + 𝑣𝑡𝑝+
𝛽𝑛
𝛽𝑝
𝑉𝑡n
∴
𝛽

36. Cont….
• But in this region both FETs are in saturation acts as t
sources in series results in unstable condition.
• A change over from one logic level to other logic leve
region.
• If βn= βp and 𝑣𝑡𝑝= -𝑉𝑡n after substituting in eq (1) 𝑉
• At 𝑉𝑖𝑛=
𝑉𝐷𝐷
2
a changeover will occur between the logic
symmetrical about the point at which 𝑉𝑖𝑛=Vout =
𝑉𝐷𝐷
2
point at which two β factors are equal. βn= βp
ε0 εinsµn
D
.
wn
Ln
=
ε0 εinsµp
D
.
wp
Lp

37. BiCMOS Inverter Operation
•Vin =0 V , T4 is OFF so that T2 will be non-
conducting But T3 is ON and supplies current
to the base of T1 which will conduct and act as
a current source to charge the load CL toward
VDD . The output of the inverter will rise to
VDD less the base to emitter voltage VBE of T1.
•Vin =VDD V , T3 is OFF so that T1 will be non-
conducting But T4 is ON and supplies current
to the base of T2 which will conduct and act as
a current sink to discharge the load CL toward
0 v . The output of the inverter will fall to 0 v
plus the collector to emitter voltage VCE of T2.
•T1 and T2 will present low impedances when
turned on into saturation and the load CL wiil
be charge or discharges rapidly.
Inverter1

38.  The output logic levels will be good and
will be close to the rail voltages since
VCEsat is quite small and VBE= 0.7 volts.
The inverter has a high input impedance
and low output impedance.
The inverter has high current drive
capability but occupies a relatively small
area and have high noise margins.
inverter2

39. Final BiCMOS Inverter

40. CMOS Inverter Cross-Sectional view with Latch-up
circuit

41. •Latch-up is defined as the generation of a low-impedance path in CMOS chips
between the power supply (VDD) and the ground (GND) due to the interaction of
parasitic PNP and NPN bipolar junction transistors (BJTs).
•These BJTs form a silicon – controlled rectifier (SCR) with positive feedback and
virtually short circuit VDD to the ground, thus causing excessive current flows and
even permanent device damage.
• Latch-up occurs when:
•When both BJTs conduct, creating low resistance path between VDD and
GND.
•Product of gain of two transistors in the feedback loop is greater than one
(β1 x β2 ≥ 1)

42. In the equivalent circuit:
Q1: vertical bipolar PNP transistor whose base
is formed by the n-well with its base-to-
collector current gain (β1) as high as several
hundred. It is associated with pMOS.
Q2: lateral bipolar NPN transistor whose base
is formed by the p-type substrate with its base-
to-collector current gain (β2) ranging from few
tenths to tens. It is associated with nMOS.
Rwell: the parasitic resistance in the n-well
structure with its value ranging up to 20kΩ.
Rsub: substrate resistance that strongly depends
on the substrate structure with its value
ranging from several hundred to few ohms.
Latch-up Circuit model

43. BiCMOS Latch-up Susceptibility
•A reduction of substrate resistance.
•A reduction of N-well resistance.
•A reduction in both resistances means that a large lateral current is
necessary to invite latch-up and a higher value of holding current is also
required.
• The parasitic (pnp) transistor which is part of the n-well latch circuit has
its beta reduced owing to the presence of n+ buried layer. This has the
effect of reducing carrier life time in the n-base region and this
contributes the reduction in beta.