It is help full to control traffic light.

1. DEI
ITV202Practical
presention
Name-Pooja
Roll no. 1904808

2. Traffic Light Control
• Traffic light help people to move properly in the junction by Stopping
the rule for one side and allowing the other but most of the traffic
lights have fixed time controller which makes the vehicles stop for a
long time during peak hour because of this, traffic congestion is
increased during peak hours. Sensors are used to control the traffic
autonomously.

3. Traffic light

4. Control signal-
• The control signal are 3-light Top light is Red (stop)-middle light is
Yellow (wait) –buttom light is Green (Go) STATES OF TRAFFIC FLOW.
• There are 8-line and at most two way can be safely open.
• In this way a minimum of 4-states are possible for which difference
which will pass through.

5. • In this VLSI design project, we will design an FPGA based traffic lights
controller system which reduces the Waitng time driver during peak
hour. VHDL is used to design FPGA because with VHDL you can
simulate the operation of digital circuit from an easy one to complex
gate.
• Quartus ii-Software is used to design the traffic lights controller
based on VHDL and with the help of Altera FLEX lok chip, the
hardware is created.

7. FPGA
• Field Programmable Gate Array is an IC (Integrated Circuit) which can
be modified by the customer or designer based on their requirements
after manufacturering. In the electronic industry, the based on their
standards and protocols which makes it difficult for the user to
configure it according to their need. This created a requirement for
new hardware which can be configured by the user or design
• FPGA-contains programmable logic blocks and interconnection circuit
which can be modified based on the requirements after
manufacturering.FPGA is cheaper to ASIC (Application –specific
integrated circuit) which is suitable for large scale production.

8. Project Implementation
• Road structure –A complex road is identified and the structure is
recreated and the timing for the light are fixed. The timing is created
wisely to avoid accident in the junction. In our case there are six
traffic ,TR1,TR2,TR3,TR4,TR5,and TR6.TR1and TR2 is the main road for
first junction TR3 and TR4 is the main road for the second junction.
TR5andTR6 are the smaller road
• VHDL model of the controller is created. It consists of clock,
RESET,PEAK, OUTPUT, SENSOR 1 AND SENSOR 2.

9. • Timing Simulation is done to verify the result of the design. Following
are the peak hour set for this project 7-9,12-14 and 17-19.The
simulation is performed for various scenarious.

11. • First cycle –TR1andTR6 are green and others are red TR1 and TR6 will
change to amber after 32s and stays for 4s then red for 2s.
• Second cycle- TR2 and TR4 starts with green for 32s then amber for 4s
at last red for 2s.
• Third cycle- TR3 and TR5(narrow roads) turn green for 16s followed
by amber for 4s and Red for 2s.

12. • After this first cycle is repeated again. Now the simulation is
performed successfully using. Altera FELI*10Kchip. The major
advantage of this design over the conversation system is, it reduces
the waiting time of the driver during the off-peak hours.