The document provides a PSpice transient model for the TPS40428 dual-output synchronous buck controller. The model simulates the controller's startup and response to overcurrent faults and output voltage faults over 1ms. Several parameters can be adjusted to mimic the controller's programmable functions, such as soft start time, fault thresholds, and current sharing gains between phases. Notes provide guidance on running the simulation and interpreting the modeled behavior.

1. TPS40428 Transient Model
U7
TPS40428_TRANS
SS = 0
IOUT_OC_FAULT_RESPONSE1 = 1
TON_RISE1 = 600u
IOUT_OC_FAULT_RESPONSE2 = 1
TON_RISE2 = 600u
IOUT_OC_FAULT_LIMIT1 = 40
API_VAL_EN = 0
IOUT_OC_FAULT_LIMIT2 = 40
VIN_ON = 4.25
VREF_TRIM1 = 0
CH2_CSGAIN_SEL = 3
PGH_HIGH1 = 675M
VREF_TRIM2 = 0
PGH_HIGH2 = 675M
API_VAL_HITH = 0
TON_DELAY1 = 0
PGL_HIGH1 = 558M
IOUT_CAL_GAIN1 = 0.5M
TON_DELAY2 = 0
PGL_HIGH2 = 558M
IOUT_CAL_GAIN2 = 0.5M
UV_FAULT1 = 499.2M
VREF_MARGIN_LOW1 = -2M
VREF_MARGIN_HIGH1 = 2M
UV_FAULT2 = 499.2M
VREF_MARGIN_LOW2 = -2M
API_AVG = 0
PGL_LOW1 = 525M
VREF_MARGIN_HIGH2 = 2M
TOFF_DELAY1 = 0
PGL_LOW2 = 525M
API_EN = 0
OV_FAULT1 = 700.8M
TOFF_DELAY2 = 0
OV_FAULT2 = 700.8M
PGH_LOW1 = 657M PGH_LOW2 = 657M
VIN_OFF = 4
CH1_CSGAIN_SEL = 3
EN_SPS = 1
SYNC
PWM1
PWM2
PWPD
SMBALERT
RT
PGND
AGND
ISH1
ISH2
BP3
BP5
COMP1
COMP2
PMBDATA
VDD
TSNS1
TSNS2
VREF_MARGIN1
VREF_MARGIN2
VSNS1
VSNS2
CNTL1
CNTL2
CS1N
CS1P
CS2N
CS2P
FB1
FB2
PMBCLK
FLT1
FLT2
PG1
PG2
DIFFO1
ADDR0
ADDR1
GSNS1
GSNS2
CNTL2
CNTL1
VREF_MARGIN
Application Notes:
1. The PSpice macromodel for TPS40428 is encrypted and will only run in PSPICE Versions 15.7 and up.
Vout1
1.2V
SW2
SW1
VIN
CS1P
COMP1
FLT1
PWM1
COMP2
CS1N
FB2
Vout2
1.8V
VSNS2
BP5
PG1
BP3
BP5
VIN
PG2
PWM2
BP5
VDD
ISH1
ISH2
CS2P
GSNS2
CS2N
VSNS2
Fsw: 500kHz
PWM1
DIFFO1
FB1
DIFFO1
RT
GSNS1
VSNS1
R1
16.2k
V7
TD = 600u
TF = 20n
PW = 1
PER = 2
V1 = 0
TR = 20n
V2 = 0
CS1N
C63
470p
C16 1u
FLT2
CS1P
R17 49.9
R41
0.5
R16
49.9
C30 1.5n C36
1n
TPS40428
Transient Model
C22
1.5n
R35
4.99k
C11
0.1u
C20 1u
R59 10
R19 1
R44 10
VDD
U5
CSD95378BQ5M
IOUT
1
REFIN
2
ENABLE
3
PGNDD
4
VDD
5
VSW
6
VIN
7
BOOT_R
8
BOOT
9
FCCM
10
TAO
11
PWM
12
PGNDA
13
C19 0.1u
C17 100p
R9
10k
Title
Size Document Number Rev
Date: Sheet of
Datasheet: SLUSBV0 - MAY2014 1.0
DUAL OUTPUT, 2-PHASE, STACKABLE PMBUS SYNCHRONOUS BUCK
D
1 1
Thursday , February 05, 2015
C58
0.1u
C33
ESR = 2m
X = 10
C = 100u
V6
TD = 500u
TF = 20n
PW = 1
PER = 2
V1 = 0
TR = 20n
V2 = 0
C28
100p
R7 40.2k
C2
ESR = 2m
X = 10
C = 22u
VIN
TD = 5u
TF = 10u
PW = 1
PER = 2
V1 = 0
TR = 10u
V2 = 12
R48 280
VIN3
TD = 10u
TF = 100n
PW = 1
PER = 2
V1 = 0
TR = 100n
V2 = 2
C12
0.1u
R60 10
R39 10k
VDD
R3 10k
R2
16.2k
L1
L = 0.47u
DCR = 0.67m
VIN
CS2P
C59
0.1u
C60
470p
CS2N
C15 0.1u
PWM2
R30 10k
VDD
R14 1
VIN2
TD = 10u
TF = 100n
PW = 1
PER = 2
V1 = 0
TR = 100n
V2 = 2
VDD
L2
L = 0.47u
DCR = 0.67m
R11
10k
C64
470p
R38
4.99k
R8 4.99k
C29
3.3n
R10
280
C18 0.1u
C27 3.3n
C44
1n
C62
ESR = 2m
X = 10
C = 100u
R12
121k
R15
121k
R46
0.5
C14 0.1u
U6
CSD95378BQ5M
IOUT
1
REFIN
2
ENABLE
3
PGNDD
4
VDD
5
VSW
6
VIN
7
BOOT_R
8
BOOT
9
FCCM
10
TAO
11
PWM
12
PGNDA
13
R45 10
VIN1
TD = 0
TF = 10u
PW = 1
PER = 2
V1 = 5
TR = 10u
V2 = 5
C35
0.1u
0
C61
470p
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VOUT1
0
VSNS1
VIN
CNTL2
GSNS1
VREF_MARGIN
CNTL1
VSNS2
VOUT2
GSNS2

2. Application Notes:
1. The PSpice macromodel for TPS40428 is encrypted and will only run in PSPICE Versions 15.7 and up.
2. Click PSpice ---> Run (F11) to run the simulation. The simulation runs till 1ms and takes ~ 60 minutes to run on a 2.4GHz machine.
3. TON_RISE is 2.7ms in Factory Default. It is set to 600us for short simulation time, also
Capacitor C11, C12 at BP5 and BP3 value is reduced from 1u to 0.1u
4. In this model, use parameter SS=0 to run the Startup Simulation.
5. To run the simulation directly in steady state without going through startup in order to see steady state information like ripple, switching freq,
load and line transients, set SS=1 and use appropriate initial conditions like the ones shown in the schematic 02_TPS40428_DUAL_STEADY.
6. The PMBUS has not been implemented in the model. However, the model has several parameters that are used to mimic the behaviour of the PMBUS.
The user must carefully enter these values in accordance with the datasheet. A description of these parameters is provided below:
- VIN_ON & VIN_OFF: UVLO limits for VIN
- TON_RISE1 & TON_RISE2: Soft Start Time for CH1 and CH2. In Multiphase Mode, TON_RISE1 is passed to CH2 and TON_RISE2 is ignored.
- TON_DELAY1, TOFF_DELAY1, TON_DELAY2, TOFF_DELAY2: Startup and Shutdown delays for CH1 and CH2. These are integer values between 0 and 7.
- UV_FAULT1, OV_FAULT1 , PGH_HIGH1, PGH_LOW1, PGL_HIGH1, and PGL_LOW1: Fault and PGOOD Limits for CH1
- UV_FAULT2, OV_FAULT2 , PGH_HIGH2, PGH_LOW2, PGL_HIGH2, and PGL_LOW2: Fault and PGOOD Limits for CH2. In Multiphase Mode, CH1 limits are passed to CH2 and CH2 limits are ignored.
- IOUT_CAL_GAIN1 and IOUT_CAL_GAIN2: DCR for CH1 and CH2 inductors. Required for Current Limit calculation. IOUT_CAL_GAIN2 is NOT ignored in Multiphase Mode.
- VREF_TRIM1 and VREF_TRIM2: TRIM for CH1 and CH2. In Multiphase Mode, CH2 value is ignored.
- VREF_MARGIN_HIGH1, and VREF_MARGIN_LOW1: MARGIN_HIGH and MARGIN_LOW for CH1. MARGIN_HIGH1 is a +ve number and MARGIN_LOW1 is a -ve number.
- VREF_MARGIN_HIGH2, and VREF_MARGIN_LOW2: MARGIN_HIGH and MARGIN_LOW for CH2. In Multiphase Mode, CH2 values are ignored.
- IOUT_OC_FAULT_LIMIT1 and IOUT_OC_FAULT_LIMIT2: IOUT_OC_FAULT_LIMIT for CH1 and CH2. In Multiphase Mode, IOUT_OC_FAULT_LIMIT1 is passed to CH2 and IOUT_OC_FAULT_LIMIT2 is ignored.
- IOUT_OC_FAULT_RESPONSE1 and IOUT_OC_FAULT_RESPONSE2: IOUT_OC_FAULT_RESPONSE for CH1 and CH2.
IOUT_OC_FAULT_RESPONSE1/2 = 1 implies Hiccup Mode and IOUT_OC_FAULT_RESPONSE1/2 = 0 implies Latchup mode requiring restart.
In Multiphase Mode, IOUT_OC_FAULT_RESPONSE1 is passed to CH2 and IOUT_OC_FAULT_RESPONSE2 is ignored.
- CH1_CSGAIN_SEL, CH2_CSGAIN_SEL: current-share gain is selected. These are integer values between 0 and 3. CHx_CSGAIN_SEL=0 Gain=50,
CHx_CSGAIN_SEL=1 Gain 40, CHx_CSGAIN_SEL=2 Gain=30 and CHx_CSGAIN_SEL=3 Gain=20 (Default).
- API_VAL_EN: When this bit is high, API valley circuit is enabled.
- API_EN API: When this bit is high, API circuit is enabled.
- API_AVG: When this bit is high, API circuit uses average value of COMP instead of peak value for threshold detection.
- API_VAL_HITH API: valley high threshold (API_VAL_HITH=1, 100mV threshold).
- EN_SPS: Enable smart power-stage
7. Temperature effects, Synchronization and supply currents have not been modeled.
8. In the model, the ON Delay = 50us + TON_RISE * TON_DELAY.
9. FCCM pin of CSD95378B must be tied to VDD
10. For Load transient testcase, the Output capacitance derating must be considered to match the simulation results and test results.
SW2
Vout2
1.8V
VSNS2
CS2N
R17 49.9
R41
0.5
C30 1.5n C36
1n
R35
4.99k
C20 1u
100p
R48 280
R60 10
R39 10k
VIN
VDD
L2
L = 0.47u
DCR = 0.67m
C29
3.3n
C18 0.1u
C62
ESR = 2m
X = 10
C = 100u
CSD95378BQ5M
PGNDD
4
VDD
5
VSW
6
VIN
7
BOOT_R
8
0
0
0
0
0
0
0
0
VOUT2
GSNS2