Moore's Law, which predicted the cost of integrated circuits would be cut in half every 18 months, was driven by improvements in CMOS technology over decades. However, the increasing complexity of 3D CMOS designs means Moore's Law scaling is no longer practical or affordable for most companies. To sustain innovation, the industry will need a new design paradigm focused on lower-cost "mini-fabs" and architectures with security and testability built in.

1. The Limitation of “Moore’s Law” & Future of IC Industry
“Moore’s Law” is an observation by Dr. Gordon Moore of Intel that the cost of “unit bit of a memory
device” can be reduced by half in about every 18 months because of transistor feature size scaling – that
became the basic pricing rule to govern any commodity IC memories. It is not a “Physical Law of
Nature”, but was a self-fulfilling prophecy driving IC industry forward based on CMOS.
2-D (as needed to model the device characteristics) CMOS was then proven to be the only
Device/Process Technology enabling “Moore’s Law” scalability because of “Power Reduction” scalability
– since CMOS draws only switching current and no DC current. Integrated Device Technology (IDT) was
the first pioneer worldwide in early 1980’s to dedicate 100% to develop High-performance CMOS (2-D
starting with >2 microns design rules) products, laying the path for others to follow and making CMOS as
the global industry standard device/process technology.
The end of “Moore’s Law” scalability in CMOS is inevitable: It reflects the Law of Diminishing Returns for
any "Linear (with a fixed paradigm) Scaling" - eventually the costs of additional improvements outweigh
the incremental benefits (or returns) making ROI unattractive. “Moore’s Law” scalability was born with
2-D CMOS and has then been being terminated with 3-D CMOS – the increase of device/process
complexities (thus costs) in 3-D CMOS (needs of 3-D modeling for deep submicron (~/<50nm)
geometries) makes Moore’s Law scalability impractical. Nowadays, only a very few super-corporations
can afford to build cutting-edge 3-D CMOS wafer fabs (at about US$5B). The lack of competitions in IC
industry suffocates innovations. IC industry is suffering from premature aging, fueled by financial games
(more M&A than IPO) instead of innovations (very few startups funded by VC in the past 10 years)!
Yet, Moore's Law scalability for performance improvement and cost reduction concurrently (the first
industry-wide collaboration in human history!) based on CMOS technology (as a common standard) with
Silicon Valley as its global innovation and collaboration center has been the driving force for the
advancement of IC industry worldwide (from 4 microns to ~50 nm feature sizes) progressing accordingly
in the fastest paces for any industry over thirty year since 1980’s with healthy product proliferation
driven mainly by startups – the healthy combination of entrepreneurship (breaking big corporations’
status quos) and innovations to drive a blooming industry. It has been carried out as a good example of
collaborative innovation: Everybody along the supply chain has been collaborating with one another
according to the ITRS (International Technology Roadmap of Semiconductor) with divide-and-conquer
tactics to address all technical challenges concurrently - device modeling, design tool developments,
process materials, manufacturing equipment, packaging, test equipment, manufacturability, quality,
reliability, etc. - beyond the capabilities of a single company.
Without collaborations under some common standards to drive the necessary ecosystem-building to
sustain the whole industry advancement - a non-zero-sum-game paradigm, IC industry could not have
been advancing so fast (following the Moore’s Law prediction)!
Nevertheless, we need a new paradigm for a new-generation of ITRS Roadmap along the line of (1) a
"Mini-Fab" that can cost under $1B – similar to the “Mini Blast Furnace” concept, and (2) a new IC design
architecture with "embedded security and testability" besides performance, robustness and cost.
By Al Kwok (Silicon Valley)
2-D CMOS Yield Guru, IDT (1983 -1988)
Serial entrepreneur (3 IPO & 1 M&A)