3D Integrated Circuits and their economic feasibilityJeffrey Funk
These slides use concepts from my (Jeff Funk) course entitled analyzing hi-tech opportunities to analyze how the economic feasibility of 3D integrated circuits (ICs) is becoming better and this will enable the continuation of Moore’s Law. 3D ICs involve the stacking of transistors and memory cells on top of each other in order to increase the number of transistors per chip area and thus continue Moore’s Law. As opposed to attempting to further reduce the feature sizes, engineers build up. They increase the number of layers of transistors and memory cells just as they have increased the number of layers of metal interconnect. To do this, they connect the different layers of transistors and memory cells with so-called Vias that are fabricated from copper.
IC suppliers began shipping 3D ICs in 2006 and these shipments have gradually grown and expanded from simple structured ICs such as image sensors to power ICs, and more recently memories, microprocessors, and ASICs. It is easier to increase the number of layers on simple than complex structured ICs. The global 3D IC market is expected to grow from $2.21 billion in 2009 to $6.55 billion in 2016 at a compound annual rate of 16.9% from 2011 to 2016.
Although it is hard to compare actual 2D and 3D ICs, simulations allow us to easily do such comparisons. For example, simulations found that chip area is almost 50% less and the metal length is about 28% less for 3D than 2D chips. The shorter metal length means that speeds will be faster since the electrons have less distance to travel. Simulations show that timing delay is 37%, 57% and 65% shorter for 2, 3, and 4-layer 3D ICs, data transfer rates are faster, and operating frequency is about 30% fasters for 3D than 2D ICs. Simulations also show that power consumption is lower for 3D ICs, achieving a 40% reduction with 4-layer 3D ICs as compared to 2D ICs.
Perhaps more importantly, these simulations show that 3D ICs are theoretically cheaper to develop and manufacture. The reason is that 3D ICs can use larger feature sizes than can 2D ICs in order to achieve the same densities of transistors per chip. These larger feature sizes reduce the cost of equipment such as photolithographic equipment, whose costs are rising rapidly. Simulations show that capital costs for 3D ICs are 5% and R&D costs are those of 2D ICs. For manufacturing costs, simulations of flash memory that the advantage of 3D ICs increases as the size of flash memory increases reaching 50% with 256Gb.
All of this suggests that Moore’s Law will continue for many years. Combined with the reductions in feature size that were mentioned earlier from International Technology Roadmap for Semiconductors, there is probably another 10-20 years left in Moore’s Law just from 3D ICs and smaller feature sizes. Nevertheless, challenges remain for 3D ICs. The simulations assume similar yields when in reality it will be harder to achieve similar yields on 3D as 2D ICs given the increa
Conformal electronics and their economic feasiblityJeffrey Funk
These slides use concepts from my (Jeff Funk) course entitled analyzing hi-tech opportunities to analyze how the economic feasibility of conformal electronics is becoming better through using thinner materials, an island-bridge design, and Moore’s Law. The island-bridge design is a mesh of islands containing somewhat rigid components that are connected by mesh of stretchable materials. This enables electronics to be more effectively used in space-restricted places, in skin patches, and next to human organs. Transfer printing, which is a form of roll-to roll printing, enables the costs to be relatively low.
3D Integrated Circuits and their economic feasibilityJeffrey Funk
These slides use concepts from my (Jeff Funk) course entitled analyzing hi-tech opportunities to analyze how the economic feasibility of 3D integrated circuits (ICs) is becoming better and this will enable the continuation of Moore’s Law. 3D ICs involve the stacking of transistors and memory cells on top of each other in order to increase the number of transistors per chip area and thus continue Moore’s Law. As opposed to attempting to further reduce the feature sizes, engineers build up. They increase the number of layers of transistors and memory cells just as they have increased the number of layers of metal interconnect. To do this, they connect the different layers of transistors and memory cells with so-called Vias that are fabricated from copper.
IC suppliers began shipping 3D ICs in 2006 and these shipments have gradually grown and expanded from simple structured ICs such as image sensors to power ICs, and more recently memories, microprocessors, and ASICs. It is easier to increase the number of layers on simple than complex structured ICs. The global 3D IC market is expected to grow from $2.21 billion in 2009 to $6.55 billion in 2016 at a compound annual rate of 16.9% from 2011 to 2016.
Although it is hard to compare actual 2D and 3D ICs, simulations allow us to easily do such comparisons. For example, simulations found that chip area is almost 50% less and the metal length is about 28% less for 3D than 2D chips. The shorter metal length means that speeds will be faster since the electrons have less distance to travel. Simulations show that timing delay is 37%, 57% and 65% shorter for 2, 3, and 4-layer 3D ICs, data transfer rates are faster, and operating frequency is about 30% fasters for 3D than 2D ICs. Simulations also show that power consumption is lower for 3D ICs, achieving a 40% reduction with 4-layer 3D ICs as compared to 2D ICs.
Perhaps more importantly, these simulations show that 3D ICs are theoretically cheaper to develop and manufacture. The reason is that 3D ICs can use larger feature sizes than can 2D ICs in order to achieve the same densities of transistors per chip. These larger feature sizes reduce the cost of equipment such as photolithographic equipment, whose costs are rising rapidly. Simulations show that capital costs for 3D ICs are 5% and R&D costs are those of 2D ICs. For manufacturing costs, simulations of flash memory that the advantage of 3D ICs increases as the size of flash memory increases reaching 50% with 256Gb.
All of this suggests that Moore’s Law will continue for many years. Combined with the reductions in feature size that were mentioned earlier from International Technology Roadmap for Semiconductors, there is probably another 10-20 years left in Moore’s Law just from 3D ICs and smaller feature sizes. Nevertheless, challenges remain for 3D ICs. The simulations assume similar yields when in reality it will be harder to achieve similar yields on 3D as 2D ICs given the increa
Conformal electronics and their economic feasiblityJeffrey Funk
These slides use concepts from my (Jeff Funk) course entitled analyzing hi-tech opportunities to analyze how the economic feasibility of conformal electronics is becoming better through using thinner materials, an island-bridge design, and Moore’s Law. The island-bridge design is a mesh of islands containing somewhat rigid components that are connected by mesh of stretchable materials. This enables electronics to be more effectively used in space-restricted places, in skin patches, and next to human organs. Transfer printing, which is a form of roll-to roll printing, enables the costs to be relatively low.
Moore’s Law is slowing, but more importantly the world is changing from PCs to smart phones and cloud computing where improvements continue to occur. Improvements are still occurring in other types of ICs such as wireless, GPUs, and 3D camera chips because they lag microprocessors and parallel processing is easier on them than on microprocessors. Data centers are also experiencing rapid improvements as changes in architecture are made, particularly for analyzing unstructured data, i.e., Big Data. These slides discuss the implications for new services in areas such as smart phones, software, and Big Data. The last one-third of the slides summarize alternatives to silicon and von Neumann.
3D IC Presented by Tripti Kumari, School of Engineering, CUSATthevijayps
A 3D Integrated Circuit is a chip that has active electronic components stacked on one or more layers that are integrated both vertically and horizontally forming a single circuit.
In the 3-D design architecture, an entire chip is divided into a number of blocks, and each block is placed on a separate layer of Si that are stacked on top of each other.
In a generic 3D IC structure, each die is stacked on top of another and communicated by Through-Silicon Vias (TSVs).
Architectural issues
Traditional shared buses do not scale well – bandwidth saturation
Chip IO is pad limited
Physical issues
On-chip Interconnects become increasingly slower w.r.t. logic
IOs are increasingly expensive
Consequences
Performance losses
Power/Energy cost
Design closure issues or infeasibility
Reduced wire length
Total wire length
Larger circuits produce more improvement
Lower power per transistor
Decreased interconnect delay
Higher transistor packing densities
Smaller chip areas
There are four ways to build a 3D IC:
Monolithic
Wafer-on-Wafer
Die-on-Wafer
Die On Die
At runtime, thermal variations will introduce additional time-varying clock skew, further increasing design uncertainty
2 - Thermal Issues In 3-D ICs
Due to reduction in chip size of a 3D implementation, 3D circuits exhibit a sharp increase in power density
Analysis of Thermal problems in 3D is necessary to evaluate thermal robustness of different 3D technology and design options.
3 - Reliability Issues In 3-D ICs
Electro thermal and Thermo-mechanical effects between various active layers can influence electro-migration and chip performance
Die yield issues may arise due to mismatches between die yields of different layers, which affect net yield of 3D chips.
TSV check on reset
Control use dedicated Vias in order to establish which vias are corrupted.
If 1, 2 and 3 TSVs are OK, the control set the enable signal set_to and set_from: broken path are skipped!
Pads routing shift as show in the figure
Need to define The handling protocol during the TSVs check
3D IC design is a relief to interconnect driven IC design.
Still many manufacturing and technological difficulties
Physical Design needs to consider the multiple layers of Silicon available.
Optimization of both temperature and wirelength
Placement and routing algorithms need to be modified
[1] J. Davis, et al., "Interconnect limits on gigascale integration (GSI) in the 21st century," Proceedings of the IEEE , vol.89, no.3, pp.305-324, Mar 2001.
[2] Banerjee, K.; Souri, S.J.; Kapur, P.; Saraswat, K.C.; , "3-D ICs: a novel chip design for improving deep- submicrometer interconnect performance and systems-on-chip integration," Proceedings of the IEEE , vol.89, no.5, pp.602-633, May 2001.
Moore’s Law is slowing, but more importantly the world is changing from PCs to smart phones and cloud computing where improvements continue to occur. Improvements are still occurring in other types of ICs such as wireless, GPUs, and 3D camera chips because they lag microprocessors and parallel processing is easier on them than on microprocessors. Data centers are also experiencing rapid improvements as changes in architecture are made, particularly for analyzing unstructured data, i.e., Big Data. These slides discuss the implications for new services in areas such as smart phones, software, and Big Data. The last one-third of the slides summarize alternatives to silicon and von Neumann.
3D IC Presented by Tripti Kumari, School of Engineering, CUSATthevijayps
A 3D Integrated Circuit is a chip that has active electronic components stacked on one or more layers that are integrated both vertically and horizontally forming a single circuit.
In the 3-D design architecture, an entire chip is divided into a number of blocks, and each block is placed on a separate layer of Si that are stacked on top of each other.
In a generic 3D IC structure, each die is stacked on top of another and communicated by Through-Silicon Vias (TSVs).
Architectural issues
Traditional shared buses do not scale well – bandwidth saturation
Chip IO is pad limited
Physical issues
On-chip Interconnects become increasingly slower w.r.t. logic
IOs are increasingly expensive
Consequences
Performance losses
Power/Energy cost
Design closure issues or infeasibility
Reduced wire length
Total wire length
Larger circuits produce more improvement
Lower power per transistor
Decreased interconnect delay
Higher transistor packing densities
Smaller chip areas
There are four ways to build a 3D IC:
Monolithic
Wafer-on-Wafer
Die-on-Wafer
Die On Die
At runtime, thermal variations will introduce additional time-varying clock skew, further increasing design uncertainty
2 - Thermal Issues In 3-D ICs
Due to reduction in chip size of a 3D implementation, 3D circuits exhibit a sharp increase in power density
Analysis of Thermal problems in 3D is necessary to evaluate thermal robustness of different 3D technology and design options.
3 - Reliability Issues In 3-D ICs
Electro thermal and Thermo-mechanical effects between various active layers can influence electro-migration and chip performance
Die yield issues may arise due to mismatches between die yields of different layers, which affect net yield of 3D chips.
TSV check on reset
Control use dedicated Vias in order to establish which vias are corrupted.
If 1, 2 and 3 TSVs are OK, the control set the enable signal set_to and set_from: broken path are skipped!
Pads routing shift as show in the figure
Need to define The handling protocol during the TSVs check
3D IC design is a relief to interconnect driven IC design.
Still many manufacturing and technological difficulties
Physical Design needs to consider the multiple layers of Silicon available.
Optimization of both temperature and wirelength
Placement and routing algorithms need to be modified
[1] J. Davis, et al., "Interconnect limits on gigascale integration (GSI) in the 21st century," Proceedings of the IEEE , vol.89, no.3, pp.305-324, Mar 2001.
[2] Banerjee, K.; Souri, S.J.; Kapur, P.; Saraswat, K.C.; , "3-D ICs: a novel chip design for improving deep- submicrometer interconnect performance and systems-on-chip integration," Proceedings of the IEEE , vol.89, no.5, pp.602-633, May 2001.
Hardware Complexity of Microprocessor Design According to Moore's Lawcsandit
The increasing of the number of transistors on a chip, which pl
ays the main role in improvement
in the performance and increasing the speed of a microproc
essor, causes rapidly increasing of
microprocessor design complexity. Based on Moore’s Law the
number of transistors should be
doubled every 24 months. The doubling of transistor count affects i
ncreasing of microprocessor
design complexity, power dissipation, and cost of design effort
.
This article presents a proposal to discuss the matter of sca
ling hardware complexity of a
microprocessor design related to Moore’s Law. Based on the dis
cussion a hardware complexity
measure is presented.
INCREASING THE TRANSISTOR COUNT BY CONSTRUCTING A TWO-LAYER CRYSTAL SQUARE ON...ijcsit
According to the Moore’s law, the number of transistor should be doubled every 18 to 24 months. The main
factors of increasing the number of transistor are: a density and a die size. Each of them has a serious physical limitation; the first one “density” may be reached “Zero” after few years, which causes limitation
in performance and speed of a microprocessor, the second one “die size” cannot be increased every 2
years, it must be fixed for several years, otherwise it will affect the economical side. This article aims to
increase the number of transistors, which increase the performance and the speed of the microprocessor
without or with a little bit increasing the die size, by constructing a two-layer crystal square for transistors,
which allows increasing the number of transistors two additional times. By applying the new approach the
number of transistors in a single chip will be approximately doubled every 24 months according to Moore’s
Law without changing rapidly the size of a chip (length and width), only the height of a chip must be
changed for putting the two layers.
Two-Layer Crystal Square for Transistors on a Single Chipcsandit
The number of transistors on a chip plays the main
role in increasing the speed and performance of a
microprocessor; more transistors, more speed. Incre
asing the number of transistors will be limited due
to
the design complexity and density of transistors. T
his article aims to introduce a new approach to
increasing the number of transistors on a chip. The
basic idea is to construct two-layer crystal squar
e for
transistors; this allows to increase the number of
transistors two additional times (four times as man
y) if
the number of transistors incorporated in a one lay
er of crystal square will approximately double ever
y 24
months according to Moore’s Law without changing ra
pidly the design complexity and density in a crysta
l
square and without changing the size of a chip (len
gth and width), in this case the height of a chip m
ust be
changed for the two layers.
Design and test challenges in Nano-scale analog and mixed CMOS technology VLSICS Design
The continuous increase of integration densities in Complementary Metal–Oxide–Semiconductor (CMOS) technology has driven the rapid growth of very large scale integrated (VLSI) circuit for today's high-tech electronics industries from consumer products to telecommunications and computers. As CMOS technologies are scaled down into the nanometer range, analog and mixed integrated circuit (IC) design and testing have become a real challenge to ensure the functionality and quality of the product. The first part of the paper presents the CMOS technology scaling impact on design and reliability for consumer and critical applications. We then propose a discussion on the role and challenges of testing analog and mixed devices in the nano-scale era. Finally we present the IDDQ testing technique used to detect the most likely defects of bridging type occurring in analog CMOS circuits during the manufacturing process and creating a resistive path between VDD supply and the ground. To prove the efficiency of the proposed technique we design a CMOS 90nm operational amplifier (Opamp) and a Built in Current Sensor (BICS) to validate the technique and correlate it with post layout simulation results.
Moore’s Law Effect on Transistors EvolutionEditor IJCATR
With respect to time increasing in the number of transistors has a great effect on the performance and the speed of
processors. In this paper we are comparing the transistors evolution related to Moore’s law. According to the Moore’s law the
number of transistors should be double every 24 month. The effect of increasing processors design complexity also increases the
power consumption and cost of design efforts. In this paper we discuss the methods and procedures to scale the hardware complexity
of processors.
A Survey Paper on Leakage Power and Delay in CMOS Circuitsijtsrd
Power consumption is one of the top issues of VLSI circuit design, for which CMOS is the primary technology. Today’s focus on low power is not only because of the recent growing demands of mobile applications. Even before the mobile era, power consumption has been a fundamental problem. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between power, delay and area and thus, designers are required to choose appropriate techniques that satisfy application and product needs. In this paper we study different author’s paper to relate to this problem and try to find out the best solution for future work. Vidhyasagar Chaudhary | Dr. Neetesh Raghuwanshi "A Survey Paper on Leakage Power and Delay in CMOS Circuits" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-5 | Issue-4 , June 2021, URL: https://www.ijtsrd.compapers/ijtsrd43615.pdf Paper URL: https://www.ijtsrd.comengineering/electronics-and-communication-engineering/43615/a-survey-paper-on-leakage-power-and-delay-in-cmos-circuits/vidhyasagar-chaudhary
TRACK D: Advanced design regardless of process technology/ Marco Casale-Rossi
Miniturization of CMOS devices
1. Miniaturisation in cMOS: Past and Future
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Miniaturisation in cMOS: Past and Future
Abstract
Computer chips can be found in almost every modern electronic device. Over the years since their
introduction they have become smaller, cheaper and more efficient, however there are limitations on
the rates of improvements that can be made to the devices. The performance of these integrated
circuits has been improving exponentially for over 40 years. In the coming years, the semi-conductor
industry must overcome several issues in order to maintain the impressive pace of improvements
made by manufacturers. The design process of CMOS devices introduces challenges in lithography,
scaling, connection, memory and circuit design, in order to maintain the pace of improvements,
solutions to such challenges must be met (Isaac, 2000).
2. Miniaturisation in cMOS: Past and Future
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Introduction
CMOS (complementary metal-oxide semiconductor) chips use complementary and symmetrical pairs
of p/n-type metal oxide semiconductor field effect transistors to perform logic functions (Sago, 2013).
The productivity of integrated circuits has improved by 25%-30% annually (Peercy, 2000), following
Moore’s Law which states that the number of transistors per square centimetre doubles every 12
months for silicon based integrated circuits. This rate of improvement discussed by Peercy is
impressive, such rates of technological advancement can’t be found in many other applications.
According to research from IBM by Randall Isaac, transistors in 1999 operate 20 times faster occupying
less than 1% of the area than those built in the 1980’s, as Isaac states this level of size reduction at
such a rate is unsustainable, in order to continuously maintain such a development rate companies
must invest large amounts of resources in cutting edge and innovative technology. The number of
components in a device directly effects the device performance, as the number of components
increases the processing power of the device increases. The increase in components per device is
largely due to the improvements in the lithographic process as well as more innovative techniques for
component formation on a device. Moore pointed out that as a result of increasing the number of
components per chip, the cost per component decreased, assuming that the increase in cost of
fabricating a chip is lower than the increase in the number of components.
The evolution of transistors used in CMOS integrated circuits was predicted with a high degree of
accuracy in 1972 at the IEEE International Electron Devices Meeting by Dennard et al. (Dennard,
Gaensslen, Kuhn, & Yu, 1972) In which they put forward a scaling theory which has driven transistor
design ever since its introduction. For any given scaling reduction factor α, Dennard et al. showed how
the voltage and levels of doping could be modified to increase the power by a factor of α, decrease
the power by a factor of α2
and keep the power density constant (Peercy, 2000). Table 1 below shows
the effect of the scaling factor α on some key device parameters, it is clear that the size of the device
has a direct effect on identifying features of the device. The lower voltage is important as it prevents
dielectric breakdown, a lower gate delay results in faster devices and a lower current means that the
device consumes less power, so it’s less likely to overheat. It is clear from the effect of the device
scaling that miniaturization in CMOS devices is something the industry aims to continue until it reaches
its limitations as it means faster, smaller and more efficient devices. This is not to say that there are
no drawbacks to using smaller and smaller devices, as CMOS devices continue to scale leakage current
becomes more and more of a major contributor to the total power consumption of the device. To
manage the increase in leakage current as devices become smaller, solutions for the leakage reduction
problem must be sought in the coming years; such solutions may well be found within in engineering
/ manufacturing techniques or at the circuit design level.
Parameter Before Scaling After Scaling
Channel Length L L / α
Channel Width W W / α
Oxide Thickness TOX Tox / α
Power Supply Vdd Vdd / α
Voltages Vto Vto / α
Current I I / α
Oxide Capacitance C C * α
Power / Unit Area P P
Gate Delay τ τ / α
Table 1 – Effects of scaling on some key device parameters (Singh & Moyal, 2014)
3. Miniaturisation in cMOS: Past and Future
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Device scaling is predicted to reach approximately 10nm nodes in the years 2016-2018, the ITRS
(International Technology Roadmap for Semiconductors) is a group of semiconductor industry experts
that have suggested by 2018 the industry will be producing 8nm nodes, “heralding the era of
nanotechnology” (Michelen, 2013). The node size is the smallest feature in a transistor. Moore’s law
is predicted to come to an end soon, the semiconductor industry is reaching the limit at which the
lithographic process can be used in the standard way, as devices become smaller and smaller the
conventional processes will not hold.
Past Devices
The microprocessor was invented in 1971, in this time the clock speed has increased from
approximately 0.108MHz in 1971, to around 3.5GHz in 2013 (that’s an increase of over 32,000 times
the original speed). The clock speed is, in layman’s terms, a measure of how often we can give a
processor instructions and still have “failure free” operations (Mattson, 2014), for a 3GHz processor
allows us to give it 3 billion operations per second and will still perform as predicted.
Figure 1 shows Moore’s Law, which explores the number of transistors in Intel’s microprocessors over
the years, we can see that this development has followed Moore’s law of doubling every 2 years. The
astounding evolution of the devices are made viable by frequent downsizing of the CMOS
semiconductors, as they become smaller, they also become cheaper, use less power, and operate
faster.
The evolution of CMOS scaling has been achieved by downsizing the components of the device, in the
middle of the 1980’s 1μm was seen to be the limit due to a predicted problem in optical Lithography
amongst other predicted limitations (Iwai, 2003), over time this limit has been re-evaluated and has
been surpassed multiple times due to innovation within the industry and various technological
advancements. Table 2 shows the predicted downsizing limits over the past 45 years, as the table
suggests, each time a prediction of a limit was made it has been surpassed and appears to be
continuing to do so into nanotech devices.
Figure 1 – Moore’s Law
4. Miniaturisation in cMOS: Past and Future
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Year Expected Limit Size
1971 10μm
1975 3μm
1982 1.5μm
1985 1μm
1989 800nm
1994 600nm
1995 350nm
1998 250nm
1999 180nm
2000 130nm
2002 90nm
2006 65nm
2008 45nm
2010 32nm
2011 22nm
2013 16nm
2016 11nm
Table 2 - Predicted limitations for downsizing (Siti, Binti, Habibah, Mamun, & Syedul, 2012)
One of the biggest challenges facing the industry in the past was that as the size of devices
continuously decreased, the conductors became too resistive, in order to solve this problem the
aluminium in the devices was replaced with copper, to reduce this resistivity (Michelen, 2013) at the
end of the period of what was effectively just simply scaling down devices using more advanced
lithography techniques (in around 2002).
Future Devices & Challenges
From 2002 devices began reaching beyond the 90nm mark, at this point scaling was not enough to
keep up the almost exponential development in technology, some innovation is required to keep up
the pace of development and keep the industries profits up. Some solutions explored and utilised by
the industry included computational lithography, hi-K metal gates and tri-gate transistors (Michelen,
2013). Perhaps the most important modern development in the field is the use of III-IV elements in
place of the channel, this is an important development as it allows integration of dissimilar materials
with silicon to enhance the performance of devices (Kazior, 2014). Beyond this stage (predicted to be
around 2018, as can be seen in Figure 2) the industry will have to invent new materials and
technologies, such as those seen in nano-electronics, in which carbon based materials are being
developed to design future devices.
Nano-electronics allows manipulation on dimensions of less than 100nm to create electronic
structures, the technology is emerging, innovative, and well-funded, although it is no emerging as
fast as the semi-conductor industry would like. In order for the technologies to be developed in a
time frame that the industry would like (as soon as possible realistically), they must collaborate
together. The use of graphene in devices is being widely researched, prototype structures are being
created by various industry leaders and researchers (Novoselov, et al., 2012), graphene is a gapless
semiconductor, causing problems for digital logic functions although proving useful for analogue
device applications such as low-noise amplifiers and millimetre-wave field-effect transistors (FETs)
(Banerjee, Register, Tutuc, & Basu, 2010).
5. Miniaturisation in cMOS: Past and Future
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Figure 2 – Feature size over time for Semiconductors (Michelen, 2013)
Nanoscale MOSFETs aren’t without their problems, table 3 below shows several key issues and their
solutions:
Problem Solution Advantages of the solution
Poor Electrostatics Double Gate Ability to retain gate control over
channel
Minimize OFF-state drain-source
leakage
Poor Channel Transport High Mobility Channel High mobility
High drive current, low intrinsic
delay
Source / Drain parasitic
resistance
Metal Schottky source
/ drain
Reduced extrinsic resistance
Gate leakage increased High-K dielectrics Reduced gate leakage
Gate depletion Metal gate High drive current
Table 3 – problems within nanotech devices and their solutions
Conclusion
The rate at which microprocessor & semiconductor technology has developed is astounding,
Moore’s law has been successful in predicting the development of devices for over 40 years
although it is now appearing to reach its limitations. Further funding for research into nano-
technology must be made available in order to develop technologies which will allow for the future
miniaturisation of devices which will still prove useful, powerful and reliable to their respective
applications. Graphene structures such as nano-tubes are providing promising research to say that it
is a recent technological development, and should provide exciting results prior to 2020, it seems
intuitive to suggest that any company which successfully develops a way to provide graphene with a
bandgap to allow for digital logic fabrication will be the industry leader for years to come.
6. Miniaturisation in cMOS: Past and Future
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Bibliography
1) Banerjee, S., Register, L., Tutuc, E., & Basu, D. (2010). Graphene for CMOS and Beyond CMOS
Applications. 98(12).
2) Dennard, R. H., Gaensslen, F. H., Kuhn, L., & Yu, H. N. (1972). Design of Micron MOS
Switching Devices. IEEE.
3) Isaac, R. D. (2000, May). The Future of CMOS Technology. IBM J. Res. Development Vol 44.
4) Iwai, H. (2003). Scaling toward sub 10nm regime. EEE International Symposium on Electron
Devices for Microwave and Optoelectronic Applications, 11.
5) Kazior, T. E. (2014). Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and
other dissimilar materials/devices with Si CMOS to create intelligent microsystems.
Philosophical Transactions. Mathematical, Physical and Engineering Sciences.
6) Mattson, P. P. (2014, November 13). Why Haven’t CPU Clock Speeds Increased in the Last
Few Years? . (COMSOL) Retrieved March 9, 2016, from COMSOL:
https://www.comsol.com/blogs/havent-cpu-clock-speeds-increased-last-years/
7) Michelen, A. (2013, February 13). 2018: The End of Easy Scaling and the Dawn of
Nanotechnology. (IHS) Retrieved March 9, 2016, from Electronics 360:
http://electronics360.globalspec.com/article/16/2018-the-end-of-easy-scaling-and-the-
dawn-of-nanotechnology
8) Novoselov, K. S., Fal'ko, V. I., Colombo, L., Gellert, P., Schwab, M., & Kim, K. (2012). A
Roadmap for Graphene. (7419).
9) Peercy, P. S. (2000, August 31). The Drive to Miniturization . Nature vol 406, pp. 1023-1026.
10) Sago, W. (2013, March). What is CMOS Memory? . Retrieved from Wicked Sago blog:
http://wickedsago.blogspot.co.uk/2011/04/what-is-cmos-memory.html
11) Singh, S. K., & Moyal, V. (2014). MOSFET Scaling and Small Geometry Effects.
12) Siti, S., Binti, S., Habibah, M., Mamun, M., & Syedul, A. (2012). Cmos Downsizing: Present,
Past And Future. 8(8), 4138-4146.