Resume

1. Aaditya Goyal
https://in.linkedin.com/in/aaditya-goyal-82303734
401, Anderson Street, Apt# 4P (979)-739-9287
College Station, TX-77840 aaditya_goyal@tamu.edu
OBJECTIVE Seeking an Internship/Co-op for Summer 2017 in the field of ASIC/VLSI Digital Design/ Verification &
Computer Architecture.
EDUCATION Texas A&M University, College Station, Texas May 2018(expected)
Master of Science in Computer and Electrical Engineering
Overall GPA: 4.0/4.0
Indian Institute of Technology, Mandi (IIT Mandi), Himachal Pradesh, India June 2013
Bachelor of Technology in Electrical Engineering
Overall GPA: 3.75/4.0
RELEVANT MS: Digital integrated Circuit Design, Computer Architecture, Intro to Hardware Verification, Microprocessor
COURSES Systems and Design, Low Noise Electronic Design.
B.Tech: Computer Organization & Microprocessor, Digital System Testing and Testable Design, Digital
Signal Processing, Power Electronics, Computer Systems and Programming, Digital Image Processing.
PROJECTS Texas A&M University, College Station, Texas Sept 2016 – Nov 2016
Design and Layout of 8 bit Pipelined Adder using buffered H-Clock Tree:
• Designed the schematic and layout for an 8-bit Pipelined Adder using Cadence Virtuoso.
• Reduced the delay in critical path by performing Logic Effort and Gate Sizing.
• Standard cell characterization with Timing Analysis and Power Dissipation using Cadence Spectre.
• Implemented Buffered H-Clock tree for clock synchronization and minimize clock skew.
RTL Design and Verification of 5-Stage Pipelined MIPS Processor:
• Designed and synthesized a 5 stage Pipelined MIPS Processor using Verilog.
• Implemented data forwarding and hazard detection units to improve CPI.
• Added support for static branch prediction, exception handling and subroutine calls.
RTL Design of Cruise Control Circuit for a vehicle:
• Designed automatic cruise control system for a vehicle and verified its functionality using NC-Verilog.
• Synthesized and generated netlist for cruise control logic unit using Synopsis Design Vision.
• Performed Static Timing Analysis (STA) using Synopsis Primetime Tool and determined the slack.
• Layout generation by automatic place and route using SoC Encounter.
IIT Mandi, Himachal Pradesh, India August 2012 – March 2013
• Advanced Car Security System: Used to track and send the location of the car to the owner’s mobile
whenever needed. In case of emergency or collision, send the location to nearest hospital and police
station. Also implemented the feature of theft control. (similar to the Safety Connect feature by Toyota).
FINISAR, Ipoh, Malaysia June 2015
• Test Time Reduction Project: Reduced test time of a particular test process by 30% by coming up
with the new tester setup for production released product.
WORK FINISAR, Ipoh, Malaysia, Product Engineer Nov 2013- Nov 2015
EXPERIENCE • Debugged and verified the transceivers for the PCBA and EEPROM related issues.
• Worked towards Yield Improvement, Cost Reduction and Test Time Reduction for XFP and QSFP
Transceivers at NPI and at Production stage.
TECHNICAL Verilog HDL, C++, Python, SQL, Assembly Language Programming, Matlab, Xilinx ISE, NC-Verilog,
SKILLS Cadence Virtuoso, Cadence Spectre, Cadence SoC Encounter, Synopsys Design Vision, Synopsys
Primetime, Mars, AVR Studio, Winspice, Tina TI, Proteus, Keil, JMP
LEADERSHIP At Finisar Malaysia, led a team of 15 technicians for many projects like Burn In Time Reduction, Test
SKILLS Time Reduction, Verification of new tester setup, etc.
AWARDS & First Price the Drill Competition in N.C.C.
ACHIEVEMENT Black Belt in Karate.
WORK Eligible to work in United States with OPT and CPT (F1 Visa).
AUTHORIZATION