1. YOGENDRI
H.No - 176 Range Colony Bhartoll, Bareilly
PIN - 243001
Email- yogendri123@gmail.com
CAREER OBJECTIVE
To work for an organization which provides me the opportunity to improve my skills and knowledge and where
my skills can be utilized for improvement and success of the organization.
ACADEMICS DETAILS
Year Degree/Exam Institute Percentage/CGPA
2016 M.Tech (VLSI Design) National Institute of Technology, Kurukshetra 8.63 till 3rd
sem.
2013 B.Tech (ECE) SRMSCET, Bareilly 77.50
2009 AISSCE Army School Bareilly Cantt 89.20
2007 AISSE Kendriya Vidyalaya No.1 Delhi Cantt 81.40
SCHOLASTICS ACHIEVEMENTS
 GATE (organized by IITs and IISc Banglore) : Two times qualified, achieved 2989 rank in 2014
 Received scholarship from SRMS Trust, Bareilly for academic performance
 Received merit scholarship from AWES for academic performance
 Won 2nd
prize in “ROBO WAR” in LAKSHYA-2011 a national level technique fest held at INVERTIS
UNIVERSSITY, Bareilly on 14.10.2011.
PROJECTS & PAPERS
 M.Tech Thesis: Layout designing of High Performance of 8,16, 32-bit Vedic multipliers using
180nm PDK of SCL Mohali using Cadence’s EDA Tools
In this project
 Low power and high speed multiplier is designed based on ancient Vedic mathematics with the help
of 180nm PDK of SCL (Semiconductor Lab, Mohali).
 Low power, high speed 20T Full adder is used for the addition of partial products. DRC and LVS
clean layouts are made and PEX is done using Calibre to calculate results for post-layout simulation
and simulation is done using Hspice simulator.
 Delays of interconnects are reduced by making compact layout.
Finally, I/O and power pads were added to the 8-bit Vedic multiplier and its layout has been
given for chip fabrication to the Semiconductor Lab, Mohali.
Guided by: Dr. Anil K. Gupta, Professor & Co-ordinator SVDE, NIT Kurukshetra
 B.Tech Project: Image Compression using MATLAB using DWT
In this project Image compression is done using HAAR wavelet transform on MATLAB to reduce
irrelevance and redundancy of image data in order to store or transmit data in an efficient form.
 Worked under the suggestions (or guidance) of SCL Lab, Mohali for making Layout.
 Research Publication on “Design of High Performance 8-bit Vedic multiplier (using UMC 180nm
technology)”, Yogendri, Dr. A.K.Gupta has been presented and published in IEEE ICACCA-2016
Conference.
 Research Publication on “Design of High Performance 16-bit Vedic multiplier (using SCL PDK
180nm technology)”,Yogendri, Dr. A.K.Gupta has been presented and published in AEEES-2016
National Conference at NIT Hamirpur.
 Presented seminar on Image Compression using DWT in MATLAB in National conference on
“ADVANCES IN ELECTRONICS & COMMUNICATION (AECT-2013).

2.  Other Projects:
 Double Gate MOSFET using Sentaurus TCAD.
 Digital Design Synthesis - Sine wave generation using Verilog.
 Electronic Voting Machine using 7493 Ripple Counter.
 Image Watermarking using DWT in MATLAB.
 Design of 6T SRAM using Hspice.
TECHNICAL SKILLS
 Programming Language : Basics of C, MATLAB, Verilog.
 Software : Cadence Virtuoso (Full Custom Layout Design), LT spice, Xilinx, ModelSim, Calibre,
Hspice, Spectre, L-edit, Sentaurus TCAD.
SUMMER INTERNSHIP
 Organization : ALTTC Ghaziabad
Duration : 4 weeks (18 June- 11 July 2012)
Brief description : Learnt the basics of Mobile communication & communication technologies
 Organization : HP India Education Services
Duration : 4 weeks (10 June- 23 July 2011)
Brief description : Learnt the basics of Microcontroller ATMEGA 16L
AREA OF INTEREST
 Digital Electronics and Design
 Analog Communication
EXTRA CO-CURICULAR ACTIVITIES & HOBBIES
 Worked as an organizer in SAMADHAN committee in National level Sport and Technical fest in 2011.
 Participated in death race in Robotics in technical fest TECHVYOM held at SRMSCET.
Participated and qualified for final round of “Roadies” at NIT Kurukshetra.
 Hobbies: Drawing, Painting, Craft work.
PERSONAL PROFILE
 Name: Yogendri
 Fathers’s Name: Ram Singh
 DOB: 03/01/1992
 Gender: Female
 Mobile No: 09457200308, 09728431816