Probe Card Cost Drivers from Architecture to Zero Defects - IEEE Semiconductor Wafer Test Workshop 2011 presentation by Ira Feldman (www.hightechbizdev.com)
1. June 12 to 15, 2011
San Diego, CA
Probe Card Cost Drivers from
Architecture to Zero Defects
Ira Feldman
Feldman Engineering Corp.
Overview
• Cost, Price, & Cost Drivers
• Serial Processing – Drilling Example
• NRE
• Advanced Process Technology
• Profitless Prosperity
• Cost Savings
• Summary
Note: price/cost examples are approximate and from multiple
vendors not necessarily those identified or shown.
June 12 to 15, 2011 IEEE SW Test Workshop 2
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2. Price
Value
Cost
Gross Profit = Price – Cost
Gross Margin = Gross Profit / Price
June 12 to 15, 2011 IEEE SW Test Workshop 3
Vertical Probe Head
Printed Circuit Board
BGA (Solder Attach)
Space Transformer
Upper
Guide Plate
Spacer
Lower
Guide Plate
MicroProbe Apollo Probes
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3. Machine Shop
Cost Drivers
Programming
Material
Setup Time
Run Time
Inspection
Yield
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Don’t bother… “Ferrari”
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4. Machine Cost $300,000 Machine Cost
Annual Maintenance 7% 25% utilization $31.44 /hr
Useful Life 7 years 85% utilization $9.25 /hr
Total Cost $447,000
Facilities Annual Cost $35,000 Tooling per hole $ 0.05
Total Annual Cost $68,857
Don’t bother… “Ferrari”
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Make vs. Buy
Utilization
Lead Time
Quality
Fixed vs. Variable Cost
Cost (Make) vs. Price (Buy)
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5. Non Recurring Engineering
Expense
Architecture Design Tester Customer
R&D NRE NRE NRE
Design Input X X
Probes ?
Guide Plates X
Space Transformer X
Interposer ?
PCB Design X (External?) X ?
PCB Fab External ? ?
Mechanical
M h i l H/W ? X ?
Electronics
Metrology
Packaging
NRE ?
X
?
X
X
?
?
?
June 12 to 15, 2011 IEEE SW Test Workshop 9
Outgoing Metrology
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6. ISC
Interposers
Spring Pin Elastomeric Molded Frame
NRE $.5 - 1 K $2 - 3 K $20 - 30 K
Small Area
$ / contact $1 - 10 $.50 60
$ 50 - .60 < $.20 - .40
$ 20 40
Large Area NRE $10 - 15 K $100 - 150 K
(1/4 wafer +)
$ / contact $.40 - . 50 < $.10 - .20
www.ksdk.co.jp ISC InterCon Systems
June 12 to 15, 2011 IEEE SW Test Workshop 11
Space Transformers
Sequential
Punch
Material &
Processing
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7. Advanced Process Technology
Cost Drivers
Process Steps
Masks
Substrates
Material
Active Area
Yield
Defect Density
Layers
Equipment
Rework / Repair
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Whitespace
Design 1 Design 2
Design 1 Design 2
FormFactor Harmony XP
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8. Solution
FormFactor Smart Matrix
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FORM – 9 years; MJC – 5 years; JEM- 5 years; VRGY - 7 years
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9. Costs Savings
STANDARDS
Input Data Formats
Probe Depth
Testhead Configurations
Specifications
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Summary
• Understand true cost of architectures
– Beware of NRE
– New architectures needed for cost reductions
• Maintain sufficient Gross Margin
– Company health
– Funding for R&D
• Honest supplier – customer partnerships
June 12 to 15, 2011 IEEE SW Test Workshop 18
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10. Acknowledgments
• Amphenol InterCon Systems
• BucklingBeam
• FormFactor
• ISC
• Kern
• Robin McAdams
• MicroProbe
• Sergio Perez
• SV Probe
• Frank Swiatowiec
June 12 to 15, 2011 IEEE SW Test Workshop 19
Thank You!
Ira Feldman
ira@feldmanengineering.com
Visit my blog
www.hightechbizdev.com
www.hightechbi dev.com
for my summary of SWTW
June 12 to 15, 2011 IEEE SW Test Workshop 20
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