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嵌入式系統 課程講義

This document provides an overview of an introductory lecture on embedded systems and ARM processors. It discusses the ARM instruction set, versions of ARM including ARM7, and ARM's design philosophy which emphasizes portability, limited memory, and price sensitivity for embedded applications. The goal is high code density and total effective system performance while minimizing power consumption.

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1 UEE1076 Introduction to Embedded Systems Lecture 1 Introduction YuLun Huang http://rtes.cn.nctu.edu.tw UEE 3303 <1> YL Huang Spring‘14 © NCTU What is a computer? ° Components: • Input (mouse, keyboard) • Output (display, printer) • Memory (disk drives, DRAM, SRAM, CD) • Network ° Our primary focus: the processor (datapath and control) • Implemented using millions of transistors • Impossible to understand by looking at each transistor • We need … UEE 3303 <2> YL Huang Spring‘14 © NCTU What are embedded computing systems? ° Processing Unit: CPU • On-chip memory • Off-chip memory ° Input: mouse, keyboard ° Output: screen ° Memory and storage ° Communication (data): NIC ° Software UEE 3303 <3> YL Huang Spring‘14 © NCTU Definition ° Embedded computing system: • Any device that includes a programmable computer but is not itself a general-purpose computer ° Take advantage of application characteristics to optimize the design: • Don’t need all the general-purpose bells and whistles UEE 3303 <4> YL Huang Spring‘14 © NCTU
2 Embedding a computer CPU output analog input mem analog embedded computer UEE 3303 <5> YL Huang Spring‘14 © NCTU The History ° System ° Systom on Board ° System on Chip (SoC) ° … ° MCU • Memory embedded ° MPU • High frequency • External memory required UEE 3303 <6> YL Huang Spring‘14 © NCTU Examples ° Cell phone ° Printer ° Automobile: engine, brakes, dash, etc ° Airplane: engine, flight controls ° Digital television ° Household appliances UEE 3303 <7> YL Huang Spring‘14 © NCTU Early history ° Late 1940’s: MIT Whirlwind computer was designed for real-time operations • Originally designed to control an aircraft simulator ° First microprocessor was Intel 4004 in early 1970’s. ° HP-35 calculator used several chips to implement a microprocessor in 1972 ° Automobiles used microprocessor-based engine controllers starting in 1970’s • Control fuel/air mixture, engine timing, etc. • Multiple modes of operation: warm-up, cruise, hill climbing, etc. • Provides lower emissions, better fuel efficiency UEE 3303 <8> YL Huang Spring‘14 © NCTU
3 Instruction Set Architecture ° A very important abstraction • interface between hardware and low-level software • standardizes instructions, machine language bit patterns, etc. • advantage: different implementations of the same architecture • disadvantage: sometimes prevents using new innovations True or False: Binary compatibility is extraordinarily important? ° Modern instruction set architectures: • IA-32, PowerPC, MIPS, SPARC, ARM, and others UEE 3303 <9> YL Huang Spring‘14 © NCTU CISC vs. RISC ° CISC emphasizes hardware complexity. RISC emphasizes compiler complexity. CISC emphasizes hardware complexity. RISC emphasizes compiler complexity. RISC processor: simpler; the core can operate at higher clock frequencies. CISC processor: more complex and operate at lower clock frequencies. UEE 3303 <10> YL Huang Spring‘14 © NCTU The Instruction Set: a Critical Interface instruction set software hardware R12 = R14 – R15 11100000010011101100000000001111 UEE 3303 <11> YL Huang Spring‘14 © NCTU MIPS R3000 Instruction Set Architecture (Summary) ° Instruction Categories • Load/Store • Computational • Jump and Branch • Floating Point - coprocessor • Memory Management • Special Registers R0 - R31 PC HI LO 3 Instruction Formats: all 32 bits wide OP OP OP rs rt rd sa funct rs rt immediate jump target UEE 3303 <12> YL Huang Spring‘14 © NCTU
4 ISA in a System Application Compiler Operating System Firmware Instr. Set Proc. I/O system Datapath & Control Digital Design Circuit Design Instruction Set Architecture Layout ° Coordination of many levels of abstraction ° Under a rapidly changing set of forces ° Design, Measurement, and Evaluation UEE 3303 <13> YL Huang Spring‘14 © NCTU
1 DCN2561 Computer Architecture Lecture 2 Instructions: Language of the Computer YuLun Huang rtes.cn.nctu.edu.tw UEE 3303 <1> YL Huang Spring‘14 © NCTU von Neumann architecture ° Central processing unit (CPU) fetches instructions from memory. • Separate CPU and memory distinguishes programmable computer. ° CPU registers help out: program counter (PC), instruction register (IR), general-purpose registers, etc. ° Memory holds data and instructions. UEE 3303 <2> YL Huang Spring‘14 © NCTU Registers vs. Memory ° MIPS: arithmetic instructions operands must be registers, — only 32 registers provided ° Compiler associates variables with registers ° What about programs with lots of variables Control Datapath Memory Input Output Processor I/O UEE 3303 <3> YL Huang Spring‘14 © NCTU Memory Organization ° Viewed as a large, single-dimension array, with an address. ° A memory address is an index into the array ° "Byte addressing" means that the index points to a byte of memory. 0 1 2 3 4 5 6 ... 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data UEE 3303 <4> YL Huang Spring‘14 © NCTU
2 Memory Operands ° Complex data structures – array/structures – are kept in memory ° Arithmetic operations occur only on registers in MIPS instr. • MIPS must include instructions that transfer data between memory and registers - Data transfer instructions • To access a word in memory, the instruction must supply the memory ‘address’ UEE 3303 <5> YL Huang Spring‘14 © NCTU Byte vs. Word ° Bytes are nice, but most data items use larger "words" ° For MIPS, a word is 32 bits or 4 bytes. 0 4 8 12 ... 32 bits of data Word must start at addr 32 bits of data the are multiples of 4 32 bits of data 32 bits of data Registers hold 32 bits of data ° 232 bytes with byte addresses from 0 to 232-1 ° 230 words with byte addresses 0, 4, 8, ... 232-4 ° Words are aligned i.e., what are the least 2 significant bits of a word address? - Left most: big endian - Right most: little endian UEE 3303 <6> YL Huang Spring‘14 © NCTU Instructions ° Load and store instructions ° Example: C code: A[12] = h + A[8]; MIPS code: lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 48($s3) 1. h is associated with $s2 2. base addr of array A is in $s3 ° Can refer to registers by name (e.g., $s2, $t2) instead of number ° Store word has destination last ° Remember arithmetic operands are registers, not memory! Can’t write: add 48($s3), $s2, 32($s3) UEE 3303 <7> YL Huang Spring‘14 © NCTU So far ° Instruction Meaning add $s1,$s2,$s3 $s1 = $s2 + $s3 sub $s1,$s2,$s3 $s1 = $s2 – $s3 lw $s1,100($s2) $s1 = Memory[$s2+100] sw $s1,100($s2) Memory[$s2+100] = $s1 bne $s4,$s5,L Next instr. is at Label if $s4 ≠ $s5 beq $s4,$s5,L Next instr. is at Label if $s4 = $s5 j Label Next instr. is at Label ° Formats: ? op rs rt rd shamt funct op rs rt 16 bit address op 26 bit address R I J R: register I: immediate UEE 3303 <8> YL Huang Spring‘14 © NCTU
3 Assembly Language vs. Machine Language ° Assembly provides convenient symbolic representation • much easier than writing down numbers • e.g., destination first ° Machine language is the underlying reality • e.g., destination is no longer first ° Assembly can provide 'pseudoinstructions' • e.g., “move $t0, $t1” exists only in Assembly • would be implemented using “add $t0,$t1,$zero” ° When considering performance you should count real instructions UEE 3303 <9> YL Huang Spring‘14 © NCTU Other Issues ° Discussed in your assembly language programming lab: support for procedures linkers, loaders, memory layout stacks, frames, recursion manipulating strings and pointers interrupts and exceptions system calls and conventions ° Some of these we'll talk more about later ° We’ll talk about compiler optimizations when we hit chapter 4. UEE 3303 <10> YL Huang Spring‘14 © NCTU Overview of MIPS ° simple instructions all 32 bits wide ° very structured, no unnecessary baggage ° only three instruction formats op rs rt rd shamt funct op rs rt 16 bit address op 26 bit address R I J ° rely on compiler to achieve performance — what are the compiler's goals? ° help compiler where we can UEE 3303 <11> YL Huang Spring‘14 © NCTU
1 UEE3303 Introduction to Embedded Systems Lecture 3 ARM YuLun Huang http://rtes.cn.nctu.edu.tw Ď UEE 3303 <1> YL Huang Spring ‘14 © NCTU ARM instruction set ° ARM versions ° ARM assembly language ° ARM programming model ° ARM memory organization ° ARM data operations ° ARM flow of control UEE 3303 <2> YL Huang Spring ‘14 © NCTU ARM versions ° ARM architecture has been extended over several versions • ARM7 • ARM9/9E • ARM10E • ARM11 • Cortex • SecurCore ° We will concentrate on ARM7 UEE 3303 <3> YL Huang Spring ‘14 © NCTU ARM11 FamilyĎ CatchĎ Tightly Couple MemoryĎ Memory ManagementĎ AHBĎ Thumb Ď DSP Ď Jazelle Ď ARM11MP Core Ď MM U+cache coherency Ď 1× or 2×AMBA AXI Ď v Ď v Ď v Ď ARM1136J (F)-S Ď variable Ď v Ď MMU Ď 5×AHB Ď vĎ v Ď v Ď ARM1156T 2(F)-S Ď variable Ď v Ď MPU Ď 3×AXI Ď v Ď v Ď x Ď ARM1176J Z(F)-S Ď variable Ď v Ď MMU+ TrustZone Ď 4×AXI Ď v Ď v Ď v Ď UEE 3303 <4> YL Huang Spring ‘14 © NCTU
2 ARM Design Philosophy Ď° Many physical features drove the ARM processor design: • Portability (require some form of battery power): smaller - reduce power consumption and extend battery operation -essential for applications (eg. PDAs). - more available space for specialized peripherals (low cost) • Limited Memory (due to cost and/or physical size restrict) - High code density • Price sensitive: - Use slow and low-cost memory devices ° ARM core: not a pure RISC architecture due to the constraints of its primary application - the embedded system. • In some sense, the strength of the ARM core is that it does not take the RISC concept too far. ° The key is not raw processor speed but total effective system performance and power consumption. UEE 3303 <6> YL Huang Spring ‘14 © NCTU UEE 3303 <5> YL Huang Spring ‘14 © NCTU ARM vs. MIPSĎ ° ⎰Ἕ㊯Ẍ • MIPS ㊯Ẍ⣒忶䯉╖炻ARM㊯Ẍ▿娎⎴㗪⬴ㆸ怷廗嗽䎮冯䦣 ỵ嗽䎮 ° 忋临屯㕁嗽䎮 • 慵㕘姕妰ġlw/swġ㊯Ẍ炻ἧ℞⎗ẍ忋临⁛廠屯㕁炻㍸ὃ屯㕁䘬 ⁛廠㓰䌯 ° 㡅ẞ⺷㊯Ẍ • ὅ㒂⇵朊➟埴䳸㝄㰢⭂㗗⏎➟埴娚㊯Ẍ炻啱ẍ㍸檀㊯Ẍ䘬➟ 埴㓰䌯 ° 䯉妨ᷳ, ARM ㍉䓐悐↮ġRISC 姕妰㤪⾝: • Load-store architecture • Fixed-length 32-bit instructions • 3-address instruction format ARM Design Philosophy Ď° The ARM instruction set differs from the pure RISC definition in several ways that make the ARM instruction set suitable for embedded applications: • Variable cycle execution for certain instructions • Inline barrel shifter leading to more complex instructions • Thumb 16-bit instruction set • Conditional execution • Enhanced instructions ° These additional features have made the ARM processor one of the most commonly used 32-bit embedded processor cores. Ď UEE 3303 <7> YL Huang Spring ‘14 © NCTU High Code Density?Ď ° Two types of instruction sets - Subset of ARM instructions ARMĎ ThumbĎ • ARM instructions: 32 bit • Thumb instructions: 16 bits Length/instructionĎ 32 bitĎ 16 bitĎ Number of Instr.Ď NĎ 1.4NĎ Code sizeĎ K Ď 0.7KĎ Code DensityĎ LowĎ High Performance (16bit memory)Ď PĎ 1.43P (faster) UEE 3303 <8> YL Huang Spring ‘14 © NCTU
3 Different ARM cores: StrongARM vs. XscaleĎ CatchĎ Tightly Couple MemoryĎ Memory Mangem entĎ AHBĎ Thumb Ď DSP Ď Jazelle Ď Strong ARM Ď 16K/8K Ď xĎ MMU Ď N/A Ď xĎ xĎ xĎ XScale Ď 32K/32K Ď xĎ MMU Ď N/A Ď vĎ vĎ xĎ UEE 3303 <9> YL Huang Spring ‘14 © NCTU ARM ArchitectureĎ ° 7 modes • usr – normal execution • sys – privileged OS tasks • fiq – fast interrupt • irq – general interrupt • svc – protected mode for OS • abt – vir mem (mem protect) • und – for s/w emulation ° 37 registers • 30: general purpose • 6: status • 1: program counter UEE 3303 <10> YL Huang Spring ‘14 © NCTU ModesĎ ModeĎ CodeĎ DescriptionĎ User (usr)Ď 10000Ď Normal mode; only condition flags in cpsr can be changedĎ FIQ (fiq)Ď 10001Ď Fast interruptĎ IRQ (irq)Ď 10010Ď Normal interruptĎ Supervisor (svc)Ď 10011Ď OS kernelĎ Abort (abt)Ď 10111Ď Memory protectionĎ Undefined (und)Ď 11011Ď Software emulationĎ System (sys)Ď 11111Ď Normal mode, but be able to r/w cpsrĎ UEE 3303 <11> YL Huang Spring ‘14 © NCTU RegistersĎ ° ARM 嗽䎮☐㚱ġ37ġᾳ㙓⬀☐炻⊭㊔ • [15] 30ᾳ忂䓐㙓⬀☐ • [1] 1 PC • [1] 6ġᾳ䉨ン㙓⬀☐烉CPSR x 1 + SPSR x 5 ° ARM 㚱ġ7ġ䧖ⶍἄ㧉⺷ • 㭷ᶨ䧖㧉⺷ᶳ悥㚱ᶨ䳬䚠⮵䘬㙓⬀☐冯ᷳ⮵ㅱ UEE 3303 <12> YL Huang Spring ‘14 © NCTU
4 ARM Register OrganizationĎ UEE 3303 <13> YL Huang Spring ‘14 © NCTU ARM registersĎ ° There are up to 17 active registers: • 16 data registers and 2 processor status registers • data registers are visible to the programmer as R0 to R15 - R0 ~ R7：不分組暫存器，真正的通用暫存器。 - R8 ~ R14：分組暫存器，與處理器模式有關。 ° three special registers: R13, R14, and R15 • R13 - stack pointer (sp), stores the head of the stack in the current processor mode • R14 - link register (lr), where the core puts the return address whenever it calls a subroutine • R15 - program counter (pc), contains the address of the next instruction to be fetched by the processor ° R13 and R14 can also be used as general-purpose registers, but DANGEROUS!! ° One more register: PSR Ď UEE 3303 <14> YL Huang Spring ‘14 © NCTU ARM registersĎ ° two program status registers (PSR): CPSR and SPSR • current program status registers烉⃚⬀䚖⇵䉨ン炻⏓㕿㧁ˣᷕ㕟ỵ⃫… • saved program status registers烉ᾅ䔁ġCPSRġ䘬䉨ン ° The register file contains all the registers available to a programmer ° Which registers are visible to the programmer depend upon the current mode of the processor. UEE 3303 <15> YL Huang Spring ‘14 © NCTU Example: When FIQ Exception Occurs..Ď UEE 3303 <16> YL Huang Spring ‘14 © NCTU
5 Then, the ARM processorĎ ° When an exception occurs, the ARM core: • SPSR_fiq ← CPSR • Set CPSR bits - T: thumb or arm - Mode = 10001 (fiq) - Disable interrupt, if appropriate • Map registers • LR_fiq ← PC • PC ← 0x0000 001c (vector address) ° To return, the exception handler need to: • CPSR ← SPSR_fiq • PC ← LR_fiqĎ UEE 3303 <17> YL Huang Spring ‘14 © NCTU ARM programming model R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC) 31 0 CPSR N Z C V N: Negative/Less Than Z: Zero C: Carry/Borrow/Extend V: OverflowĎ T:ġ嬻嗽䎮☐⎗ẍ冒䓙⛘⛐ ARMġ␴ġThumbġᷳ攻↯㎃Ď UEE 3303 <18> YL Huang Spring ‘14 © NCTU Endianness ° Relationship between bit and byte/word ordering defines endianness: bit 31 bit 0 bit 0 bit 31 byte 3 byte 2 byte 1 byte 0 byte 0 byte 1 byte 2 byte 3 little-endian big-endian UEE 3303 <19> YL Huang Spring ‘14 © NCTU ARM data types ° Word is 32 bits long ° Word can be divided into four 8-bit bytes ° ARM addresses cam be 32 bits long ° Address refers to byte • Address 4 starts at byte 4 ° Can be configured at power-up as either little- or big-endian mode UEE 3303 <20> YL Huang Spring ‘14 © NCTU
6 ARM status bits ° Every arithmetic, logical, or shifting operation sets CPSR bits: • N (negative), Z (zero), C (carry), V (overflow) ° Examples: • -1 + 1 = 0: NZCV = 0101 • 231-1+1 = 231: NZCV = 0000 • -2 + -5 = -7: NZCV = 1010 • N is set as bit 31 • Z is set result is 0 • V is set when the register cannot properly represent the result as a signed value (you overflowed into the sign bit). • C is set when the register cannot properly represent the result as an unsigned value (no sign bit required). Ď UEE 3303 <21> YL Huang Spring ‘14 © NCTU Carry vs. Overflow (8-bit examples): generic conceptĎ ° Unsigned operation: 0x70 + 0x68 = 0xD8 • No carry, no oVerflow ° Unsigned operation: 0xC0 + 0xD8 = 0x98 • Carry, but no oVerflow • Sign of the result is correct • The "correct" answer is actually 0x198. ° Signed operation: -0x40 + -0x28 = -0x68 • No carry, no "oVerflow" • Result of the arithmetic is correct ° Signed operation: 0x70 + -0x98 = 0x28 • No carry, but oVerflow • The answer is obviously wrong • The V flag reveals that the "correct" answer is -0x28.Ď UEE 3303 <22> YL Huang Spring ‘14 © NCTU ARM InstructionsĎ UEE 3303 <23> YL Huang Spring ‘14 © NCTU ARM ASM Ď .text ; Executable code follows _start: .global _start ; "_start" is required by the linker .global main ; "main" is our main program b main ; Start running the main program main: ; Entry to the function "main" ; Insert your code here mov pc,lr ; Return to the caller .endĎ UEE 3303 <24> YL Huang Spring ‘14 © NCTU
7 Types of ARM InstructionsĎ ° Arithmetic operations ° Comparisons (no results - just set condition codes) ° Logical operations ° Data movement between registersĎ UEE 3303 <25> YL Huang Spring ‘14 © NCTU Arithmetic OperationsĎ ° Syntax • <Operation>{<cond>}{S} Rd, Rn, Operand2 ° Operations are • ADD operand1 + operand2 • ADC operand1 + operand2 + carry • SUB operand1 - operand2 • SBC operand1 - operand2 + carry -1 ° Examples ADD r0, r1, r2 SUBGT r3, r3, #1 UEE 3303 <26> YL Huang Spring ‘14 © NCTU ComparisonsĎ ° The only effect of the comparisons is to • UPDATE THE CONDITION FLAGS. (no need to set S bit.) ° Syntax: • <Operation>{<cond>} Rn, Operand2 ° Operations are: • CMP operand1 - operand2, but result not written • CMN operand1 + operand2, but result not written • TST operand1 AND operand2, but result not written • TEQ operand1 EOR operand2, but result not written ° Examples: CMP r0, r1 TSTEQ r2, #5Ď UEE 3303 <27> YL Huang Spring ‘14 © NCTU Logical OperationsĎ ° Syntax: • <Operation>{<cond>}{S} Rd, Rn, Operand2 ° Operations are: • AND operand1 AND operand2 • EOR operand1 EOR operand2 • ORR operand1 OR operand2 • BIC operand1 AND NOT operand2 [ie bit clear] ° Examples AND r0, r1, r2 BICEQ r2, r3, #7 EORS r1,r3,r0Ď UEE 3303 <28> YL Huang Spring ‘14 © NCTU
8 Data MovementĎ ° Syntax: • <Operation>{<cond>}{S} Rd, Operand2 ° Operations are: • MOV operand2 • Note that it makes no use of operand1. ° Examples: MOV r0, r1 MOVS r2, #10 UEE 3303 <29> YL Huang Spring ‘14 © NCTU GCD in CĎ int gcd(int a, int b){ int c; while ( a != b) { if (a > b) c = a - b; else c = b-a; b = a; a = c; } return a; } UEE 3303 <30> YL Huang Spring ‘14 © NCTU Convert & Replace variables with registersĎ UEE 3303 <31> YL Huang Spring ‘14 © NCTU ARM CodeĎ gcd cmp r0, r1 ;reached the end? beq stop blt less ;if r0 > r1 sub r0, r0, r1 ;subtract r1 from r0 bal gcd less sub r1, r1, r0 ;subtract r0 from r1 bal gcd stop UEE 3303 <32> YL Huang Spring ‘14 © NCTU
9 ARM Conditional Assembler Ďgcd cmp r0, r1 ;if r0 > r1 subgt r0, r0, r1 ;subtract r1 from r0 sublt r1, r1, r0 ;else subtract r0 from r1 bne gcd ;reached the end?Ď UEE 3303 <33> YL Huang Spring ‘14 © NCTU QEMU EMULATORĎ UEE 3303 <34> YL Huang Spring ‘14 © NCTU ARM EmulatorĎ ° QEMU • an emulator that emulate real machines • supported platforms: arm MIPS x86…. ° QEMU Tools • Qemu.exe àemulator • Qemu-img.exe àdisk image tool xx.binĎ Realview-ebĎ xx.binĎ Realview-ebĎ Qemu Ď Qemu Ď UbuntuĎ VMPlayer/Virtual X86Ď BoxĎ WindowsĎ UbuntuĎ UEE 3303 <35> YL Huang Spring ‘14 © NCTU So, after launch VMPlayerĎ ° You login to ubuntu ° Launch QEMU • qemu-system-arm • qemu-arm ° You need to specify the target to be emulated ° You also need to specify the kernel image for the targetĎ UEE 3303 <36> YL Huang Spring ‘14 © NCTU
10 Our QEMU supports..Ď codeĎ targetĎ codeĎ targetĎ syborgĎ Symbian Virtual PlatformĎ borzoiĎ PDA, PXA270Ď musicpalĎ Marvell 88w8618Ď terrierĎ PDA, PXA270Ď mainstoneĎ PXA27xĎ connexĎ Gumstix PXA255Ď N800, n810Ď Nokia N800/N810 tabletĎ verdexĎ Gumstix PXA270Ď cheetahĎ Palm TungstenĎ lm3s811evbĎ StellarisĎ sx1Ď Siemens SX1 v2Ď lm3s6965evbĎ StellarisĎ sx1-v1Ď Siemens SX1 v1Ď realview-ebĎ ARM926Ď tosaĎ PDA, PXA255Ď realview-eb-mpcore Ď ARM11Ď akitaĎ PDA, PXA270Ď realview-pb-a8Ď Cortex-A8Ď spitzĎ PDA, PXA270Ď versatilepbĎ …Ď UEE 3303 <37> YL Huang Spring ‘14 © NCTU 忚ℍġqemu ᷳ⼴Ď ° ⛐➟埴ġQEMU ⼴炻㚫↢䎦ˬ(qemu)˭ġ䘬㍸䣢ˤ⛐忁ᾳ㍸䣢ᶳ⎗ẍ廠ℍ ᶨṃ㊯ẌἮ㑵ἄġQEMUˤ ° QEMU ㊯Ẍ • help ㆾġ? [cmd]: 栗䣢婒㖶㔯⫿Ď • info: 栗䣢䲣䴙䉨ンˤἳ烉Ď • info network - 栗䣢䵚嶗ṳ朊䉨ンĎ • info block - 栗䣢⃚⬀墅伖䉨ンĎ • info registers - 栗䣢ġCPU 䘬㙓⬀☐䉨ンĎ • info history - 栗䣢㬟⎚㊯ẌĎ • What else? UEE 3303 <38> YL Huang Spring ‘14 © NCTU infoĎ ° info version -- show the version of QEMU ° info network -- show the network state ° info chardev -- show the character devices ° info block -- show the block devices ° info blockstats -- show block device statistics ° info registers -- show the cpu registers ° info cpus -- show infos for each CPU ° info history -- show the command line history ° info irq -- show the interrupts statistics (if available) ° info pic -- show i8259 (PIC) state ° info pci -- show PCI info ° info jit -- show dynamic compiler info ° info kvm -- show KVM information ° info numa -- show NUMA information ° info usb -- show guest USB devices ° info usbhost -- show host USB devices ° info profile -- show profiling information ° info capture -- show capture information ° info snapshots -- show the currently saved VM snapshots ° info status -- show the current VM status (running|paused) ° info pcmcia -- show guest PCMCIA status ° info mice -- show which guest mouse is receiving events ° info vnc -- show the vnc server status ° info name -- show the current VM name ° info uuid -- show the current VM UUID ° info usernet -- show user network stack connection states ° info migrate -- show migration status ° info balloon -- show balloon information ° info qtree -- show device tree ° info qdm -- show qdev device model list ° info roms -- show roms UEE 3303 <39> YL Huang Spring ‘14 © NCTU 忚ℍġqemu ᷳ⼴Ď ° q ㆾġquit:ġ斄攱㧉㒔☐ ° eject [-f] device烉徨↢墅伖ˤġ-f 堐䣢⻟⇞徨↢ ° change device filename:ġ㚜㎃㉥⍾⺷⨺橼炻⤪庇䡇䇯ㆾ⃱䡇䇯ˤ ° screendump filename: ㇒⍾坊ⷽ䔓朊炻⃚⬀ㆸġPPM ⼙⁷ˤġlog item1[,...]: ⮯㇨㊯⭂䘬枭䚖ᷳġLOG ⮓ℍġ/tmp/qemu.log ᷕˤ ° savevm filename: ⮯㔜ᾳ㧉㒔☐䉨ン⃚⬀军㨼㟰ᷕ ° loadvm filename: 䓙㨼㟰ᷕ庱ℍ㧉㒔☐䉨ン ° Stop:  㬊㧉㒔 ° c ㆾġcont: 两临㧉㒔 ° sendkey keys: ⁛復㝸ᾳkey䴎㧉㒔☐ˤἧ䓐ġ- Ἦ忋䳸墯⎰挝ˤ • ἳ烉``sendkey ctrl-alt-f1”ġ堐䣢⁛復ġ<Ctrl><Alt><F1> 䴎㧉㒔☐ˤ ° system_reset:ġ慵㕘┇≽䲣䴙ˤĎ UEE 3303 <40> YL Huang Spring ‘14 © NCTU
A R M 組合語言與指令集介紹 ! !!!㛔䪈ṳ䳡 BSN ㊯Ẍ普ˣUivnc ㊯Ẍ普炻ẍ⍲⎬栆㊯Ẍ⮵ㅱ䘬⭂⛨㕡⺷炻忂忶⮵ 㛔䪈䘬教嬨炻ⶴ㛃嬨侭傥䝕妋 BSN ⽖嗽䎮☐㇨㓗㎜䘬㊯Ẍ普⍲℟橼䘬ἧ䓐㕡㱽ˤ! !!!! 1 A R M 指令集的分類與格式 BSN ⽖嗽䎮☐䘬㊯Ẍ普㗗Ⱄ㕤!庱ℍ0⬀⚆!✳䘬炻ḇ⌛㊯Ẍ普傥嗽䎮㙓⬀ ☐ᷕ䘬屯㕁炻侴ᶼ嗽䎮䳸㝄悥天㓦⚆㙓⬀☐ᷕ炻侴⮵䲣䴙姀ㅞ橼䘬⬀⍾⇯暨天忂 忶⮰攨䘬!庱ℍ0⬀⚆!㊯ẌἮ⬴ㆸˤ! BSN⽖嗽䎮☐䘬㊯Ẍ普⎗ẍ↮䁢嶛廱㊯Ẍˣ屯㕁嗽䎮㊯Ẍˣ䦳⺷䉨ン㙓⬀☐ 炷QTS炸嗽䎮㊯Ẍˣ庱ℍ0⬀⚆㊯Ẍˣ庼≑忳䬿☐㊯Ẍ␴ἳ⢾䓊䓇㊯Ẍℕ⣏栆炻℟ 橼䘬㊯Ẍ⍲≇傥⤪堐3.2㇨䣢炷堐ᷕ㊯Ẍ䁢➢㛔BSN㊯Ẍ炻ᶵ⊭㊔埵䓇䘬BSN㊯Ẍ炸ˤ! BSN 䘬㊯Ẍ普⣏农ᶲ⎗ẍ↮䁢ℕ⣏栆烉! l 嶛廱㊯Ẍ)Csbodi!Jotusvdujpot*烉! 忂ⷠ㗗䓐Ἦ 䦳⺷㳩䦳㍏⇞ˤ! l 屯㕁嗽䎮㊯Ẍ)Ebub.qspdfttjoh!Jotusvdujpot*烉! ᶨ凔䘬㙓⬀☐忳䬿㊯Ẍˤ! l 庱ℍ⬀⚆㊯Ẍ)Mpbe!boe!Tupsf!Jotusvdujpot*烉! ⮵姀ㅞ橼␴㙓⬀☐ᷳ攻䘬屯㕁㏔䦣㊯Ẍˤ! l 䉨ン㙓⬀☐⬀⍾㊯Ẍ)Tubuvt!Sfhjtufs!Usbotgfs!Jotusvdujpot*烉! ⬀⍾ DQTS ␴ TQTS 㙓⬀☐䘬䚠斄㊯Ẍˤ! l 庼≑忳䬿☐)⋼⎴嗽䎮☐*㊯Ẍ)Dpqspdfttps!Jotusvdujpot*烉! ⬀⍾⋼⎴嗽䎮☐ㆾ冯⋼⎴嗽䎮☐㹅忂ᷳ㊯Ẍˤ! l ἳ⢾䓊䓇㊯Ẍ)Fydfqujpo.hfofsbujoh!Jotusvdujpot*烉! 䓊䓇庇橼ᷕ㕟␴℞Ṿἳ⢾䘬㊯Ẍˤ! ! ㊯Ẍ䫎嘇! ㊯Ẍ≇傥㍷徘! 㔠⬠忳䬿)Bsjuinfujd!jotusvdujpo* ! BED! 䲵ℍ忚ỵ㕿㧁䚠≈㊯Ẍ! BEE! ≈㱽㊯Ẍ! DNO! 㭼庫⍵嘇㊯Ẍ! DNQ! 㭼庫㊯Ẍ! TVC! 㷃㱽㊯Ẍ! TVD! 䲵ℍ忚ỵ㕿㧁䚠㷃㊯Ẍ! NMB! 43 ỵ⃫䚠Ḁ᷎䚠≈㊯Ẍ! NVM! 43 ỵ⃫Ḁ㱽㊯Ẍ! STC! ⮵婧䚠㷃㊯Ẍ! STD! 䲵ℍ忚ỵ㕿㧁⮵婧䚠㷃㊯Ẍ! 怷廗忳䬿)Mphjd!jotusvdujpo* ! BOE! BOE 忳䬿㊯Ẍ! ! 第2 頁!
CJD! ỵ⃫㶭暞)cju!dmfbs*㊯Ẍ! FPS! Fydmvtjwf!ㆾ!忳䬿㊯Ẍ! PSS! PSS 忳䬿㊯Ẍ! UFR! 䚠䫱㷔娎㊯Ẍ! UTU! ỵ⃫㷔娎㊯Ẍ! 嶛廱㊯Ẍ)Csbodi!Jotusvdujpo* ! C! 嶛廱㊯Ẍ! CM! ⷞ彼⚆䘬嶛廱㊯Ẍ! CMY! ⷞ彼⚆␴䉨ン↯㎃䘬嶛廱㊯Ẍ! CY! ⷞ䉨ン↯㎃䘬嶛廱㊯Ẍ! 庱ℍ㊯Ẍ)Mpbe!Jotusvdujpo* ! MEN! 庱ℍ⣂ᾳ㙓㊯Ẍ! MES! 姀ㅞ橼⇘㙓⬀☐䘬屯㕁⁛廠㊯Ẍ! ㏔䦣㊯Ẍ)Npwf!jotusvdujpo* ! NPW! 屯㕁⁛復)㏔䦣*㊯Ẍ! NWO! 屯㕁⍾⍵㏔䦣㊯Ẍ! NST! ⁛復 DQTS ㆾ TQTS 䘬㔠ῤ⇘ᶨ凔㙓⬀☐㊯Ẍ! NTS! ⁛復ᶨ凔㙓⬀☐⇘ DQTS ㆾ TQTS 䘬㊯Ẍ! 庼≑忳䬿☐)⋼⎴嗽䎮☐*!)Dpqspdfttps!jotusvdujpo* ! NDS! ⽆ BSN 㙓⬀☐䘬㔠ῤ⇘庼≑忳䬿☐)⋼⎴嗽䎮☐*㙓⬀☐䘬屯㕁⁛廠㊯Ẍ! NSD! ⽆庼≑忳䬿☐)⋼⎴嗽䎮☐*㙓⬀☐䘬㔠ῤ⇘ BSN 㙓⬀☐䘬屯㕁⁛廠㊯Ẍ! MED! ⽆庼≑忳䬿☐)⋼⎴嗽䎮☐*㙓⬀☐䘬㔠ῤ⇘姀ㅞ橼䘬屯㕁⁛廠㊯Ẍ! TUD! ⽆姀ㅞ橼ℏ䘬㔠ῤ⇘庼≑忳䬿☐)⋼⎴嗽䎮☐*㙓⬀☐䘬屯㕁⁛廠㊯Ẍ! DEQ! 庼≑忳䬿☐屯㕁㑵ἄ㊯Ẍ! 庇橼ᷕ㕟)Tpguxbsf!Joufssvqu!jotusvdujpo* ! TXJ! 妠䘤庇橼ᷕ㕟㊯Ẍ! TCD! ⷞῇỵ㷃㱽㊯Ẍ! ⃚⬀㊯Ẍ)Tupsx!jotusvdujpo* ! TUN! ⣂慵姀ㅞ橼⮓ℍ㊯Ẍ! TUS! 㙓⬀☐⇘姀ㅞ橼䘬屯㕁⁛廠㊯Ẍ! ℞Ṿ㊯Ẍ)Puifst*! OPQ! 䃉㊯Ẍ! TXQ! 㙓⬀☐冯姀ㅞ橼㔠ῤṌ㎃㊯Ẍ! 堐 3 . 2 !!!B S N ㊯Ẍ⍲≇傥㍷徘! ! 1.1 ARM 條件式指令 ᶨ凔 BSN ㊯Ẍ䘬℠✳㊯Ẍ䶐䡤㟤⺷⤪ᶳ㇨䣢烉! 42! 39! 38! 36! 35! 32! 31! 2:! 27! 26! 23! 22! 1! dpoe! y!y!y! pqdpef! T! So! Se! tijgufs`pqfsboe! ! ℞ᷕ烉! ! dpoe! ! ! ㊯Ẍ➟埴䘬㡅ẞ⺷䶐䡤! ! pqdpef!! ! ㊯Ẍ㑵ἄ䫎嘇! ! T! ! ! ! ㊯⭂㗗⏎⛐忳䬿➟埴㗪枮ὧ㚜㕘 DQST 䘬㕿㧁! ! 第3 頁!
! So! ! ! ! ⊭⏓䫔ᶨᾳ忳䬿⃫䘬䚖㧁㙓⬀☐䘬䶐嘇! ! Se! ! ! ! 屯㕁Ἦ㸸㙓⬀☐䘬䶐嘇! ! tijgufs`pqfsboe! 䫔Ḵᾳ屯㕁Ἦ㸸忳䬿⃫! ! BSN 䘬㊯Ẍ⊭⏓ᶨᾳ⎗怠䘬㡅ẞ䡤ˤ⎒㚱⛐ DQTS ᷕ䘬㡅ẞ䡤㕿㧁㺧嵛㊯⭂䘬 㡅ẞ㗪炻ⷞ㡅ẞ䡤䘬㊯Ẍㇵ⎗ẍ➟埴ˤḇ⎗ẍ㟡㒂ᶨ㡅㊯Ẍ姕伖䘬㕿㧁炻㚱㡅ẞ ⛘➟埴⎎ᶨ㡅㊯Ẍˤ㭷ᶨ㡅 BSN ㊯Ẍ⊭⏓ 5 ỵ⃫䘬㡅ẞ䡤炻ỵ㕤㊯Ẍ䘬㚨檀 5 ỵ⃫42;39^ˤ㭷䧖㡅ẞ䡤⎗䓐ℑᾳ⫿⃫堐䣢炻忁ℑᾳ⫿⃫⎗ẍ㶣≈⛐㊯䫎嘇䘬 ⼴朊␴㊯Ẍ⎴㗪ἧ䓐ˤἳ⤪炻嶛廱㊯Ẍ C ⎗ẍ≈ᶲ⯦䡤 FR 嬲䁢 CFR 堐䣢Ⱦ䚠䫱 ⇯嶛廱ȿ炻⌛䔞 DQTS ᷕ䘬 [ 㕿㧁䁢 2 㗪䘤䓇嶛廱ˤ㡅ẞ䶐䡤㚱⤪ᶳ⸦䧖烉! ! 䶐䡤 4 2 ; 3 9 ^ ! 㡅ẞ㍷ 徘! 䉨ン㕿㧁! 忳䬿⏓佑! ㊯Ẍ䭬ἳ! 1111! FR! [!>!2! 䚠䫱! CFR! 1112! OF! [!>!1! ᶵ䫱ῤ! COF! 1121! DT0IT! D!>2! ⣏㕤䫱㕤! CDT! 1122! DD0MP! D!>!1! ⮷㕤! CDD! 1211! NJ! O!>2! 屈ῤ! CNJ! 1212! QM! O!>1! 㬋㔠ㆾ暞! CQM! 1221! WT! W!>!2! 㹊ỵ! CWT! 1222! WD! W!>!1! 䃉㹊↢! CWD! 2111! IJ! D!>!2!boe![!>!1! ⣏㕤! CIJ! 2112! MT! D!>!1!ps![!w! ⮷㕤䫱㕤! CMT! 2121! HF! O!>W!! ⣏㕤䫱㕤! CHF! 2122! MU! O!ɽ!W!! ⮷㕤! CMU! 2211! HU! [!>!1!boe!O!>!W! ⣏㕤! CHU! 2212! MF! [!>!2炻ps!O!ɽ!W! ⮷㕤ㆾ䫱㕤! CMF! 2221! BM! Boz! 枸姕ῤ! CBM! !!!!!!!!!!!!!!!!!!!!!!!!!!!!堐 3 . 3 !㡅ẞ⺷⭂佑ˣ䶐䡤冯嶛廱㊯Ẍ䭬ἳ! ! BSN ㊯Ẍ⎗㟡㒂➟埴䳸㝄Ἦ怠㑯㗗⏎㚜㕘㡅ẞ㕿㧁ỵ⃫ˤ劍天㚜㕘㡅ẞ㕿㧁ỵ ⃫炻枰⛐㊯Ẍᷕ⊭⏓⯦䡤ȾTȿˤ! ᶨṃ㊯Ẍᶵ暨天⯦䡤ȾTȿ炻⤪ DNQˣDNOˣUTU ␴ UFRˤ⬫Ᾱ䘬≇傥㛔Ἦ⯙㗗 㚜㕘㡅ẞ㕿㧁ỵ⃫䘬ˤ! 2 A R M 指令的定址方式 ⭂⛨㕡⺷⯙㗗嗽䎮☐㟡㒂㊯Ẍᷕ䴎↢䘬ỵ⛨屯妲Ἦ⮳㈦⮎晃ỵ⛨䘬㕡⺷ˤ䚖 ⇵ BSN ㊯Ẍ䘬⭂⛨㕡⺷)⭂⛨㱽*➢㛔ᶲ⎗ẍ↮䁢ẍᶳ⸦䧖烉! ! 2/!䩳⌛⭂⛨! ㊯Ẍᷕ⶚⊭⏓Ḯ忳䬿⃫炻⌛䩳⌛㔠ˤἳ⤪烉! BEE!S1炻S1炻炲2! ! ! 烊S1ɤS1為2! ! 第4 頁!
BEE!S1炻S1炻炲1y4g! ! 烊S1ɤS1為1y4g! ! ⛐ẍᶲℑ㡅㊯Ẍᷕ炻䫔Ḵᾳ屯㕁Ἦ㸸忳䬿⃫)㔠ῤ*⌛䁢䩳⌛㔠炻᷎天㯪ẍ Ⱦ炲ȿ䁢⋨↮炻⮵㕤ẍ⋩ℕ忚ỵ堐䣢䘬䩳⌛㔠炻怬天㯪⛐Ⱦ炲ȿ⼴≈ᶲȾ1yȿㆾ Ⱦ'ȿˤ! ! ! 3/!㙓⬀☐䚜㍍⭂⛨! ㊯Ẍᷕ䘬ỵ⛨䶐䡤悐↮䴎↢㝸ᶨ㙓⬀☐䶐嘇炻忳䬿⃫)㔠ῤ*⛐㙓⬀☐ᷕˤἳ ⤪烉! BEE!S1-S2-S3! <S2,S3àS1! 娚㊯Ẍ䘬➟埴枮⸷䁢⮯㙓⬀☐S2␴S3䘬㔠ῤ䚠≈炻⮯℞䳸㝄⬀㓦⛐㙓⬀☐S1 ᷕˤ! ! 4/ 㙓⬀☐攻㍍⭂⛨! 㙓⬀☐攻㍍⭂⛨⯙㗗ẍ㙓⬀☐ᷕ䘬ῤἄ䁢忳䬿⃫䘬ỵ⛨炻侴忳䬿⃫㛔幓⬀㓦 ⛐姀ㅞ橼ᷕˤἳ⤪烉! MES!!S1-!S2^! <S2^àS1!!00⮯ S2 ㊯⎹䘬姀ㅞ橼ᷕ䘬ℏ⭡庱ℍ⇘ S1 ᷕˤ! TUS!!S1炻S2^! 烊S2^ɤS1!00⮯ S1 䘬ῤ⁛復⇘ẍ S2 䘬ῤ䁢ỵ⛨䘬姀ㅞ橼 ᷕˤ! ! 5/ 㙓⬀☐䦣ỵ⭂⛨! 䫔Ḵᾳ㙓⬀☐ᷕ⬀㓦䘬忳䬿⃫⃰忚埴䦣ỵ㑵ἄ炻䃞⼴冯䫔ᶨᾳ忳䬿⃫䳸⎰ˤ ἳ⤪烉! BEE!S1-!S2-!S3!MTM!$4!! <S2,S3+9àS1!!00S3 ᷕ䘬忳䬿⃫ⶎ䦣 4 ỵ⃫! ! ⎗ẍ㍉䓐䘬䦣ỵ㊯Ẍ㚱ẍᶳ⸦䧖烉! MTM)Mphjdbm!Tijgu!Mfgu*烉怷廗ⶎ䦣ˤ㙓⬀☐ᷕ䘬忳䬿⃫ⶎ䦣ᶨỵ炻MTM ⽆! cju!1 Ỷỵ墄 1 忚Ἦˤ! MTS)Mphjdbm! Tijgu! Sjhiu*烉怷廗⎛䦣ˤ㙓⬀☐ᷕ䘬忳䬿⃫⎛䦣ᶨỵ炻 MTS! ⽆ cju!42 檀ỵ墄 1!忚Ἦˤ! BTS)Bsjuinfujd!Tijgu!Sjhiu*烉䬿埻⎛䦣ˤBsjuinfujd!Tijgu ẋ堐ᾅ 䔁㬋! 屈嘇㪬ỵ℞Ṿ ỵ䦣≽ἄˤ⚈㬌䦣ỵ⃫䘬忶䦳ᷕㅱᾅ㊩忳䬿⃫䘬䫎嘇ᶵ嬲ˤ! 㙓⬀☐ᷕ䘬忳䬿⃫⎛䦣ᶨỵˤ劍忳䬿⃫䁢㬋㔠炻⇯ cju!42 墄 1ˤ劍忳䬿⃫䁢! 屈㔠炻⇯ cju!42!墄忚 2ˤ! SPS)Spubuf!Sjhiu*烉徜⚰⎛䦣ˤ㙓⬀☐ᷕ䘬忳䬿⃫⎛䦣ᶨỵ炻㚨檀ỵ⃫ 䨢! ↢ỵ⃫᷎䦣ℍ㚨Ỷỵ䦣↢䘬ỵ⃫ˤ! SSY)Spubuf!Sjhiu!fYufoefe*烉⺞Ỡ SPS 䘬徜⚰⎛䦣ˤ㙓⬀☐ᷕ䘬忳䬿 ⃫⎛! 䦣ᶨỵ炻㚨檀ỵ⃫䨢↢ỵ⃫⼴䓐⍇Ἦ DQTS 䘬㕿㧁ỵ⃫ᷕ䘬ῤ⠓ℍˤ! ! ! 第5 頁!
6/ ⣂㙓⬀☐⭂⛨! 䓐㬌㕡⺷⎗ᶨ㫉⁛怆⸦ᾳ㙓⬀☐ᷕ䘬ῤˤ⃩姙⛐ᶨ㡅㊯Ẍᷕ㚨⣂⁛復 27 ᾳ ᶨ凔㙓⬀☐䘬ảỽ⫸普ˤἳ⤪烉! MENJB!!S1-!|S2-!S3-!S4~! <!S1^àS2! !! ! ! ! ! ! !!!!<!S1,5^àS3! !! ! ! ! ! ! !!!<!S1,9^àS4! 娚㊯Ẍ䘬⯦⶜䘬 JB 堐䣢㭷㫉➟埴⬴ᶳ庱0⬀⚆㑵ἄ⼴炻S1 ㊱ Xpse 攟⹎⡆≈炻! ⚈㬌㊯Ẍ⎗⮯忋临姀ㅞ橼䘬ῤ⁛復⇘ S2S4ˤ! ! 7/ ➢⛨⭂⛨! 㬌㕡⺷㗗⮯➢⛨㙓⬀☐ᷕ䘬ℏ⭡冯㊯Ẍᷕ䘬ῷ䦣慷䚠≈炻⼿⇘忳䬿⃫䘬⬀㓦 ỵ⛨ˤ➢⛨⭂⛨䓐㕤⬀⍾➢⸽ỵ⛨旬役䘬姀ㅞ橼ˤἳ⤪烉! MES!S1-!S2-!$9^! ! ! <S2,9^àS1! MES!S1-!S2,S3^! ! ! <S2,S3^àS1! ! ➢⛨⭂⛨⊭㊔⇵䳊⺽␴⼴䳊⺽⭂⛨ˤ! ⇵䳊⺽⭂⛨㊯⮯➢⸽ỵ⛨≈ᶲῷ䦣慷ᷳ⼴䓊䓇䘬ỵ⛨ἄ䁢㚱㓰ỵ⛨ˤἳ⤪烉! MES!S1-!S2-!$9^! ! ! <S2,9^àS1! ! ⼴䳊⺽⭂⛨㊯⮯ᶵⷞ㚱ῷ䦣慷䘬➢⸽ỵ⛨ἄ䁢㚱㓰ỵ⛨ˤ! MES!S1-!S2^-!$9! ! ! <S2^àS1! !! ! ! ! ! ! !!!<S2,9àS2! ! ⎎⢾炻䫎嘇Ⱦ炰ȿ⎗ẍ䓐Ἦἧ㊯Ẍ➟埴⬴⼴㚜㕘➢⸽ỵ⛨ˤἳ⤪烉! MES!S1-!S2-!$9^"!! ! <S2,9^àS1! !! ! ! ! ! ! !!!!<S2,9àS2! ! 8/ ➮䔲⭂⛨! ➮䔲⭂⛨⌛⇑䓐➮䔲㊯㧁炻㊱䈡⭂枮⸷⬀⍾姀ㅞ橼╖⃫炻ἧ䓐 qvti ㊯Ẍ⎹➮! 䔲⮓屯㕁ˤἧ䓐 qpq ㊯Ẍ⽆➮䔲ᷕ嬨㔠㒂ˤ! ➮䔲⎗↮䁢ℑ䧖烉! 怆⡆➮䔲)btdfoejoh!tubdl*炻⌛➮䔲⎹檀ỵ⛨㕡⎹Ỡ⯽烊! 怆㷃➮䔲)eftdfoejoh!tubdl*炻⌛➮䔲⎹Ỷỵ⛨㕡⎹Ỡ⯽烊! ➮䔲㊯㧁㊯⎹㚨⼴⡻ℍ➮䔲䘬㚱㓰屯㕁炻䧙䁢㺧➮䔲)gvmm!tubdl*ˤ➮䔲㊯!!!!! 㧁㊯⎹ᶳᶨᾳ㚱㓰屯㕁⮯天⬀㓦䘬ỵ伖炻䧙䁢䨢➮䔲)fnquz!tubdl*ˤ! ㊱㬌䳬⎰炻⎗䓊䓇 5 䧖栆✳䘬➮䔲烉! 㺧怆⡆烉!!㺧➮䔲炻怆⡆➮䔲! 䨢怆⡆烉!!䨢➮䔲炻怆⡆➮䔲! 㺧怆㷃烉!!㺧➮䔲炻怆㷃➮䔲! 䨢怆㷃烉!!䨢➮䔲炻怆㷃➮䔲! ! 9/ 䚠⮵⭂⛨! !!!㈲ QD ㊯㧁ἄ䁢➢⸽ỵ⛨ˤ妰䬿↢䚖䘬⛘⛨␴䎦埴㊯Ẍỵ⛨ᷳ攻䘬ῷ䦣慷ˤ!!!!! !!!➢⸽ỵ⛨≈ῷ䦣慷⌛⼿⇘㚨䳪䘬㚱㓰ỵ⛨ˤἳ⤪烉! ! 第6 頁!
CM!TVCS! ! <嶛廱⇘ TVCS! Ƀ! ! !!!TVCS! Ƀ! ! ! ! <∗䦳⺷ℍ⎋! NPW!QD-!S25! ! <彼⚆! 3 A R M 指令分類介紹 ⇵朊⶚䞍 BSN ㊯Ẍ⎗↮䁢ℕ⣏栆烉㍍ᶳἮ䁢忁ℕ⣏栆㊯Ẍ忚埴娛䳘䘬妋婒ˤ!! 3.1 記憶體存取指令 2/!MES ␴ TUS烉䓐㕤╖ᶨ xpse ␴䃉䫎嘇ỵ⃫䳬)Votjhofe!Czuf*㗪ˤ! 庱ℍ㙓⬀☐㊯Ẍ)MES*⮯屯㕁⽆姀ㅞ橼庱ℍ⇘㙓⬀☐ᷕˤ⃚⬀㙓⬀☐㊯Ẍ)TUS* ⮯屯㕁⽆㙓⬀☐⬀㓦⇘姀ㅞ橼ᷕˤ⎗䓐㕤 43 ỵ⃫ xpse ㆾ 9 ỵ⃫䃉䫎嘇ỵ⃫䳬ˤ ỵ⃫䳬庱ℍ㚫䓐Ⱦ1ȿ⺞Ỡ军 43 ỵ⃫ˤ! MES ␴ TUS 悥㚱⤪ᶳ 5 䧖⼊⺷烉! l 暞ῷ䦣慷){fsp!pggtfu*! pq|dpoe~|C~|U~!Se炻So^! So 䘬ῤἄ䁢⁛復屯㕁䘬ỵ⛨ˤ! ! l ⇵䳊⺽ῷ䦣)qsf.joefyfe!pggtfu*! pq|dpoe~|C~!Se炻So炻Gmfypggtfu^|"~! ⛐屯㕁⁛復ᷳ⇵炻⮯ῷ䦣慷≈⇘ So ᷕˤ℞䳸㝄ἄ䁢⁛復屯㕁䘬姀ㅞ橼 ỵ⛨ˤ劍ἧ䓐⯦䡤Ⱦ"ȿ炻⇯䳸㝄⮓⚆⇘ So ᷕ炻ᶼ So ᶵ⃩姙㗗 S26ˤ! ! l 䦳⺷䚠⮵ῷ䦣)qsphsbn!sfmbujwf*! pq|dpoe~|C~!Se炻mbcfm! 䦳⺷䚠⮵ῷ䦣㗗⇵䳊⺽⼊⺷䘬⎎ᶨ䧖䇰㛔ˤ⽆ QD 妰䬿ῷ䦣慷炻᷎⮯ QD ἄ䁢 So 䓊䓇⇵䳊⺽㊯Ẍˤᶵ傥ἧ䓐⯦䡤Ⱦ"ȿˤ! ! l ⼴䳊⺽ῷ䦣)qptu.joefyfe!pggtfu*! pq|dpoe~|C~|U~!Se炻So^炻Gmfypggtfu! So 䘬ῤ䓐 ⁛復屯㕁䘬姀ㅞ橼ỵ⛨ˤ⛐屯㕁⁛復⼴炻⮯ῷ䦣慷≈⇘ So! ᷕˤ䳸㝄⮓⚆⇘ SoˤSo ᶵ⃩姙㗗 S26ˤ! ! ℞ᷕ烉! pq! 㑵ἄ䡤炻㊯Ẍ MES ㆾ TUSˤ! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! C! ⎗怠㑯⯦䡤ˤ劍㚱 C炻⇯⁛復 Se 䘬㚨Ỷ㚱㓰ỵ⃫䳬ˤ劍 pq 㗗 MES炻⇯⮯ Se 䘬℞Ṿỵ⃫䳬㶭昌䁢暞ˤ! U! ⎗怠㑯⯦䡤ˤ劍㚱 U炻恋湤⌛ἧ嗽䎮☐㗗⛐䈡㬲㧉⺷ᶳ炻⃚⬀ 䲣䴙ḇ⮯⬀⍾䚳ㆸ嗽䎮☐㗗⛐ἧ䓐侭㧉⺷ᶳˤU ⛐ἧ䓐侭㧉⺷ ᶳ䃉㓰炻ᶵ傥冯⇵䳊⺽ῷ䦣ᶨ崟ἧ䓐 Uˤ! Se! 䓐㕤庱ℍㆾ⃚⬀䘬 BSN 㙓⬀☐ˤ! So! 姀ㅞ橼䘬➢⸽㙓⬀☐ˤ劍㊯Ẍ㗗℟㚱⮓⚆)xsjufcbdl*䘬⇵䳊 ! 第7 頁!
⺽ㆾ⼴䳊⺽)⯦䡤䁢Ⱦ"ȿ*炻ㆾἧ䓐⯦䡤 U炻⇯ᶵ⃩姙 So 冯 Se 䚠⎴ˤ! Gmfypggtfu! ≈⇘ So ᶲ䘬曰㳣䘬ῷ䦣慷ˤ! Mbcfm! 䦳⺷䚠⮵ῷ䦣忳䬿⺷ˤmbcfm ⽭枰㗗⛐䚖⇵㊯Ẍ䘬㬋屈 5LC 䭬 ⚵ℏˤ! "! ⎗怠⯦䡤ˤ劍㚱Ⱦ"ȿ炻⇯⮯⊭⏓ῷ䦣慷䘬ỵ⛨⮓⚆⇘ Soˤ劍 So 㗗 S26炻⇯ᶵ傥ἧ䓐⯦䡤Ⱦ"ȿˤ! ! Gmfypggtfu 䓐㱽烉! !!!!⇵䳊⺽␴⼴䳊⺽⎗ẍ㗗ẍᶳℑ䧖⼊⺷ᷳᶨ烉! !!!!$fyqs! !!!!|ᶨ~Sn|炻tijgu~! !!!!℞ᷕ烉! ᶨ! ⎗怠屈嘇ˤ劍ⷞ䫎嘇Ⱦᶨȿ炻⇯⽆ So ᷕ㷃⍣ῷ䦣慷ˤ⏎⇯炻 ⮯ῷ䦣慷≈⇘ So ᷕˤ! fyqs! 忳䬿⺷炻⍾ῤ䭬⚵㗗.51:6 ⇘,51:6 䘬㔜㔠ˤ! Sn! ℏ⏓ῷ䦣慷䘬㙓⬀☐ˤSn ᶵ⃩姙㗗 S26ˤ! tijgu! Sn 䘬⎗怠䦣ỵ㕡㱽ˤ⎗ẍ㗗ᶳ↿⼊⺷䘬ảỽᶨ䧖烉! BTS!o!!䬿埻⎛䦣 o ỵ)2=>o=>43*! MTM!o!!怷廗ⶎ䦣 o ỵ⃫)2=>o=>42*! MTS!o!!怷廗⎛䦣 o ỵ⃫)2=>o=>43*! SPS!o!!徜⚰⎛䦣 o ỵ)2=>o=>42*! SSY!!!徜⚰⎛䦣 2 ỵ炻ⷞ㚱⺞Ỡ! ! ἳ⫸烉! MES!!S9炻S1^! ! ! ! 烊S1^à!S9! MESOF!!S3炻S6炻$:71^"!! 烊 ) 㚱 㡅 ẞ ⛘ *! S6,:71^à! S3 烊 S6,:71àS6! TUS!!S6炻$S8^炻$..9! ! 烊S6àS8^炻S8.9àS8! ! 3/ MES ␴ TUS烉䓐㕤╖ᶨ ibmuxpse ␴ⷞ䫎嘇ỵ⃫䳬)Tjhofe!Czuf*㗪ˤ! 庱ℍ㙓⬀☐炻䓐㕤ⷞ䫎嘇䘬 9 ỵ⃫ỵ⃫䳬ˣⷞ䫎嘇␴䃉䫎嘇䘬 27 ỵ⃫ ibmuxpseˤ! ⃚⬀㙓⬀☐炻䓐㕤 27 ỵ⃫ ibmuxpseˤ! ⷞ䫎嘇庱ℍ㗗㊯ⷞ䫎嘇⺞Ỡ军 43 ỵ⃫ˤ䃉䫎嘇 ibmuxpse 庱ℍ㗗㊯䓙暞⺞Ỡ ⇘ 43 ỵ⃫ˤ! 忁ṃ㊯Ẍ㚱 5 䧖⎗傥䘬⼊⺷烉暞ῷ䦣ˣ⇵䳊⺽ῷ䦣ˣ䦳⺷䚠⮵ῷ䦣␴⼴䳊⺽ ῷ䦣ˤẍ⎴㧋䘬枮⸷炻5 䧖⼊⺷䘬⎍㱽䁢烉! pq|dpoe~uzqf!!Se炻So^! pq|dpoe~uzqf!!Se炻So炻pggtfu^|"~! pq|dpoe~uzqf!!Se炻mbcfm! pq|dpoe~uzqf!!Se炻So^炻pggtfu! ! ℞ᷕ烉! ! 第8 頁!
pq! 㑵ἄ䡤炻㊯Ẍ MES ㆾ TUSˤ! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! uzqf! ! ⽭枰㗗ẍᶳ㇨↿䘬℞ᷕᷳᶨ烉! TI! ! ⮵ⷞ䫎嘇 ibmuxpse)⮵ MES*! I!! ⮵䃉䫎嘇 ibmuxpse! TC! ! ⮵ⷞ䫎嘇ỵ⃫䳬)⮵ MES*! 2bcfm! 䦳⺷䚠⮵ῷ䦣忳䬿⺷ˤmbcfm ⽭枰㗗⛐䚖⇵㊯Ẍ䘬.366 军,366 ỵ⃫ 䳬䭬⚵ℏˤ! pggtfu!≈⛐ So ᶲ䘬ῷ䦣慷ˤ! Se! ! 䓐㕤庱ℍㆾ⃚⬀䘬 BSN 㙓⬀☐ˤ! So! 姀ㅞ橼䘬➢⛨㙓⬀☐ˤ劍㊯Ẍ㗗ⷞ㚱⮓⚆)xsjufcbdl*䘬⇵䳊⺽ㆾ ⼴䳊⺽)⯦䡤䁢Ⱦ"ȿ*炻⇯ᶵ⃩姙 So 冯 Se 䚠⎴ˤ! ἳ⫸烉! MESI!!S2炻S1炻$31^! 烊S1,31^àS2炻庱ℍ 27 ỵ ibmuxpse炻䓙暞 ⺞Ỡ⇘ 43 ỵ⃫ˤ! TUSI!!S3炻S1炻S2^"! 烊S1,S2^àS3炻⃚⬀㚨Ỷ䘬㚱㓰 ibmuxpse ⇘ S1,Sm ỵ⛨攳⥳䘬ℑᾳỵ⃫䳬炻ỵ⛨⮓⚆ ⇘ S1ˤ! ! 4/ MES ␴ TUSȹ䓐㕤暁 xpse 㗪ˤ! 庱ℍℑᾳ䚠惘䘬㙓⬀☐炻75 ỵ⃫暁 xpseˤ! ⃚⬀ℑᾳ䚠惘䘬㙓⬀☐炻75 ỵ暁⃫ xpseˤ! 忁ṃ㊯Ẍ㚱 5 䧖⎗傥䘬⼊⺷烉暞ῷ䦣ˣ⇵䳊⺽ῷ䦣ˣ䦳⺷䚠⮵ῷ䦣␴⼴䳊⺽ ῷ䦣ˤẍ⎴㧋䘬枮⸷炻5 䧖⼊⺷䘬⎍㱽䁢烉! pq|dpoe~E!!Se炻So^! pq|dpoe~E!!Se炻So炻pggtfu^|"~! pq|dpoe~E!!Se炻mbcfm! pq|dpoe~E!!Se炻So^炻pggtfu! ! ℞ᷕ烉! pq! 㑵ἄ䡤炻㊯Ẍ MES ㆾ TUSˤ! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! Se! 庱ℍㆾ⃚⬀䘬㙓⬀☐ᷕ䘬ᶨᾳ炻⎎ᶨᾳ㗗 S)e,2*ˤSe ⽭枰㗗„㔠 㙓⬀☐炻ᶼᶵ㗗 S25ˤ! So! 昌朆㊯Ẍ䁢暞ῷ䦣炻ㆾᶵⷞ㚱⮓⚆䘬⇵䳊⺽炻⏎⇯ So ᶵ⃩姙冯 Se ␴ S)e,2*䚠⎴ˤ! Pggtfu! ≈⛐ So ᶲ䘬ῷ䦣慷ˤ! Mbcfm! 䦳⺷䚠⮵ῷ䦣忳䬿⺷ˤmbcfm ⽭枰㗗⛐䚖⇵㊯Ẍ䘬²363 ỵ⃫䳬䭬⚵ ℏˤ! "! ⎗怠⯦䡤ˤ劍㚱Ⱦ"ȿ炻⇯⮯⊭⏓ῷ䦣慷䘬㚨⼴䘬ỵ⛨⮓⚆⇘ Soˤ! ! ἳ⫸烉! MESE!!S7炻S22^! TUSE!!S1炻S:炻.S3^"! ! 第9 頁!
! 5/ MEN ␴ TUN! 庱ℍ⣂ᾳ㙓⬀☐)MpbE! Nvmujqmf! sfhjtufst*␴⃚⬀⣂ᾳ㙓⬀☐)TUpsf! Nvmujqmf!sfhjtufst*ˤ⎗ẍ⁛復 S1S26 䘬ảỽ䳬⎰ˤ! ! ⎍㱽烉! pq|dpoe~npef!!So|"~炻sfhmjtu|_~! ! ℞ᷕ烉! pq! 㑵ἄ䡤炻㊯Ẍ MEN ㆾ TUNˤ! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! npef! 㗗ᶳ↿ね㱩ᷳᶨ烉! JB! 㭷㫉⁛復⼴ỵ⛨≈ 2! JC! 㭷㫉⁛復⇵ỵ⛨≈ 2! EB! 㭷㫉⁛復⼴ỵ⛨㷃 2! EC! 㭷㫉⁛復⇵ỵ⛨㷃 2! GE! 㺧怆㷃➮䔲! FE! 䨢怆㷃➮䔲! GB! 㺧怆⡆➮䔲! FB! 䨢怆⡆➮䔲! So! ➢⸽㙓⬀☐炻墅㚱⁛復屯㕁䘬⇅⥳ỵ⛨ˤSo ᶵ⃩姙㗗 S26ˤ! "! ⎗怠⯦䡤ˤ劍㚱Ⱦ"ȿ炻⇯㚨⼴䘬ỵ⛨⮓⚆⇘ Soˤ! Sfhmjtu! 庱ℍㆾ⃚⬀䘬㙓⬀☐↿堐炻⊭⏓⛐㊔⻏ᷕˤ⬫ḇ⎗ẍ⊭⏓㙓⬀☐䘬 䭬⚵ˤ劍⊭⏓⣂㕤 2 ᾳ㙓⬀☐ㆾ⊭⏓㙓⬀☐䭬⚵炻⇯⽭枰䓐徿嘇↮ 攳ˤ! _! ⎗怠⯦䡤炻ᶵ⃩姙⛐ἧ䓐侭㧉⺷ㆾ䲣䴙㧉⺷ᶳἧ䓐ˤ⬫㚱ℑᾳ䚖䘬烉! 2/!劍 pq 㗗 MEN ᶼ sfhmjtu ᷕ⊭⏓ QD)S26*炻恋湤昌Ḯ㬋ⷠ䘬⣂㙓 ⬀☐⁛復⢾炻⮯ TQTS ḇ㊟居⇘ DQTS ᷕˤ忁䓐㕤⽆ἳ⢾嗽䎮彼⚆炻 ⛐ἳ⢾㧉⺷ᶳἧ䓐ˤ! 3/!屯㕁⁛ℍㆾ⁛↢䘬㗗ἧ䓐侭㧉⺷䘬㙓⬀☐炻侴ᶵ㗗䚖⇵㧉⺷䘬 㙓⬀☐ˤ! ! ⷞ㚱⮓⚆䘬庱ℍㆾ⃚⬀➢⸽㙓⬀☐烉! ⤪㝄 So ⊭⏓⛐㙓⬀☐↿堐ᷕ炻ᶼ䓐⯦䡤Ⱦ炰ȿ㊯㖶天⮓⚆)xsjufcbdl*炻恋 湤烉! ..!劍 pq 㗗 TUN炻ᶼ So 㗗㙓⬀☐↿堐ᷕ㔠⫿㚨⮷䘬㙓⬀☐炻⇯⮯ So 䘬⇅ ῤᾅ⬀ˤ! ..!So 䘬庱ℍ␴⃚⬀ῤ⇯ᶵ⎗枸㷔ˤ! ! ἳ⫸烉! MENJB!!S9炻|S1炻S3炻S8~! TUNEC!!S2"炻|S4 ᶨ S7炻S22炻S23~! ! 6/ TXQ! ! 第: 頁!
⛐㙓⬀☐␴姀ㅞ橼ᷳ攻忚埴屯㕁Ṍ㎃ˤ! ⎗ἧ䓐 TXQ)TXbQ*Ἦ⮎䎦ᾉ嘇慷)tfnbqipsf*ˤ! ⎍㱽烉! TXQ|dpoe~|C~!!Se炻Sn炻So^! !!!℞ᷕ烉! dpoe!⎗怠㑯䘬㡅ẞ䡤ˤ! C! ⎗怠㑯⯦䡤ˤ劍㚱 C炻⇯Ṍ㎃ỵ⃫䳬ˤ⏎⇯Ṍ㎃ 43 ỵ xpseˤ! Se! 屯㕁⽆姀ㅞ橼庱ℍ⇘ Seˤ! Sn!!Sn 䘬ℏ⭡⃚⬀⇘姀ㅞ橼ˤSn ⎗ẍ冯 Se 䚠⎴ˤ⛐忁䧖ね㱩ᶳ炻㙓⬀☐䘬 ℏ⭡冯姀ㅞ橼䘬ℏ⭡忚埴Ṍ㎃ˤ! So!!!So 䘬ℏ⭡㊯⭂天忚埴屯㕁Ṍ㎃䘬姀ㅞ橼䘬ỵ⛨ˤSo ⽭枰冯 Se ␴ Sn ᶵ ⎴ˤ! ! 2.3.2 資料處理指令 2/ 曰㳣䘬䫔Ḵ忳䬿⃫! ⣏⣂㔠 BSN 忂䓐屯㕁嗽䎮㊯Ẍ㚱ᶨᾳ曰㳣䘬䫔Ḵ忳䬿⃫ˤ⛐㭷ȹᾳ㊯Ẍ䘬⎍ 㱽㍷徘ᷕẍȾPqfsboe3ȿ堐䣢ˤ! Pqfsboe3 㚱⤪ᶳℑ䧖⎗傥䘬⼊⺷烉! $jnnfe`9s! Sn!|炻tijgu~! ! ℞ᷕ烉! jnnfe`9s! 䩳⌛ῤ䁢㔠⫿ⷠ㔠䘬忳䬿⺷ˤ! ⎰㱽ⷠ㔠烉! 1yGGˣ1y215ˣ1yGG1ˣ1yGG111ˣ1yGG111111ˣ1yG111111Gˤ! 朆㱽ⷠ㔠烉! 1y212 ˣ 1y213 ˣ 1yGGm ˣ 1yGG15 ˣ 1YGG114 ˣ 1yGGGGGGGG ˣ 1yG111112Gˤ! Sn! ⃚⬀䫔Ḵ忳䬿⃫屯㕁䘬 BSN 㙓⬀☐ˤ! Tijgu! Sn 䘬⎗怠㑯䦣ỵ㕡㱽ˤ⎗ẍ㗗ẍᶳ㕡㱽䘬ảỽᶨ䧖烉! BTS!o! 䬿埻⎛䦣 o ỵ)2=>o=>43*! MTM!o! 怷廗ⶎ䦣 o ỵ⃫)2=>o=>42*! MTS!o! 怷廗⎛䦣 o ỵ⃫)2=>o=>43*! SPS!o! 徜⚰⎛䦣 o ỵ)2=>o=>42*! SSY! ⷞ㚱⺞Ỡ䘬徜⚰⎛䦣 2 ỵ! uzqf!St! ℞ᷕ烉! uzqd! BTSˣMTMˣMTS ␴ SPS ᷕ䘬ᶨ䧖ˤ! St! ㍸ὃ䦣ỵ慷䘬 BSN 㙓⬀☐炻ἧ䓐㚨Ỷ㚱㓰 ỵ⃫䳬ˤ! ! ⛐㊯Ẍᷕ䦣ỵ⃫㑵ἄ䘬䳸㝄䓐  pqfsboe3炻Ữ Sn 㛔幓ᶵ嬲ˤ! ! 3/ BEEˣTVCˣSTCˣBEDˣTCD ␴ STD! ≈ˣ㷃ˣ⍵㷃炻≈ᶲ!ⷞㆾᶵⷞ忚ỵˤ! ! 第21 頁!
⎍㱽烉! pq!|dpoe~|T~!!Se炻So炻Pqfsboe3! ℞ᷕ烉! pq! 㑵ἄ䡤ˤBEEˣTVCˣSTCˣBEDˣTCD ␴ STD ℞ᷕȹᾳˤ! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! T! ⎗怠㑯䘬⯦䡤ˤ劍㊯⭂ T炻⇯㟡㒂㑵ἄ䳸㝄㚜㕘㡅ẞ䡤㧁娴)Oˣ[ˣ D ␴ W*ˤ! Se! BSN 䳸㝄㙓⬀☐ˤ! So! ᾅ⬀䫔ᶨ忳䬿⃫䘬 BSN 㙓⬀☐ˤ! Pqfsboe3! 䫔Ḵ忳䬿⃫ˤ! ! 䓐㱽烉! 炽BEE)BEE*㊯Ẍ䓐㕤⮯ So ␴ Pqfsboe3 䘬ῤ䚠≈ˤ! 炽TVC)TVCusbdu*㊯Ẍ䓐㕤⽆ So 䘬ῤᷕ㷃⍣ Pqfsboe3 䘬ῤˤ! 炽STC)Sfwfstf!TvCusbdu*㊯Ẍ䓐㕤⽆ Pqfsboe3 䘬ῤᷕ㷃⍣ So 䘬ῤˤ䓙㕤 Pqfsboe3 䘬⎗怠䭬⚵⮔炻㇨ẍ忁㡅㊯Ẍ⼰㚱䓐ˤ! 炽BED)BEe!xjui!Dbssz*㊯Ẍ⮯ So ␴ Pqfsboe3 ᷕ䘬ῤ䚠≈炻᷎ⷞ㚱忚ỵ⃫ 㧁娴ˤ! 炽TCD)TvCusbdu!xjui!Dbssz*㊯Ẍ⽆ So 䘬ῤᷕ㷃⍣ Pqfsboe3 䘬ῤˤ劍忚ỵ ⃫㧁娴㗗㶭昌䁢暞-⇯䳸㝄㷃 mˤ! 炽STD)Sfwfstf!Tvcusbdu!xjui!Dbssz*㊯Ẍ⽆ Pqfsboe3 䘬ῤᷕ㷃⍣ So 䘬ῤˤ 劍忚ỵ⃫㧁娴㗗㶭昌䁢暞炻⇯䳸㝄㷃 2ˤ! 炽BEDˣTCD ␴ STD 䓐㕤⣂ᾳ⫿䘬䬿埻忳䬿ˤ! 炽劍㊯⭂ T炻恋湤忁ṃ㊯Ẍ㟡㒂䳸㝄㚜㕘㧁娴 Oˣ[ˣD ␴ Wˤ! ! ἳ⫸烉! BEE!!S3炻S2炻S4! TVCT!!S9炻S7炻$351! 烊㟡㒂䳸㝄姕伖㧁娴! STC!!S5炻S5炻$2391! 烊2391.S5! BEDIJ!!S22炻S1炻S4! 烊⎒㚱㧁娴 D 伖ỵ⃫ᶼ㧁娴 [ 㶭昌䁢暞 㗪ㇵ➟埴! STDMFT!!S1炻S6炻S1炻MTM!S5! 烊㚱㡅ẞ➟埴炻姕伖㧁娴! ! 4/ BOEˣPSSˣFPS ␴ CJD! 怷廗忳䬿..Ⱦ冯ȿˣȾㆾȿˣȾ䔘ㆾȿ␴Ⱦỵ⃫㶭昌䁢暞ȿˤ! ⎍㱽烉! pq|dpoe~|T~!!Se炻So炻Pqfsboe3! ! ℞ᷕ! pq! 㑵ἄ䡤ˤBOEˣPSSˣFPS ␴ CJD ℞ᷕȹᾳˤ! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! T! ⎗怠㑯䘬⯦䡤ˤ劍㊯⭂ T炻⇯㟡㒂㑵ἄ䳸㝄㚜㕘㡅ẞ䡤㧁娴)Oˣ[ˣ D ␴ W*ˤ! Se! BSN 䳸㝄㙓⬀☐ˤ! ! 第22 頁!
So! ᾅ⬀䫔ᶨ忳䬿⃫䘬 BSN 㙓⬀☐ˤ! Pqfsboe3! 䫔Ḵ忳䬿⃫ˤ! ! BOEˣFPS ␴ PSS ㊯Ẍ↮⇍⬴ㆸ怷廗忳䬿⫸Ⱦ冯)BOE*ȿˣȾ䔘ㆾ)Fydmvtjwf! PS*ȿ␴Ⱦㆾ)PS*ȿ㑵ἄ炻忳䬿⃫㗗 So ␴ Pqfsboe3 䘬ῤˤ! CJD)CJu!Dmfbs*㚫⮯ So 冯䫔ᶱ⍫㔠䘬墄㔠ἄ BOE 忳䬿炻䃞⼴⮯䳸㝄⬀ℍ Seˤ ℞㓰㝄⯙⁷㗗⮯ Se ᷕ冯䚠⮵ㅱ䫔ᶱ⍫㔠墉䁢 2 䘬ỵ⃫㶭昌䁢暞ˤ! 劍㊯⭂ T炻⇯忁ṃ㊯Ẍ⮯烉荛㟡㒂䳸㝄㚜㕘㧁娴 O ␴ [烊荜⛐妰䬿 Pqfsboe3 㗪㚜㕘㧁娴 D烊荝ᶵ⼙枧㧁娴 Wˤ! ἳ⫸烉! BOE!!S:炻S3炻$1yGG11! PSSFR!!S3炻S1炻S6! FPST!!S1炻S1炻S4炻SPS!S7! CJDOFT!!S9炻S21炻S1炻SSY! ! 5/ NPW ␴ NWO! ⁛復␴朆⁛復ˤ! ⎍㱽烉! pq|dpoe~|T~!!Se炻Pqfsboe3! ℞ᷕ烉! pq! 㑵ἄ䡤ˤNPW ␴ NWO ᷕȹᾳˤ! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! T! ⎗怠㑯䘬⯦䡤ˤ劍㊯⭂ T炻⇯㟡㒂㑵ἄ䳸㝄㚜㕘㡅ẞ䡤㧁娴)Oˣ[ˣ D ␴ W*ˤ! Se! BSN 䳸㝄㙓⬀☐ˤ! Pqfsboe3! 䫔Ḵ忳䬿⃫ˤ! ! NPW)NPWf*㊯Ẍ⮯ Pqfsboe3 䘬ῤ㊟居⇘ SeˤNWO)NpWf!Opu*㊯Ẍ⮵ Pqfsboe3 䘬ῤ忚埴㊱ỵ⃫怷廗朆㑵ἄ炻䃞⼴⮯䳸㝄復⇘ Seˤ! !! ἳ⫸烉! !!NPW!!S3炻S2! !!NPW!!S2炻$1y234567! !!NPWT!!S1炻S1炻BTS!S4! ! 6/ DNQ ␴ DNO! 㭼庫␴⍵嘇㭼庫ˤ! ⎍㱽烉! pq|dpoe~!!So炻Pqfsboe3! ! ℞ᷕ烉! pq! 㑵ἄ䡤ˤDNQ ␴ DNO ᷕȹᾳˤ! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! So! ᾅ⬀䫔ᶨ忳䬿⃫䘬 BSN 㙓⬀☐ˤ! ! 第23 頁!
Pqfsboe3! 䫔Ḵ忳䬿⃫ˤ! ! ㊯Ẍ⮯㙓⬀☐䘬ῤ冯 Pqfsboe3 忚埴㭼庫ˤ⬫Ᾱ㟡㒂䳸㝄㚜㕘㡅ẞ䡤㧁娴炻 Ữ䳸㝄ᶵ㓦⇘ảỽ㙓⬀☐ᷕˤ! DNQ)DpNQbsf*㊯Ẍ⽆ So 䘬ῤᷕ㷃⍣ Pqfsboe3 䘬ῤˤ昌⮯䳸㝄᷇㡬⢾炻DNQ ㊯Ẍ⎴ TVCT ㊯Ẍᶨ㧋ˤ! DNO)DpNqbsf!Ofhbujwf*㊯Ẍ⮯ Pqfsboe3 䘬ῤ≈⇘ So 䘬ῤᷕˤ昌⮯䳸㝄᷇ 㡬⢾炻DNO ㊯Ẍ䘬䓐㱽⎴ BEET ᶨ㧋ˤ! DNQ ␴ DNO ㊯Ẍ㟡㒂䳸㝄㚜㕘㧁娴 Oˣ[ˣD ␴ Wˤ! ! ἳ⫸烉! DNQ!!S3炻S4! DNO!!S1炻$234! DNQHU!!S24炻S8炻MTM!$3! ! 7/ UTU ␴ UFR! 㷔娎␴㷔娎䚠䫱ˤ! ⎍㱽烉! pq|dpoe~!!So炻Pqfsboe3! ! ℞ᷕ烉! pq! 㑵ἄ䡤ˤUTU ␴ UFR ᷕȹᾳˤ! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! So! ᾅ⬀䫔ᶨ忳䬿⃫䘬 BSN 㙓⬀☐ˤ! Pqfsboe3! 䫔Ḵ忳䬿⃫ˤ! ! 忁ṃ㊯Ẍὅ㒂 Pqfsboe3 㷔娎㙓⬀☐ᷕ䘬ῤˤ⬫Ᾱ㟡㒂䳸㝄㚜㕘㡅ẞ䡤㧁娴炻 Ữ䳸㝄ᶵ㓦⇘ảỽ㙓⬀☐ᷕˤ! UTU)UfTU*㊯Ẍ⮵ So 䘬ῤ␴ Pqfsboe3 䘬ῤ忚埴ȾBOEȿ㑵ἄˤ昌䳸㝄᷇㡬 ⢾炻≇傥⎴ BOET ㊯Ẍᶨ㧋ˤ! UFR)Uftu!FRvjwbmfodf*㊯Ẍ⮵ So 䘬ῤ␴ Pqfsboe3 䘬ῤ忚埴ȾFPSȿ㑵ἄˤ 昌䳸㝄᷇㡬⢾炻℞≇傥⎴ FPST ㊯Ẍᶨ㧋ˤ! UTU ␴ UFR ㊯Ẍ㟡㒂䳸㝄㚜㕘㧁娴 Oˣ[ˣD ␴ Wˤ! ! ἳ⫸烉! UTU!!S1炻$1y4G9! UFRFR!!S21炻S:! UTUOF!!Sm炻S6炻BTS!Sm! ! 8/ DM[! ⇵⮶暞妰㔠ˤ! ⎍㱽烉! DM[|dpoe~!!Se炻Sn! ! ! 第24 頁!
℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! Se! BSN 䳸㝄㙓⬀☐炻Se ᶵ⃩姙㗗 S26ˤ! Sn! 忳䬿⃫㙓⬀☐ˤ! ! DM[)Dpvou!Mfbejoh![fspt*㊯Ẍ⮵ Sn ᷕ㔠ῤ䘬⇵⮶暞)2fbejoh!{fspt*䘬ᾳ 㔠忚埴妰㔠炻䳸㝄㓦⇘ Se ᷕˤ劍⍇⥳㙓⬀☐ℐ䁢 1炻⇯䳸㝄䁢 43ˤ劍 cju42^ 䁢 m炻⇯䳸㝄䁢 1ˤ! 忁㡅㊯Ẍᶵ⼙枧㡅ẞ䡤㧁娴ˤ! ! ἳ⫸烉! DM[!!S5炻S:! DM[OF!!S3炻S4! ! 9/ NVM ␴ NMB! Ḁ㱽␴Ḁ≈ 43 ỵØ43 ỵ炻䳸㝄䁢Ỷ 43 ỵ⃫ˤ! ⎍㱽烉! NVM|dpoe~|T~!!Se炻Sn炻St! NMB|dpoe~|T~!!Se炻Sn炻St炻So! ! ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! T! ⎗怠㑯⯦䡤ˤ劍㊯⭂ T炻⇯㟡㒂㑵ἄ䳸㝄㚜㕘㡅ẞ䡤㧁娴)Oˣ [ˣD ␴ W*ˤ! Se! 䳸㝄㙓⬀☐ˤ! SnˣStˣSo! 忳䬿⃫㙓⬀☐ˤ! ! S26 ᶵ傥䓐  SeˣSnˣSt ㆾ SoˤSe ᶵ傥冯 Sn 䚠⎴ˤ! NVM)NVMujqmz*㊯Ẍ⮯ Sn ␴ St ᷕ䘬ῤ䚠Ḁ炻᷎⮯㚨Ỷ㚱㓰䘬 43 ỵ⃫䳸㝄㓦 ⇘ Se ᷕˤ! NMB)NvMujqmz!Bddvnvmbuf*㊯Ẍ⮯ Sn ␴ St ᷕ䘬ῤ䚠Ḁ炻ℵ≈ᶲ So 䘬ῤ炻᷎ ⮯㚨Ỷ㚱㓰䘬 43 ỵ⃫䳸㝄㓦⇘ Se ᷕˤ! !劍㊯⭂ T炻⇯忁ṃ㊯Ẍ⮯烉荛㟡㒂䳸㝄㚜㕘㧁娴 O ␴ [烊荜ᶵ⼙枧㧁娴 W烊 荝⛐ BSNw5! !!⍲ẍ⇵䇰㛔ᷕ㧁娴 D ᶵ⎗月烊荞⛐ BSNw6 ⍲ẍ⼴䇰㛔ᷕᶵ⼙枧㧁娴 Dˤ! ! !!ἳ⫸烉! !!NVM!!S21炻S3炻S2! !!NMB!!S21炻S3炻Sm炻S6! !!NVMT!!S21炻S3炻S2! !!NMBWDT!!S9炻S7炻S4炻S9! ! :/ VNVMMˣVNMBMˣTNVMM ␴ TNMBM! 䃉䫎嘇␴ⷞ䫎嘇攟㔜㔠Ḁ㱽␴Ḁ≈)43 ỵØ43 ỵ炻≈㱽ㆾ䳸㝄䁢 75 ỵ⃫*ˤ! ! 第25 頁!
⎍㱽烉! pq|dpoe~|T~!!SeMp炻SeIj炻Sn炻St! ! ℞ᷕ烉! pq! 㑵ἄ䡤ˤVNVMMˣVNMBMˣTNVMM ␴ TNMBM ᷕȹᾳˤ! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! T! ⎗怠㑯䘬⯦䡤ˤ劍㊯⭂ T炻⇯㟡㒂㑵ἄ䳸㝄㚜㕘㡅ẞ䡤㧁 娴)Oˣ[ˣD ␴ W*ˤ! SeMp炻SeIj! BSN 䳸㝄㙓⬀☐ˤ⮵㕤 VNMBM ␴ TNMBM炻忁ℑᾳ㙓⬀☐䓐㕤 ᾅ⬀≈㱽ῤˤ! Sn炻St! 忳䬿⃫㙓⬀☐ˤ! ! S26 ᶵ傥䓐㕤 SeMpˣSeIjˣSn ㆾ StˤSeMpˣSeIj ␴ Sn ⽭枰㗗ᶵ⎴䘬㙓⬀☐ˤ! VNVMM)Votjhofe!Mpoh!NVMujqmz*㊯Ẍ⮯ Sn ␴ St ᷕ䘬ῤ妋慳䁢䃉䫎嘇㔜㔠ˤ 娚㊯Ẍ⮯忁ℑᾳ㔜㔠䚠Ḁ炻᷎⮯䳸㝄䘬㚨Ỷ㚱㓰 43 ỵ⃫㓦⛐ SeMp ᷕ炻㚨檀㚱㓰 43 ỵ⃫㓦⛐ SeIj ᷕˤ! VNMBM)Votjhofe!Mpoh!NvMujqmz!Bddvnvmbuf*㊯Ẍ⮯ Sn ␴ St ᷕ䘬ῤ妋慳䁢 䃉䫎嘇㔜㔠ˤ娚㊯Ẍ⮯忁ℑᾳ㔜㔠䚠Ḁ炻᷎⮯ 75 ỵ⃫䳸㝄≈⇘ SeIj ␴ SeMp ᷕ 䘬 75 ỵ⃫䃉䫎嘇㔜㔠ᶲˤ! TNVMM)Tjhofe!Mpoh!NVMujqmz*㊯Ẍ⮯ Sn ␴ St ᷕ䘬ῤ妋慳䁢ⷞ䫎嘇䘬墄㔠 㔜㔠ˤ娚㊯Ẍ⮯忁ℑᾳ㔜㔠䚠Ḁ炻᷎⮯䳸㝄䘬㚨Ỷ㚱㓰 43 ỵ⃫㓦⛐ SeMp ᷕ炻⮯ 㚨檀㚱㓰 43 ⃫ỵ㓦⛐ SeIj ᷕˤ! TNMBM)Tjhofe!Mpoh!NvMujqmz!Bddvnvmbuf*㊯Ẍ⮯ Sn ␴ St ᷕ䘬ῤ妋慳䁢ⷞ 䫎嘇䘬墄㔠㔜㔠ˤ娚㊯Ẍ⮯忁ℑᾳ㔜㔠䚠Ḁ炻᷎⮯ 75 ỵ⃫䳸㝄≈⇘ SeIj ␴ SeMp ᷕ䘬 75 ỵ⃫ⷞ䫎嘇墄㔠㔜㔠ᶲˤ! 劍㊯⭂ T炻⇯忁ṃ㊯Ẍ⮯烉荛㟡㒂䳸㝄㚜㕘㧁娴 O ␴ [烊荜⛐ BSNw5 ⍲ẍ⇵ 䇰㛔ᷕ㧁娴 D ᶵ⎗月烊荝⛐ BSNw6 ⍲ẍ⼴䇰㛔ᷕᶵ⼙枧㧁娴 D ㆾ Wˤ! ! ἳ⫸烉! VNVMM!!S1炻S5炻S6炻S7! VNMBMT!!S5炻S6炻S4炻S9! TNMBMMFT!!S9炻S:炻S8炻S7! TNVMMOF!!S1炻Sm炻S:炻S1! ! 21/ TNVMyz! ⷞ㚱䫎嘇Ḁ㱽)27 ỵØ27 ỵ炻䳸㝄䁢 43 ỵ⃫*ˤ! ⎍㱽烉! TNVM烋y烍烋z烍|dpoe~!!Se炻Sn炻St! ℞ᷕ烉! 烋y烍! C ㆾ UˤC シ␛叿ἧ䓐 Sn 䘬Ỷ昶)cju26;1^*炻U シ␛叿ἧ䓐 Sn 䘬檀昶)cju42;27^*ˤ! 烋z烍! C ㆾ UˤC シ␛叿ἧ䓐 St 䘬Ỷ昶)cju26;1^*炻U シ␛叿ἧ䓐 St 䘬檀昶)cju42;27^*ˤ! Se! 䳸㝄㙓⬀☐ˤ! ! 第26 頁!
Sn炻St! Ḁ㔠㙓⬀☐ˤ! ! S26 ᶵ傥䓐㕤 SeˣSn ␴ StˤSeˣSn ␴ St ⎗䓐䚠⎴䘬㙓⬀☐ˤ! TNVMyz)Tjhofe!NVMujqmz*㊯Ẍ䓐ẍ⮯ Sn ␴ St ᷕ⎬怠㑯ᶨ⋲䘬 27 ỵ⃫ⷞ㚱 䫎嘇㔜㔠䚠Ḁ炻⮯ 43 ỵ⃫䳸㝄㓦⛐ Se ᷕˤ! 忁㡅㊯Ẍᶵ⼙枧ảỽ㡅ẞ䡤㧁娴ˤ! ! ἳ⫸烉! TNVMUCFR!!S9炻S8炻S:! ! 22/ TNMByz! ⷞ䫎嘇Ḁ≈)27 ỵ⃫Ø27 ỵ炻≈㱽䁢 43 ỵ⃫*ˤ! ⎍㱽烉! TNMB烋y烍烋z烍|dpoe~!!Se炻Sn炻St炻So! ℞ᷕ烉! 烋y烍! C ㆾ UˤC シ␛叿ἧ䓐 Sn 䘬Ỷ昶)cju26;1^*炻U シ␛叿ἧ䓐 Sn 䘬檀昶)cju42;27^*ˤ! 烋z烍! C ㆾ UˤC シ␛叿ἧ䓐 St 䘬Ỷ昶)cju26;1^*炻U シ␛叿ἧ䓐 St 䘬檀昶)cju42;27^*ˤ! Se! 䳸㝄㙓⬀☐ˤ! Sn炻St! Ḁ㔠㙓⬀☐ˤ! So! ≈㔠㙓⬀☐ˤ! ! S26 ᶵ傥䓐  SeˣSnˣSt ㆾ SoˤSeˣSnˣSt ␴ So ⎗䓐䚠⎴䘬㙓⬀☐ˤ! TNMByz)Tjhofe!NvMujqmz!Bddvnvmbuf*㊯Ẍ䓐ẍ⮯ Sn ␴ St ᷕ⎬怠㑯ᶨ⋲䘬 27 ỵ⃫ⷞ䫎嘇㔜㔠䚠Ḁ炻⮯ 43 ỵ⃫䳸㝄≈ᶲ So ᷕ䘬 43 ỵῤ炻㚨䳪䳸㝄㓦⛐ Se ᷕˤ! 忁㡅㊯Ẍᶵ㚫㶭昌㧁娴 Rˤ天㶭昌㧁娴 R炻枰ἧ䓐 NTS ㊯Ẍˤʉ! ! ἳ⫸烉! TNMBUU!!S9炻S22炻S1炻S9! TNMBCCOF!!S1炻S3炻Sm炻S21! ! 23/ NVMXz! ⷞ䫎嘇Ḁ)43 ỵ⃫Ø43 ỵ炻䳸㝄䁢檀 43 ỵ*ˤ! ⎍㱽烉! TNVMX烋z烍|dpoe~!!Se炻Sn炻St! ! ℞ᷕ烉! 烋z烍! C ㆾ UˤC シ␛叿ἧ䓐 St 䘬Ỷ昶)cju26;1^*炻U シ␛叿ἧ䓐 St 䘬檀昶)cju42;27^*ˤ! Se! 䳸㝄㙓⬀☐ˤ! Sn炻St! Ḁ㔠㙓⬀☐ˤ! ! ! 第27 頁!
S26 ᶵ傥䓐  SeˣSnˣㆾ St 䘬ảỽᶨᾳˤảỽ SeˣSn ㆾ St 悥⎗䓐䚠⎴䘬 㙓⬀☐ˤ! TNVMXz)Tjhofe!NVMujqmz*㊯Ẍ䓐ẍ⮯ St ᷕ怠㑯ᶨ⋲䘬ⷞ㚱䫎嘇㔜㔠冯 Sn 䘬ⷞ㚱䫎嘇㔜㔠䚠Ḁ炻⮯ 59 ỵ⃫䳸㝄䘬檀 43 ỵ⃫㓦⛐ Se ᷕˤ! ! ἳ⫸烉! TNVMXC!!S3炻S5炻S8! TNVMXUWT!!S1炻S1炻S:! ! 24/!TNMBXz! ⷞ㚱䫎嘇Ḁ≈)43 ỵ⃫Ø27 ỵ炻䓐檀 43 ỵ⃫忚埴≈㱽*ˤ! ⎍㱽烉! TNMBX烋z烍|dpoe~!!Se炻Sn炻St炻So! ! ℞ᷕ烉! 烋z烍! C ㆾ UˤC シ␛叿ἧ䓐 St 䘬Ỷ昶)cju26;1^*炻U シ␛叿ἧ䓐 St 䘬檀昶)cju42;27^*ˤ! Se! 䳸㝄㙓⬀☐ˤ! Sn炻St! Ḁ㔠㙓⬀☐ˤ! So! ≈㔠㙓⬀☐ˤ! ! S26 ᶵ傥䓐  SeˣSnˣSt ㆾ So 䘬ảỽᶨᾳˤảỽ SeˣSnˣSt ㆾ So ⎗䓐䚠 ⎴䘬㙓⬀☐ˤ! TNMBXz)Tjhofe!NvMujqmz!Bddvnvmbuf*㊯Ẍ䓐ẍ⮯ St ᷕ怠㑯ᶨ⋲䘬ⷞ㚱䫎 嘇㔜㔠冯 Sn ᷕ䘬ⷞ㚱䫎嘇㔜㔠䚠Ḁ炻ℵ⮯ 43 ỵ䳸㝄≈⇘ So ᷕ䘬 43 ỵῤᶲ炻㚨 䳪䳸㝄㓦⛐ Se ᷕˤ! 忁㡅㊯Ẍᶵ⼙枧㧁娴 Oˣ[ˣD ㆾ Wˤ! 劍≈㱽↢䎦㹊↢炻⇯伖ỵ⃫㧁娴 Rˤἧ䓐 NST ㊯ẌἮ嬨㧁娴 R 䘬䉨ンˤ! 忁㡅㊯Ẍᶵ㚫㶭昌 R 㧁娴ˤ天㶭昌 R 㧁娴炻枰ἧ䓐 NTS ㊯Ẍˤ! ! ἳ⫸烉! TNMBXC!!S3炻S5炻S8炻Sm! TNMBXUWT!!S1炻S1炻S:炻S3! ! 25/ TNMBMyz! ⷞ㚱䫎嘇Ḁ≈)27 ỵ⃫Ø27 ỵ炻≈㱽䁢 75 ỵ*ˤ! ⎍㱽烉! TNMBM烋y烍烋z烍|dpoe~!!SeMp炻SeIj炻Sn炻St! ℞ᷕ烉! 烋y烍! C ㆾ UˤC シ␛叿ἧ䓐 Sn 䘬Ỷ昶)cju26;1^*炻U シ␛叿ἧ 䓐 Sn 䘬檀昶)cju42;27^*ˤ! 烋z烍! C ㆾ UˤC シ␛叿ἧ䓐 St 䘬Ỷ昶)cju26;1^*炻U シ␛叿ἧ 䓐 St 䘬檀昶)cju42;27^*ˤ! SeIj炻SeMp! 䳸㝄㙓⬀☐ˤ⬫Ᾱḇᾅ⬀ bee.jo ῤˤ! ! 第28 頁!
Sn炻St! Ḁ㔠㙓⬀☐ˤ! ! TNMBMyz)Tjhofe!NvMujqmz!Bddvnvmbuf*㊯Ẍ䓐ẍ⮯ Sn ␴ St ᷕ⎬怠㑯ᶨ⋲ 䘬ⷞ㚱䫎嘇㔜㔠䚠Ḁ炻ℵ⮯ 43 ỵ䳸㝄≈⇘ SeIj ␴ SeMp ᷕ䘬 75 ỵ⛨ᶲˤ! 忁㡅㊯Ẍᶵ⼙枧ảỽ㧁娴ˤ! 忁㡅㊯Ẍᶵ㚫⺽崟ἳ⢾ˤ劍➟埴忁㡅㊯Ẍ㗪䘤䓇㹊↢炻⇯䳸㝄䑘丆)xsbqt! spvoe*侴ᶵ䘤↢ảỽ嬎⏲ˤ! ! ἳ⫸烉! TNMBMUC!!S3炻S4炻S8炻S2! TNMBMCUWT!!S1炻Sm炻S:炻S3! ! 26/ RBEEˣRTVCˣREBEE ␴ RETVC! 梥␴≈ˣ梥␴㷃ˣ梥␴Ḁ 3 ≈!␴!梥␴Ḁ 3 㷃ˤ! ⎍㱽! pq|dpoe~!!Se炻Sn炻So! ! ℞ᷕ烉! Se! 䳸㝄㙓⬀☐ˤ! SnˣSo! 忳䬿⃫㙓⬀☐ˤ! !! RBEE)tbuvsbujoh!BEE*㊯Ẍ⮯ Sn ␴ So 䘬ῤ䚠≈ˤ! RTVC)tbuvsbujoh!TVCusbdu*㊯Ẍ⽆ Sn 䘬ῤᷕ㷃⍣ So 䘬ῤˤ! REBEE)tbuvsbujoh!Epvcmf!boe!BEE*㊯Ẍ妰䬿 TBU)Sn,TBU)So+3**ˤ梥␴⎗ 䘤䓇⛐≈᾵㑵ἄˣ≈㱽ᶲ炻ㆾℑ䧖ね㱩ᶳ⎴㗪䘤䓇ˤ劍梥␴䘤䓇⛐≈᾵㑵ἄᶲ炻 ⇯㧁娴 R 伖ỵ⃫炻Ữ㚨⼴䳸㝄㗗ᶵ梥␴䘬ˤ! RETVC)tbuvsbujoh!Epvcmf!boe!TVCusbdu*㊯Ẍ妰䬿 TBU)Sn.TBU)So+3**ˤ梥 ␴⎗䘤䓇⛐≈᾵㑵ἄˣ≈㱽ᶲ炻ㆾℑ䧖ね㱩ᶳ⎴㗪䘤䓇ˤ劍梥␴䘤䓇⛐≈᾵㑵 ἄᶲ炻⇯㧁娴 R 伖ỵ⃫炻Ữ㚨⼴䳸㝄㗗ᶵ梥␴䘬ˤ! 忁ṃ㊯Ẍ㈲㇨㚱ῤ䚳 ⷞ㚱䫎嘇䘬墄㔠㔜㔠ˤ! 忁ṃ㊯Ẍᶵ⼙枧㧁娴 Oˣ[ˣD ␴ Wˤ劍↢䎦梥␴炻⇯伖ỵ⃫㧁娴 Rˤἧ䓐 NST ㊯ẌἮ嬨㧁娴 R 䘬䉨ンˤ! ⌛ἧ㗗梥␴ᶵ↢䎦炻忁ṃ㊯Ẍḇ⽆ᶵ㶭昌 R 㧁娴ˤἧ䓐 NTS ㊯Ẍ㶭昌 R 㧁娴ˤ! ! ἳ⫸烉! RBEE!!S1炻Sm炻S:! RETVCMU!!S:炻S1炻Sm! ! 3.3 跳轉指令 2/ C ␴ CM! 嶛廱␴ⷞ㚱捰䳸嶛廱ˤ! ⎍㱽烉! C|dpoe~!!mbcfm! ! 第29 頁!
CM|dpoe~!!mbcfm! ! ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! 2bcfm! 䦳⺷䚠⮵ῷ䦣忳䬿⺷ˤ! ! C)Csbodi*㊯Ẍ⺽崟嗽䎮☐廱䦣⇘ 2bcfmˤ! CM)Csbodi!xjui!Mjol*㊯Ẍ⮯ᶳᶨ㡅㊯Ẍ䘬ỵ⛨㊟居⇘ S25)捰䳸㙓⬀☐*炻 ᷎廱䦣⇘ 2bcfmˤ! 㨇☐䳂䘬 C ␴ CM ㊯Ẍ旸⇞⛐䚖⇵㊯Ẍ䘬²43Nc 䭬⚵ℏˤỮ㗗炻⌛ἧ mbcfm 崭 ↢Ḯ娚䭬⚵炻ḇ⎗ẍἧ䓐忁ṃ㊯Ẍˤ! ! ἳ⫸烉! C!!MppqB! CMF!!oh,9! !! 3/ CY! 嶛廱᷎⎗怠㑯⛘Ṍ㎃㊯Ẍ普ˤ! ⎍㱽烉! CY|dpoe~!!Sn! ! ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! Sn! ⏓㚱廱䦣ỵ⛨䘬㙓⬀☐ˤSn 䘬 cju1^ᶵ䓐Ἦἄ䁢⛘⛨䘬ᶨ悐↮ˤ劍 Sn 䘬 cju1^䁢 m炻⇯㊯Ẍ⮯ DQTS ᷕ䘬㧁娴 U 伖ỵ⃫炻ᶼ⮯䚖㧁ỵ⛨ 䘬ẋ䡤妋慳䁢 Uivnc ẋ䡤ˤ劍 Sn 䘬 cju1^䁢 1炻⇯ cju2^⯙ᶵ傥䁢 mˤ! ! ➟埴 CY)Csbodi!boe!pqujpobmmz!fYdibohf*㊯Ẍ⮯⺽崟嗽䎮☐廱䦣⇘ Sn ᷕ 䘬ỵ⛨ˤ劍 Sn 䘬 cju1^䁢 2炻⇯㊯Ẍ普嬲㎃⇘ Uivncˤ! ! ἳ⫸烉! CY!!S8! CYWT!!S1! ! 4/ CMY! ⷞ㚱捰䳸嶛廱᷎⎗怠⛘Ṍ㎃㊯Ẍ普ˤ忁㡅㊯Ẍ㚱⤪ᶳ 3 䧖⼊⺷烉! 2/!ⷞ㚱捰䳸䃉㡅ẞ廱䦣⇘䦳⺷䚠⮵ῷ䦣ỵ⛨ˤ! 3/!ⷞ㚱捰䳸㚱㡅ẞ廱䦣⇘㙓⬀☐ᷕ䘬䳽⮵ỵ⛨ˤ! ⎍㱽烉! CMY|dpoe~!!Sn! CMY!!mbcfm! ! ℞ᷕ烉! ! 第2: 頁!
dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! Sn! ⏓㚱廱䦣ỵ⛨䘬㙓⬀☐ˤSn 䘬 cju1^ᶵ䓐Ἦἄ䁢⛘⛨䘬ᶨ悐↮ˤ 劍 Sn 䘬 cju1^䁢 2炻⇯㊯Ẍ⮯ DQTS ᷕ䘬㧁娴 U 伖ỵ⃫炻ᶼ⮯䚖㧁 ỵ⛨䘬ẋ䡤妋慳䁢 Uivnc ẋ䡤ˤ劍 Sn 䘬 cju1^䁢 1炻⇯ cju2^⯙ ᶵ傥䁢 2ˤ! Mbcfm! 䦳⺷䚠⮵ῷ䦣忳䬿⺷ˤ! ! ȾCMY!mbcfmȿᶵ傥㗗㚱㡅ẞ䘬ˤ⬫⥳䳪⺽崟嗽䎮☐↯㎃⇘ Uivnc 䉨ンˤ! CMY)Csbodi!xjui!Mjol!boe!pqujpobmmz!fYdibohf*㊯Ẍ㚱⤪ᶳ䓐㱽烉! 2/ ⮯ᶳᶨ㡅㊯Ẍ䘬ỵ⛨㊟居⇘ S25 ᷕ)捰䳸㙓⬀☐*ˤ! 3/ 廱䦣⇘ mbcfm ㆾ Sn ᷕ䘬⛘⛨ˤ! 4/ 劍ᶳ朊ℑ㡅ᷕ䘬ảỽᶨ㡅ㆸ䩳炻⇯⮯㊯Ẍ普↯㎃⇘ Uivnc烉! ..!Sn 䘬 cju1^䁢 2! !!!!!!!!..!ἧ䓐ȾCMY!mbcfmȿ⼊⺷! 㨇☐䳂䘬ȾCMY!mbcfmȿ㊯Ẍᶵ傥廱䦣⇘䚖⇵㊯Ẍ⛇ 43NC 䭬⚵ᷳ⢾䘬ỵ⛨ˤ! !!!!! ἳ⫸烉! CMY!!S3! CMYOF!!S1! CMY!!uivnctvc! ! 3.4 輔助運算器指令 2/ DEQ ␴ DEQ3! 庼≑忳䬿☐屯㕁㑵ἄ)DEQ炻Dpqspdfttps!Ebub!pQfsbujpo*ˤ! ⎍㱽烉! DEQ|dpoe~!!dpqspd炻pqdpef2炻DSe炻DSo炻DSn|炻pqdpef3~! DEQ3!!dpqspd炻pqdpef2炻DSe炻DSo炻DSn|炻pqdpef3~! ! ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! dpqspd! ㊯Ẍ㑵ἄ䘬庼≑忳䬿☐⎵䧙ˤ㧁㸾⎵䧙䁢 qo炻℞ᷕ o 䁢 1 ᶨ 26 䭬⚵ℏ䘬㔜㔠ˤ! Pqdpef2! 庼≑忳䬿☐䘬䈡⭂㑵ἄ䡤ˤ! DSe炻DSo炻DSn! 庼≑忳䬿☐㙓⬀☐ˤ! pqdpef3! ⎗怠㑯䘬庼≑忳䬿☐䈡⭂㑵ἄ䡤ˤ! !! 忁ṃ㊯Ẍ䘬ἧ䓐⍾㰢㕤庼≑忳䬿☐ˤ! DEQ3 ⥳䳪㗗䃉㡅ẞ䘬ˤ! ! 3/ NDSˣNDS3 ␴ NDSS! ⮯屯㕁⽆ BSN 㙓⬀☐⁛復⇘庼≑忳䬿☐ˤ⎗㊯⭂⎬䧖旬≈㑵ἄ炻ὅ㒂庼≑忳 䬿☐侴⭂ˤ! ⎍㱽烉! NDS|dpoe~!!dpqspd炻pqdpef2炻Se炻DSo炻DSn|炻pqdpef3~! ! 第31 頁!
NDS3!!dpqspd炻pqdpef2炻Se炻DSo炻DSn|炻pqdpef3~! NDSS|dpoe~!!dpqspd炻pqdpef2炻Se炻So炻DSn! ! ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! dpqspd! ㊯Ẍ㑵ἄ䘬庼≑忳䬿☐⎵䧙ˤ㧁㸾⎵䁢 qo炻℞ᷕ o 䁢 1 ᶨ 26 䭬⚵ℏ䘬㔜㔠ˤ! Pqdpef2! 庼≑忳䬿☐䘬䈡⭂㑵ἄ䡤ˤ! Se炻So! ⍇⥳㙓⬀☐炻ᶵ⃩姙㗗 S26ˤ! DSo炻DSn! 庼≑忳䬿☐㙓⬀☐ˤ! pqdpef3! ⎗怠㑯䘬庼≑忳䬿☐䈡⭂㑵ἄ䡤ˤ! ! 忁ṃ㊯Ẍ䘬ἧ䓐⍾㰢㕤庼≑忳䬿☐ˤ! NDS3 ⥳䳪㗗䃉㡅ẞ䘬ˤ! ! B/ NSDˣNSD3 ␴ NSSD! ⮯屯㕁⽆庼≑忳䬿☐⁛復⇘ BSN 㙓⬀☐ˤ⎗㊯⭂⎬䧖旬≈㑵ἄ炻ὅ㒂庼≑忳 䬿☐侴⭂ˤ! ⎍㱽烉! NSD|dpoe~!!dpqspd炻pqdpef2炻Se炻DSo炻DSn|炻pqdpef3~! NSD3!!dpqspd炻pqdpef2炻Se炻DSo炻DSn|炻pqdpef3~! NSSD|dpoe~!!dpqspd炻pqdpef2炻Se炻So炻DSn! ! ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! dpqspd! ㊯Ẍ㑵ἄ䘬庼≑忳䬿☐⎵䧙ˤ㧁㸾⎵䁢 qo炻℞ᷕ o 䁢 1 ᶨ 26 䭬⚵ℏ䘬㔜㔠ˤ! Pqdpef2! 庼≑忳䬿☐䘬䈡⭂㑵ἄ䡤ˤ! Se炻So! ⍇⥳㙓⬀☐炻ᶵ⃩姙㗗 S26ˤ! DSo炻DSn! 庼≑忳䬿☐㙓⬀☐ˤ! pqdpef3! ⎗怠㑯䘬庼≑忳䬿☐䈡⭂㑵ἄ䡤ˤ! ! 忁ṃ㊯Ẍ䘬ἧ䓐⍾㰢㕤庼≑忳䬿☐ˤ! NSD3 ⥳䳪㗗䃉㡅ẞ䘬ˤ! ! C/ MED ␴ TUD! ⛐姀ㅞ橼␴庼≑忳䬿☐ᷳ攻⁛復屯㕁ˤ! ⎍㱽烉! 忁ṃ㊯Ẍ㚱 4 䧖⎗傥⼊⺷烉! 暞ῷ䦣烉pq|dpoe~|M~!!dpqspd炻DSe炻So^! ⇵䳊⺽ῷ䦣烉pq|dpoe~|M~!!dpqspd炻DSe炻So炻$|.~pggtfu^|"~! ⼴䳊⺽ῷ䦣烉pq|dpoe~|M~!!dpqspd炻DSe炻So^炻$|.~pggtfu! ! ℞ᷕ烉! ! 第32 頁!
dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! M! ⎗怠㑯⯦䡤炻㊯㖶㗗攟㔜㔠⁛復ˤ! dpqspd! ㊯Ẍ㑵ἄ䘬庼≑忳䬿☐⎵䧙ˤ㧁㸾⎵䧙䁢 qo炻℞ᷕ o 䁢 1ȹ26 䭬⚵ℏ䘬㔜㔠ˤ! DSe! 䓐㕤庱ℍㆾ⃚⬀䘬庼≑忳䬿☐㙓⬀☐ˤ! So! 姀ㅞ橼➢⛨㙓⬀☐ˤ劍㊯⭂ S26炻⇯ἧ䓐䘬ῤ㗗䔞⇵㊯Ẍỵ⛨≈ 9ˤ! pggtfu! 忳䬿⺷炻℞ῤ䁢 5 䘬㔜᾵㔠炻䭬⚵⛐ 1ȹ2131 ᷳ攻ˤ! !! 忁ṃ㊯Ẍ䘬ἧ䓐⍾㰢㕤庼≑忳䬿☐ˤ! ! D/ MED3 ␴ TUD3! ⛐姀ㅞ橼␴庼≑忳䬿☐ᷳ攻⁛復屯㕁䘬㊯Ẍˤ㟡㒂屯㕁⁛復㕡⎹⎗ẍ怠㑯ℑ 侭℞ᶨˤ! ⎍㱽烉! 忁ṃ㊯Ẍ㚱 4 䧖⎗傥䘬⼊⺷烉! 暞ῷ䦣烉pq!!dpqspd炻DSe炻So^! ⇵䳊⺽ῷ䦣烉pq!!dpqspd炻DSe炻So炻$|.~pggtfu^|"~! ⼴䳊⺽ῷ䦣烉pq!!dpqspd炻DSe炻So^炻$|.~pggtfu! ! ℞ᷕ烉! dpqspd! ㊯Ẍ㑵ἄ䘬庼≑忳䬿☐⎵䧙ˤ㧁㸾⎵䧙䁢 qo炻℞ᷕ o 䁢 1ȹ26 䭬⚵ℏ䘬㔜㔠ˤ! DSe! 䓐㕤庱ℍㆾ⃚⬀䘬庼≑忳䬿☐㙓⬀☐ˤ! So! 姀ㅞ橼➢⛨㙓⬀☐ˤ劍㊯⭂ S26炻⇯ἧ䓐䘬ῤ㗗䔞⇵㊯Ẍỵ⛨≈ 9ˤ! pggtfu! 忳䬿⺷炻℞ῤ䁢 5 䘬㔜᾵㔠炻䭬⚵⛐ 1ȹ2131 ᷳ攻ˤ! ! 忁ṃ㊯Ẍ䘬ἧ䓐⍾㰢㕤庼≑忳䬿☐ˤ! MED3 ␴ TUD3 ⥳䳪㗗䃉㡅ẞ䘬ˤ! ! 3.5 雜項指令 2/ TXJ! 庇橼ᷕ㕟ˤ! ⎍㱽烉! TXJ|dpoe~!!jnnfe`35! ! ℞ᷕ烉jnnfe`35 䁢忳䬿⺷ˤ℞ῤ䁢 1!ȹ!)335.2*!䭬⚵ℏ䘬㔜㔠)35 ỵ⃫㔜㔠*ˤ! ! TXJ)TpguXbsf!Joufssvqu*㊯Ẍ⺽崟 TXJ ἳ⢾ˤ忁シ␛叿嗽䎮☐㧉⺷嬲㎃䁢 䭉䎮㧉⺷炻DQTS ᾅ⬀⇘䭉䎮㧉⺷䘬 TQTS ᷕ炻➟埴廱䦣⇘ TXJ ⎹慷ˤ! 忁㡅㊯Ẍᶵ⼙枧㡅ẞ䡤㧁娴ˤ! ! ! 第33 頁!
ἳ⫸烉! TXJ!!1y234567! ! 3/ NST! ⮯ DQTS ㆾ TQTS 䘬ℏ⭡⁛復⇘ᶨ凔䓐徼㙓⬀☐ˤ! ⎍㱽烉! NST|dpoe~!!Se炻qts! ! ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! Se! 䚖㧁㙓⬀☐ˤSe ᶵ⃩姙䁢 S26ˤ! qts! DQTS ㆾ TQTSˤ! ! NST 冯 NTS 惵⎰ἧ䓐炻ἄ䁢㚜㕘 QTS 䘬Ⱦ嬨ᶨᾖ㓡ȹ⮓ȿ⸷↿䘬ȹ悐↮ˤἳ ⤪烉㓡嬲嗽䎮☐㧉⺷ㆾ㶭昌㧁娴 Rˤ! 䔞嗽䎮☐⛐ἧ䓐侭㧉⺷ㆾ䲣䴙㧉⺷ᶳ㗪炻ᶨ⭂ᶵ傥娎⚾⬀⍾ TQTSˤ! 忁㡅㊯Ẍᶵ⼙枧㡅ẞ䡤㧁娴ˤ! ἳ⫸烉! NTS!!S4炻TQTS! ! B/ NTS! 䓐䩳⌛㔠ⷠ㔠ㆾᶨ凔䓐徼㙓⬀☐䘬ℏ⭡庱ℍ DQTS ㆾ TQTS 䘬㊯⭂⋨➇ˤ! ⎍㱽烉! NTS|dpoe~!!=qts?`=gjfmet?炻$jnnfe`9s! NTS|dpoe~!!=qts?`=gjfmet?炻Sn! ! ℞ᷕ烉! =qts?! DQTS ㆾ TQTSˤ! =gjfmet?! ㊯⭂⁛復䘬⋨➇ˤ=gjfmet?⎗ẍ㗗ẍᶳ䘬ȹ䧖ㆾ⣂䧖烉! d! ㍏⇞➇怖休ỵ⃫䳬)QTS8;1^*! y! 㒜⯽➇怖休ỵ⃫䳬)QTSm6;9^*! t! 䉨ン➇怖休ỵ⃫䳬)QTS34;27^*! g! 㧁娴➇怖休ỵ⃫䳬)QTS42;35^*! jnnfe`9s! ῤ䁢㔠⫿ⷠ㔠䘬忳䬿⺷ˤⷠ㔠⽭枰⮵ㅱ 9 ỵ溆昋⚾ˤ娚溆昋⚾ ⛐ 43 ỵ⃫ᷕ徜⚰䦣ỵ„㔠ỵˤ! Sn! Ἦ㸸㙓⬀☐ˤ! !! NST 冯 NTS 䚠惵⎰ἧ䓐炻ἄ䁢㚜㕘 QTS 䘬Ⱦ嬨ȹᾖ㓡ȹ⮓ȿ⸷↿䘬ȹ悐↮ˤ ἳ⤪烉㓡嬲嗽䎮☐㧉⺷ㆾ㶭昌㧁娴 Rˤ! 劍㊯⭂ g)gjfme*炻⇯㊯Ẍ栗⺷㚜㕘㧁娴ˤ! ! ἳ⫸烉! NTS!!DQTS`g炻S6! ! ! 第34 頁!
C/ CLQU! ᷕ㕟溆㊯Ẍˤ! ⎍㱽烉! CLQU!!jnnfe`27! ! ℞ᷕ烉jnnfe`27 䁢忳䬿⺷ˤ℞ῤ䁢䭬⚵⛐ 1ȹ76647 ℏ䘬㔜㔠)27 ỵ⃫㔜㔠*ˤ! ! CLQU)CsfbLQpjoU*㊯Ẍ⺽崟嗽䎮☐忚ℍ昌拗㧉⺷ˤ昌拗ⶍ℟⎗ἧ䓐忁ᶨ溆⛐ ㊯Ẍ⇘忼䈡⭂䘬ỵ⛨㗪婧㞍䲣䴙䉨ンˤ! ! ἳ⫸烉! CLQU!!1yG13D! CLQU!!751! ! 3.6 虛擬指令 2/ BES! ⮯䦳⺷䚠⮵ῷ䦣ㆾ㙓⬀☐䚠⮵ῷ䦣ỵ⛨庱ℍ⇘㙓⬀☐ᷕˤ! ⎍㱽烉! BES|dpoe~!!sfhjtufs炻fyqs! ! ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! sfhjtufs! 庱ℍ䘬㙓⬀☐ˤ! Fyqs! 䦳⺷䚠⮵ῷ䦣ㆾ㙓⬀☐䚠⮵ῷ䦣忳䬿⺷炻⍾ῤ䁢! ..!朆 xpse ⮵㸾ỵ⛨炻⛐.366ȹ,366 ỵ⃫䳬䭬⚵ℏˤ! ..!xpse ⮵㸾ỵ⛨炻⛐.2131ȹ,2131 ỵ⃫䳬䭬⚵ℏˤ! ! ⮵㕤䦳⺷䚠⮵ῷ䦣忳䬿⺷炻䴎⭂䭬⚵㗗䚠⮵䚖⇵㊯Ẍỵ⛨⼴ℑᾳ⫿嗽ˤ! BES ⥳䳪⼁䶐ㆸ m 㡅㊯Ẍˤ⼁䶐☐娎⚾䓊䓇╖ᾳ BEE ㆾ TVC ㊯ẌἮ庱ℍỵ⛨ˤ 劍ỵ⛨ᶵ傥㓦Ṣ m 㡅㊯Ẍ炻⇯䓊䓇拗婌炻⼁䶐⣙㓿ˤ! ⚈䁢ỵ⛨㗗䦳⺷䚠⮵ῷ䦣ㆾ㙓⬀☐䚠⮵ῷ䦣炻BES 䓊䓇ỵ伖䃉斄䘬ẋ䡤ˤ! ἧ䓐 BESM 嘃㒔㊯Ẍẍ⼁䶐㚜⮔䘬㚱㓰ỵ⛨䭬⚵ˤ! 劍 fyqs 㗗䦳⺷䚠⮵ῷ䦣炻⇯⬫⽭枰⍾ῤㆸ冯 BES 嘃㒔㊯Ẍ⛐⎴ᶨẋ䡤⋨➇ 䘬ỵ⛨ˤ! ! ἳ⫸烉! tubsu! NPW!!S1炻$21! BES!!S5炻tubsu! ! 3/ BESM! ⮯䦳⺷䚠⮵ῷ䦣ㆾ㙓⬀☐䚠⮵ῷ䦣ỵ⛨庱ℍ⇘㙓⬀☐ᷕˤBESM 栆Ụ㕤 BES 嘃 㒔㊯ẌˤBESM ⚈䁢䓊䓇 3 ᾳ屯㕁嗽䎮㊯Ẍ炻㭼 BES ⎗庱ℍ㚜⮔䭬⚵䘬ỵ⛨ˤ! ⛐⼁䶐 Uivnc ㊯Ẍ㗪 BESM 䃉㓰ˤBESM 䓐⛐ BSN ẋ䡤ᷕˤ! ⎍㱽烉! ! 第35 頁!
BESM|dpoe~!!sfhjtufs炻fyqs! ! ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! sfhjtufs! 庱ℍ䘬㙓⬀☐ˤ! fyqs! 䦳⺷䚠⮵ῷ䦣ㆾ㙓⬀☐䚠⮵ῷ䦣忳䬿⺷炻⍾ῤ䁢! ..!朆 xpse ⮵㸾⛘⛨炻⛐ 75LC 䭬⚵ℏˤ! ..!xpse ⮵㸾⛘⛨炻⛐ 367LC 䭬⚵ℏˤ! ! ⮵㕤䦳⺷䚠⮵ῷ䦣忳䬿⺷炻䴎⭂䭬⚵㗗䚠⮵䚖⇵㊯Ẍỵ⛨⼴ℑᾳ⫿嗽ˤʉ! BESM ⥳䳪⼁䶐ㆸ 3 㡅㊯Ẍˤ⌛ἧỵ⛨⎗㓦ℍ 2 㡅㊯Ẍ炻ḇ䓊䓇䫔 3 㡅∑检㊯ Ẍˤ劍⼁䶐☐ᶵ傥⮯ỵ⛨㓦ℍ 3 㡅㊯Ẍ炻⇯䓊䓇拗婌炻⼁䶐⣙㓿ˤ! ⚈䁢ỵ⛨㗗䦳⺷䚠⮵ῷ䦣ㆾ㙓⬀☐䚠⮵ῷ䦣炻BESM 䓊䓇ỵ伖䃉斄䘬ẋ䡤ˤ! 劍 fyqs 㗗䦳⺷䚠⮵ῷ䦣炻⇯⽭枰⍾ῤㆸ冯 BESM 嘃㒔㊯Ẍ⛐⎴ᶨẋ䡤⋨➇䘬 ỵ⛨烊⏎⇯捰䳸⼴⎗傥崭↢䭬⚵ˤ! ! ἳ⫸烉! tubsu! ! NPW!!S1炻$21! BESM!!S5炻tubsu,7111! ! B/ MES! 䓐 43 ỵ⃫ⷠ㔠ㆾᶨᾳỵ⛨庱ℍ㙓⬀☐ˤ! ⎍㱽烉! MES|dpoe~!!sfhjtufs炻>fyqs!}!mbcfm.fyqs^! ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! ! sfhjtufs! 庱ℍ䘬㙓⬀☐ˤ! fyqs! 䴎ῤㆸ㔠⫿ⷠ㔠ˤ! ..!劍 fyqs ῤ㗗⛐㊯Ẍ䘬䭬⚵ℏ炻⇯⼁䶐☐䓊䓇ᶨ㡅 NPW ㆾ NWO ㊯Ẍˤ! ..!劍 fyqs ῤᶵ⛐ NPW ㆾ NWO ㊯Ẍ䘬䭬⚵ℏ炻⇯⼁䶐☐⮯ⷠ㔠㓦 ℍ 2jufsbm!qppm炻᷎䓊䓇ᶨ㡅䦳⺷䚠⮵ῷ䦣䘬 MES ㊯Ẍ⽆ 2jufsbm!qppm 嬨ⷠ㔠ˤ! mbcfm.fyqs!䦳⺷䚠⮵ῷ䦣ㆾ⢾悐忳䬿⺷ˤ⼁䶐☐⮯ mbcfm.fyqs 䘬ῤ㓦ℍ 2jufsbm!qppm炻᷎䓊䓇ᶨ㡅䦳⺷䚠⮵ῷ䦣䘬 MES ㊯Ẍ⽆ mjufsbm! qppm ᷕ庱ℍῤˤ劍 mbcfm.fyqs 㗗⢾悐忳䬿⺷炻ㆾᶵ⊭⏓⛐䚖⇵ ⋨➇ℏ炻⇯⼁䶐☐⮯ᶨᾳ捰䳸☐⎗慵⭂ỵ㊯Ẍ㓦ℍ䚖㧁㨼ˤ捰䳸 ☐⛐捰䳸㗪䓊䓇ỵ⛨ˤ! ! MES)MpbE!Sfhjtufs*嘃㒔㊯Ẍ䓐㕤 3 ᾳᷣ天䚖䘬烉! 2/ 䔞䩳⌛㔠ῤ䓙㕤崭↢ NPW ␴ NWO ㊯Ẍ䭬⚵侴ᶵ傥庱ℍ⇘㙓⬀☐ᷕ㗪炻䓊 䓇㔯⫿ⷠ㔠ˤ! 3/ ⮯䦳⺷䚠⮵ῷ䦣ㆾ⢾悐ỵ⛨庱ℍ⇘㙓⬀☐ᷕˤỵ⛨ᾅ㊩㚱㓰侴冯捰䳸☐ ! 第36 頁!
⮯⊭⏓ MES 䘬 FMG ⋨➇㓦⇘ỽ嗽䃉斄ˤ! 忁䧖㕡㱽庱ℍ䘬ỵ⛨⛐䄼㍍㗪㗗⚢⭂䘬炻⚈侴ẋ䡤冯ỵ伖㚱斄ˤ! ⽆ QD ⇘ mjufsbm!qppm ᷕῤ䘬ῷ䦣慷⽭枰⮷㕤 5LCˤ攳䘤侭⽭枰䡢ᾅ⛐㊯Ẍ 䭬⚵ℏ㚱ᶨᾳ mjufsbm!qppmˤ! ἳ⫸烉! MES!!S4炻>1ygg1! MES!!S2炻>qmbdf! ! C/ OPQ! OPQ 䓊䓇㇨暨䘬 BSN 䃉㑵ἄẋ䡤ˤ! ⎍㱽烉! OPQ! ! OPQ)Op!PQfsbujpo*ᶵ傥㚱㡅ẞἧ䓐ˤ➟埴␴ᶵ➟埴䃉㑵ἄ㊯Ẍ㗗ᶨ㧋䘬炻 ⚈侴ᶵ暨天㚱㡅ẞ➟埴ˤ! BMV 䉨ン㧁娴ᶵ⍿ OPQ ⼙枧ˤ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! 第37 頁!
1 UEE3303 Introduction to Embedded Systems Lecture 4 Cortex Processors YuLun Huang http://rtes.cn.nctu.edu.tw UEE 3303 <1> YL Huang Spring ‘14 © NCTU Cortex Profiles ° 2004, ARM introduced new Cortex family of processors ° Three profiles • Cortex-A: high-end application processor • Cortex-R: real-time processor • Cortex-M: microcontroller UEE 3303 <2> YL Huang Spring ‘14 © NCTU Cortex-M Profiles ° Cortex-M0, Cortex-M0+ • Smallest processor in the family • Low-cost, low-power • Replacement of the existing 8-bit uC (still offering 32-bit performance) ° Cortex-M1 • Similar to M0, but designed as a soft core (running on FPGA) ° Cortex-M3 • High performance uC ° Cortex-M4 • +DSP • +FPU UEE 3303 <3> YL Huang Spring ‘14 © NCTU 8051 vs. Cortex-M0 ° M0 is a reduced version of M3, but keeps good performance model ° The example is a 16 x 16 mult • multiplies r1 & r0, and put the results in r0 UEE 3303 <4> YL Huang Spring ‘14 © NCTU
2 Cortex-M0 vs. Cortex-M0+ ° Cortex-M0+ is fully compatible with Cortex-M0 ° Cortex-M0+ has more advanced features • More processing power and lower power consumption - 11 uW vs. 16 uW • 2-stage pipeline to reduce number of memory accesses and runtime energy consumption UEE 3303 <5> YL Huang Spring ‘14 © NCTU New peripheral I/O interface ° New I/O interface supports single cycle access to peripheral registers ° Cortex-M0+ can fetch instruction via AHB while making a data access to the peripheral registers UEE 3303 <6> YL Huang Spring ‘14 © NCTU Cortex-M3 ° The mainstay of the Cortex-M family ° High-performance 32-bit uC ° 3-stage pipeline: Fetch, Decode, Execute ° Like the ARM7, it is a RISC processor: most instructions execute in a single cycle ° Manufactured at a very low cost UEE 3303 <7> YL Huang Spring ‘14 © NCTU Cortex-M3 Pipeline ° ARM instructions ° Thumb instructions ° Thumb-2 instructions • a blend of 16- and 32-bit instructions UEE 3303 <8> YL Huang Spring ‘14 © NCTU
3 Cortex-M4 ° M3 + DSP + Floating Point Support: single precision Support event-driven microcontroller code UEE 3303 <9> YL Huang Spring ‘14 © NCTU In this class, we have ° PTK using Cortex-M3 ° K60D using Cortex-M4 UEE 3303 <10> YL Huang Spring ‘14 © NCTU
1 UEE3303 Introduction to Embedded Systems Lecture 5 PTK YuLun Huang http://rtes.cn.nctu.edu.tw UEE 3303 <1> YL Huang Spring’14 © NCTU PTK ° Contains a PTK-BASE and a PTK-MCU • NOTE: LED2 & 3 are not workable in our target board UEE 3303 <2> YL Huang Spring’14 © NCTU (What we have?) Top side of PTK-BASE UEE 3303 <3> YL Huang Spring’14 © NCTU Hardware Installation ° PTK ° DC-12V ° JTAG (debugger) UEE 3303 <4> YL Huang Spring’14 © NCTU
2 GPIO UEE 3303 <5> YL Huang Spring’14 © NCTU LEDs (LED0 ~ LED3) UEE 3303 <6> YL Huang Spring’14 © NCTU 7-Segment (HEX1) UEE 3303 <7> YL Huang Spring’14 © NCTU Button (KEY0 ~ KEY3, RESET) UEE 3303 <8> YL Huang Spring’14 © NCTU
3 DIP Switch (SW1) 1 DIP Switch with 4 bits connected to MCU for input UEE 3303 <9> YL Huang Spring’14 © NCTU Buzzer (SU1) • The only audible device in PTK-BASE • Should be connected to a clock signal for generating beep • You can change the tone of buzzer by changing the frequency of clock input UEE 3303 <10> YL Huang Spring’14 © NCTU Sensors ° Built-in Sensors • Potentiometer (VR1) • Light Sensor (U3) • Temperature Sensor (U5) • Infrared TX/RX ° Extended Sensor Modules • Follow the PTK-MEMS module design specification, you can design your own sensor modules UEE 3303 <11> YL Huang Spring’14 © NCTU I/O Map for Light Sensor (U3: ISL29023) ° Full-scale Range: 1000 lux~64000lux ° Human eye response ° 16-bit resolution ° Programmable upper and lower threshold interrupt ° The I2C device address is 0x44 • PTK-MCU uses I2C bus to link ISL29023 for setup and retrieving ambient light data UEE 3303 <12> YL Huang Spring’14 © NCTU
4 Storage ° EEPROM (U6) ° SD Socket (CN13) UEE 3303 <13> YL Huang Spring’14 © NCTU Communication ° Ethernet (CN16) ° USB (CN15) ° RS-485 & CAN (CN12, JP3) ° RS-232 (CN11) UEE 3303 <14> YL Huang Spring’14 © NCTU
1 UEE3303 Introduction to Embedded Systems Lecture 6 Embedded System Development YuLun Huang http://rtes.cn.nctu.edu.tw UEE 3303 <1> YL Huang Spring‘14 © NCTU Hardware and Software Co-Design Model ° Hardware and software for an embedded system are developed in parallel • Software component can take advantage of special hardware features to gain performance • Hardware component can simplify module design if functionality can be achieved in software - Reduce overall hardware complexity and cost • Co-design model emphasized the fundamental characteristics of embedded systems: APPLICATION-SPECIFIC UEE 3303 <2> YL Huang Spring‘14 © NCTU Cross-Platform Development ° Platform: • Hardware (processor) • Operating System • Software Development tools ° Software for an embedded system is developed on one platform but runs on another. • Host system: where the software is developed • Target system: embedded system under development ° Cross-Compiler • Compiler that runs on one type of processor architecture but produces object code for a different type of processor architecture - Host: Intel (IA-32/IA64) - Target: ARM/MIPS UEE 3303 <3> YL Huang Spring‘14 © NCTU Cross-platform Host System Target System HEWLET PACKARD Serial Host Resident Software Target Resident ICE Ethernet JTAG Software Application API layer File system layer Logical block layer Device driver Hardware layer UEE 3303 <4> YL Huang Spring‘14 © NCTU
2 Essential Development Tools ° Host System offers: • Cross compiler • Linker • Source-level debugger ° Target Embedded System offers: • Linker loader • Monitor • Debug agent ° Connections between host and target system: • Serial Interface • ICE: JTAG (Xmit debug info b/w host debugger & target debug agent) ° Programs including: • System software • Real-time operating system (RTOS): Kernel • Application code ° Steps: • Compiled programs into object code • Linked together into an executable image UEE 3303 <5> YL Huang Spring‘14 © NCTU Development ° Native development: • Writing applications that execute in the same env as used for development • Do not need to be concerned with - How an executable image is loaded into memory and - How execution control is transferred to the application ° Cross-platform development: • Need to understand the target system fully: - How to store the program image on the target system - How and where to load the image during runtime - How to develop and debug the system iteratively - .. • These aspects impact how the code is developed, compiled and linked. UEE 3303 <6> YL Huang Spring‘14 © NCTU Product design process UEE 3303 <7> YL Huang Spring‘14 © NCTU IDE (Integrated Development Environment) ° Integrated • Editor • Compiler • Linker • Debugger… ° IAR ° CodeWarrior UEE 3303 <8> YL Huang Spring‘14 © NCTU
3 IAR UEE 3303 <9> YL Huang Spring‘14 © NCTU IAR Product offering ° IAR Embedded Workbench • Generic development platform, supports more than 35 different 8, 16 and 32 bit architectures • Includes C/Embedded C++ optimizing compiler, assembler, linker, librarian, editor, project manager and C-SPY debuggers IAR visualSTATE • Graphical design tool for embedded applications based on state machine models • Designing, testing and implementation real-time applications based on superior technology • Automatically generates consistent code for embedded systems IAR MakeApp • Device driver wizard. Master the complexity of an modern microcontroller more quicker and easier than ever before IAR’s products for Bluetooth • IAR Embedded Stack for Bluetooth, » Compact and easy configurable • PreQual • Starter kit UEE 3303 <10> YL Huang Spring‘14 © NCTU Complete suite of tools from IAR visualSTATE Design Embedded Workbench Verify, Validate, Implement IAR J-Link & IAR J-Trace IAR Development Kits Compile Debug Deploy Target applicati on Idea IAR RTOS & Middleware IAR PowerPac UEE 3303 <11> YL Huang Spring‘14 © NCTU Model State Chart / UML State Machine Modeling Tool User-Written Codes Middleware TCP/IP Stack USB Stack GUI RTOS Kernel BSP File System Compiler / Assembler Linker Debugger Code IDE Auto- Generated Code Project Manager Target System ARM SoC On-Chip Peripherals On-Chip Flash On-Chip RAM ARM Core Embedded ICE ETM Trace Port JTAG Port Emulator Trace Probe JTAG Probe UEE 3303 12 YL Huang Spring‘14 © NCTU
4 ePBB Development UEE 3303 13 YL Huang Spring‘14 © NCTU IAR Workspace ° Manage multiple projects for a product • by right-clicking on the project and choosing ‘Set as Active’ to select the project V V V V V The workspace contains 5 projects: adc, alarm, lcd, pit, rtc UEE 3303 14 YL Huang Spring‘14 © NCTU IAR Project ° Manage multiple files/libraries for a project ° One example is creating a group to hold source files that is common between projects, and you only want one unique copy of these files. UEE 3303 15 YL Huang Spring‘14 © NCTU Create Project ° 1. Open IAR. Inside the startup window click the first button: “Create new project in current workspace.” UEE 3303 16 YL Huang Spring‘14 © NCTU
5 ° 2. Select the “Empty project” Template, then click OK. UEE 3303 17 YL Huang Spring‘14 © NCTU ° 3. name your project and specify the desired directory. Click “OK.” Then your project should appear in the upper left-hand side of the screen. Right-click on it then choose “Options.” UEE 3303 18 YL Huang Spring‘14 © NCTU ° 4. Inside the options: choose the appropriate XXXXX device (STM32F207VG in this case). • If you want to be programming in ASM, also check the “Assembler -only project” box in the lower-right hand side of the screen. • If you are programming in C, please leave this box unchecked. UEE 3303 19 YL Huang Spring‘14 © NCTU ° 5. For C project please verify that the “Library Configurations” tab has “CLIB” chosen for the library. For assembly projects this option should be selected as “none.” UEE 3303 20 YL Huang Spring‘14 © NCTU
6 ° 6. Next select the “Debugger” category on the left-side of the screen. • Choose “YYYY Debugger” under the “Driver” (J-Link in this case). • For C projects please make sure “Run to main” is checked. UEE 3303 21 YL Huang Spring‘14 © NCTU ° 7. Under the “YYYY Debugger” category, make sure the appropriate hardware programmer is selected under “Connection” and the appropriate JTAG protocol is selected under “Debug protocol.” • Click OK. These should be the only changes necessary to build a simple code and load it onto your target XXXXX. • NOTE: The Spy-Bi-Wire mode is not supported by the Parallel Programmer (e.g. MSP-FET430PIF), when LPTx is selected. UEE 3303 22 YL Huang Spring‘14 © NCTU ° 8. Now we are ready to load our code file onto your XXXXX. To do this, right-click on your project and go to Add - Add files. Browse to your code file with a “.c” C -file or “.s” assembly file. UEE 3303 23 YL Huang Spring‘14 © NCTU ° 9. Now your code should be added to your project. If you double-click on the newly added code file the text should appear in the main window. UEE 3303 24 YL Huang Spring‘14 © NCTU
7 Configuration of a Project ° By default when creating a new project, you automatically get two configurations: Release and Debug UEE 3303 25 YL Huang Spring‘14 © NCTU CODE WARRIOR UEE 3303 26 YL Huang Spring‘14 © NCTU
                                                                                                                                                                                                                                                               
                                                                                                                                                                                                                             
                                                                                                                                                                                                                                         
                                                                                                                                                                                                                                                                                                            
                                                                                                                                                                                                                                                                                                                                 
                                                                                                                                                                                                                                                                                                                         
                                                                                                                                                                                           
1 UEE3303 Introduction to Embedded Systems Lecture 7 uCOS/II YuLun Huang http://rtes.cn.nctu.edu.tw UEE 3303 1 YL Huang Spring‘14 © NCTU A computer is… ° Computer = App + OS + Hardware UEE 3303 2 YL Huang Spring‘14 © NCTU RTOS Overview UEE 3303 3 YL Huang Spring‘14 © NCTU Real Time OS ° Real-time OS (RTOS) is an intermediate layer between hardware devices and software programming ° “Real-time” means keeping deadlines, not speed ° Advantages of RTOS in SoC design • Shorter development time • Less porting efforts • Better reusability ° Disadvantages • More system resources needed • Future development confined to the chosen RTOS UEE 3303 4 YL Huang Spring‘14 © NCTU
2 μC/OS-II ° Written by Jean J. Labrosse in ANSI C ° A portable, ROMable, scalable, preemptive, real -time, multitasking kernel ° Used in hundreds of products since its introduction in 1992 ° Certified by the FAA for use in commercial aircraft ° Available in ARM Firmware Suite (AFS) ° Over 90 ports for free download ° http://www.ucos-ii.com UEE 3303 5 YL Huang Spring‘14 © NCTU μC/OS-II Features ! Portable 8-bit ~ 64 bit ! ROMable small memory footprint ! Scalable select features at compile time ! Multitasking preemptive scheduling, up to 64 tasks UEE 3303 6 YL Huang Spring‘14 © NCTU μC/OS-II vs. μHAL ° uHAL is shipped in ARM Firmware Suite ° uHAL is a basic library that enables simple application to run on a variety of ARM-based development systems ° uC/OS-II use uHAL to access ARM-based hardware uC/OS-II User application AFS Utilities C, C++ libraries uHAL routines Development board AFS support routines UEE 3303 7 YL Huang Spring‘14 © NCTU Kernel ! Basic jobs of uC/OS-II kernel • Task management • Interrupt handling • Inter-process communication UEE 3303 8 YL Huang Spring‘14 © NCTU
3 Kernel API ° Service routines provided by uC/OS-II Kernel • Task management APIs • Time management APIs • Memory management APIs • Inter-process communication APIs • Synchronization APIs ° To make a System Call means to call Kernel API UEE 3303 9 YL Huang Spring‘14 © NCTU Task ! Task is an instance of program ! Task thinks that it has the CPU all to itself ! Task is assigned a unique priority ! Task has its own set of stack ! Task has its own set of CPU registers (backup in its stack) ! Task is the basic unit for scheduling ! Task status are stored in Task Control Block (TCB) UEE 3303 10 YL Huang Spring‘14 © NCTU Task Structure Task structure: ! An infinite loop ! An self-delete function Task with infinite loop structure void ExampleTask(void *pdata) { for(;;) { /* User Code */ /* System Call */ /* User Code */ } } Task that delete itself void ExampleTask(void *pdata) { /* User Code */ OSTaskDel(PRIO_SELF); } UEE 3303 11 YL Huang Spring‘14 © NCTU Task States Waiting Task Delete Task Create Task Gets Event Task Pending Events Highest Priority Task Interrupt Dormant Ready Running ISR Task Delete Task is Preempted Task Delete Int. Exit UEE 3303 12 YL Huang Spring‘14 © NCTU
4 Task Priority ! Unique priority (also used as task identifiers) ! 64 priorities max (8 reserved) ! Always run the highest priority task that is READY ! Allow dynamically change priority UEE 3303 13 YL Huang Spring‘14 © NCTU Task Control Block uC/OS-II use TCB to keep record of each task States Stack Pointer Priority Misc … Link Pointer UEE 3303 14 YL Huang Spring‘14 © NCTU Task Control Block(cont.) UEE 3303 15 YL Huang Spring‘14 © NCTU Exchanging CPU Control Control returns from task to OS when Kernel API is called void ExampleTask(void *pdata) { for(;;) { /* User Code */ /*System Call */ /* User Code */ } } uC/OS-II Kernel API OSMboxPend(); OSQPend(); OSSemPend(); OSTaskSuspend(); OSTimeDly(); OSTimeDlyHMSM(); More… UEE 3303 16 YL Huang Spring‘14 © NCTU
5 Exchanging CPU Control Only one of OS, Task, Interrupt Handler gets CPU control at a time A B B C A Interrupt Handler OS Task Time Scheduling System Call Interrupt Interrupt Exit UEE 3303 17 YL Huang Spring‘14 © NCTU Task Scheduling ° Non-preemptive Time ISR Low-priority Task ISR makes the high-priority task ready High-priority Task low-priority task Relinquishes the CPU UEE 3303 18 YL Huang Spring‘14 © NCTU Task Scheduling ° Preemptive ISR Low-priority Task ISR makes the high-priority task ready high-priority task Relinquishes the CPU uC/OS-II adopts preemptive scheduling Time High-priority Task UEE 3303 19 YL Huang Spring‘14 © NCTU Context Switching ! Context Switching • The process of swap in/out the context of tasks when scheduler choose a new task to run. ! Context • Usually means values in registers used by the task. ! Switching Steps 1. Save registers of current task to stack(curr) 2. Load new task’s SP into CPU 3. Restore registers of new task from stack(new) 4. Resume execution of new task UEE 3303 20 YL Huang Spring‘14 © NCTU
6 Context Switching Time ISR Low-priority Task Context Switching High-priority Task ISR makes the high-priority task ready Context Switching high-priority task Relinquishes the CPU UEE 3303 21 YL Huang Spring‘14 © NCTU Critical Region ° Code need to be treated indivisibly ! Code have to be executed without interrupt creating task…etc ! Non-reentrant code accessing shared variable…etc UEE 3303 22 YL Huang Spring‘14 © NCTU Critical Region ! Protecting critical region • OS_ENTER_CRITICAL( ) temporarily disable interrupt • OS_EXIT_CRITICAL( ) re-enable interrupt UEE 3303 23 YL Huang Spring‘14 © NCTU Events ! A way for Synchronization and Communication • Pend (Wait for an event) • Post (Signal an event) ! Events in uC/OS-II • Semaphore • Counting Semaphore • Message Mailbox • Message Queues UEE 3303 24 YL Huang Spring‘14 © NCTU
7 Semaphore ! Semaphore serves as a key to the resource ! A flag represent the status of the resource ! Prevent re-entering Critical Region ! Can extent to counting Semaphore Task 1 Task 2 RS-232 Send data via RS232 Request/Release Semaphore Request/Release Send data via RS232 UEE 3303 25 YL Huang Spring‘14 © NCTU Semaphore Using Semaphore in uC/OS-II ! OSSemCreate() ! OSSemPend() ! OSSemPost() ! OSSemQuery() ! OSSemAccept() UEE 3303 26 YL Huang Spring‘14 © NCTU Message Mailbox ! Used for Inter-Process Communication (IPC) ! A pointer in MailBox points to the transmitted message Task ISR Task Post Mail Box Pend “message” Post UEE 3303 27 YL Huang Spring‘14 © NCTU Message Queues ! Array of MailBox ! FIFO FILO configuration Task ISR Task Post Mail Queues Pend “message” Post UEE 3303 28 YL Huang Spring‘14 © NCTU
8 MailBox Queues Using MailBox in uC/OS-II ! OSMboxCreate() ! OSMboxPend() ! OSMboxPost() ! OSMboxQuery() ! OSMboxAccept() Using Queue in uC/OS-II ! OSQCreate() ! OSQPend() ! OSQPost() ! OSQPostFront() ! OSQQuery() ! OSQAccept() ! OSQFlush() UEE 3303 29 YL Huang Spring‘14 © NCTU Memory Management ! Semi-dynamic memory allocation ! Allocate statically and dispatch dynamically ! Explore memory requirements at design time dispatch dynamically Task 1 Task 2 Task 3 partition into memory blocks allocate statically OS Initializing OS running UEE 3303 30 YL Huang Spring‘14 © NCTU Memory Management Using Memory in uC/OS-II ! OSMemCreate() ! OSMemGet() ! OSSemPut() ! OSSemQuery() UEE 3303 31 YL Huang Spring‘14 © NCTU Interrupt ° Interrupt Controller • A device that accepts up to 22 interrupt sources from other pheripherals and signals ARM processor ° Interrupt Handler • A routine executed whenever an interrupt occurs. It determines the interrupt source and calls corresponding ISR. Usually provided by OS. ° Interrupt Service Routine (ISR) • Service routines specific to each interrupt source. This is usually provided by hardware manufacturer. UEE 3303 32 YL Huang Spring‘14 © NCTU
9 Interrupt ° Peripheral sends interrupt request to interrupt controller ° Interrupt controller sends masked request to ARM ° ARM executes interrupt handler to determine int. source Peripheral A Interrupt Controller Peripheral B ARM Processor bus UEE 3303 33 YL Huang Spring‘14 © NCTU Interrupt ! Default interrupt handler: uHALr_TrapIRQ() 1. Save all registers in APCS-compliant manner 2. Call StartIRQ(), if defined 3. Determine interrupt source, call the corresponding interrupt service routine (ISR) 4. Call FinishIRQ(), if defined 5. Return from interrupt UEE 3303 34 YL Huang Spring‘14 © NCTU Interrupt ! When an interrupt occurs, no further interrupt accepted ! To achieve real-time, the period of interrupt disabled should be as short as possible ! Do only necessary jobs in ISR, leave other jobs in a deferred Task UEE 3303 35 YL Huang Spring‘14 © NCTU Starting μC/OS-II Initialize hardware uC/OS-II ARMTargetInit(), OSInit() Allocate resources OSMemCreate(), OSMboxCreate(), …etc Create at least one task OSTaskCreate() Start Scheduler OSStart() UEE 3303 36 YL Huang Spring‘14 © NCTU
10 Porting Application ° Necessary coding changes ! variables • use local variables for preemption • use semaphore to protect global variables (resources) ! data transfer • arguments = mailbox/queue ! memory allocation • malloc() = OSMemCreate() OSMemGet() UEE 3303 37 YL Huang Spring‘14 © NCTU Porting Application ° assign task priorities ! unique priority level in uC/OS-II • only 56 levels available • priority can be change dynamically ! call OSTimeDly() in infinite loop task • ensure lower priority task get a chance to run MUST: if lower priority task is pending data from higher priority task UEE 3303 38 YL Huang Spring‘14 © NCTU Driver ! What is a Driver • A named entity that support basic I/O of a device • A handler that manages interrupt from a device • A description to a device, registered and managed by OS • An abstraction layer for user application to access device easily UEE 3303 39 YL Huang Spring‘14 © NCTU Driver ° Original configuration of a System – No additional Hardware Application OS HAL Development Board UEE 3303 40 YL Huang Spring‘14 © NCTU
11 Driver ° New configuration of a System – additional Hardware added ° We must add driver into system to provide easy access of new hardware Application OS HAL Driver New Hardware Development Board UEE 3303 41 YL Huang Spring‘14 © NCTU Driver ! High-level API • Interactive with OS • Interface to Application ! Low-level Command • Direct access to hardware (usually written in assembly) ! Data • Private data to driver Application OS HAL API Data Command New Hardware Development Board UEE 3303 42 YL Huang Spring‘14 © NCTU Driver ! Command Layer • A set of functions/macros to manipulate hardware • Interrupt handler • Usually written in Assembly to get optimized speed • Keep essential commands only ! Common essential commands • Read, Write, Init, Enable, Disable UEE 3303 43 YL Huang Spring‘14 © NCTU Driver ! API layer • Interactive with OS to maintain resources • Interactive with OS to acknowledge interrupt and task scheduling • Provides unique interface to application to achieve device abstraction • Encapsulate driver internal data • Combine commands to provide various functionality ! Data • Driver Status • Data Buffer UEE 3303 44 YL Huang Spring‘14 © NCTU
12 Driver ° Why divide driver into two parts • Easy to replace underlying hardware • Unique interface to applications • Easy to adopt pre-written assembly code UEE 3303 45 YL Huang Spring‘14 © NCTU Driver ° API Example Available commands: • Read_Byte • Write_Byte • Init_Device • Enable_Device • Disable_Device Set_serial_baudrate(int baud) { OS_Request_Device(); Disable_Device(); Write_Byte(CONF_BASE, baud); Enable_Device(); OS_Release_Device(); } UEE 3303 46 YL Huang Spring‘14 © NCTU Driver ° API Example Send_serial(char data[], int len) { OS_Request_Device(); for(I=0;Ilen;I++) Write_Byte(IO_BASE, data[I]); OS_Release_Device(); } Available commands: • Read_Byte • Write_Byte • Init_Device • Enable_Device • Disable_Device UEE 3303 47 YL Huang Spring‘14 © NCTU Driver Design Flow start Decide I/O interface (I/O address, I/O method) Write Assembly code to control hardware Pack assembly code into commands Write interrupt handler Write API base on previously Developed commands Test Driver end Test assembly code UEE 3303 48 YL Huang Spring‘14 © NCTU
1 UEE3303 Introduction to Embedded Systems Lecture 8 Freescale YuLun Huang http://rtes.cn.nctu.edu.tw UEE 3303 1 YL Huang Spring‘14 © NCTU KINETIS VS. K60D UEE 3303 2 YL Huang Spring‘14 © NCTU Vybrid Controller Solutions Rich Apps in Real Time. Real-time, highly integrated solutions with best-in-class 2D graphics to enable your system to control, interface, connect, secure and scale. i.MX Application Processors Your Interface to the World. Industry’s most versatile solutions for multimedia and display applications, with multicore scalability and market-leading power, performance integration. Kinetis Microcontrollers Design Potential. Realized Industry’s most scalable ultra-low-power, mixed -signal MCU solutions based on the ARM® Cortex™-M4 and ARM® Cortex™-M0+ architectures. QorIQ Processors built on Layerscape Architecture Accelerating the Network’s IQ Industry’s first software -aware, core-agnostic networking system architecture for the smarter, more capable networks of tomorrow – end to end. Consumer Automotive Industrial Consumer Industrial Consumer Automotive Industrial Networking Industrial Freescale has the industry’s broadest range of solutions built on ARM® technology for automotive, industrial, consumer and networking applications. Find your ideal solution at the price, performance and power level you desire, and leverage the extensive software and tool bundles available to speed and ease your design process. UEE 3303 3 YL Huang Spring‘14 © NCTU Kinetis Series • Kinetis Overview • K Series- 32-bit ARM Cortex M4 • L Series - 32-bit ARM Cortex M0+ • M Series – 32-bit ARM Cotex M0+ for Smart Metering • W Series - 32-bit ARM Cortex M0+ M4 for Wireless (IoT) UEE 3303 4 YL Huang Spring‘14 © NCTU
2 Kinetis Portfolio Performance General Purpose Segment Focused Integration Coming 2013 Kinetis L Series Ultra-low power/cost ARM Cortex-M0+ MCU families from 48MHz / 8KB with mixed-signal, connectivity HMI features in low pin-count packages. Availability NOW! Kinetis K Series Industry-first ARM Cortex-M4 MCU families from 50MHz / 32KB with low power, FlexMemory, mixed-signal and broad connectivity, HMI security features. Availability NOW! Kinetis W Series Integrated wireless connectivity 5V ARM Cortex -M0+ ARM Cortex-M4 MCU families with class-leading sub-1 GHz and 2.4 GHz RF transceivers Kinetis M Series High accuracy metrology ARM Cortex-M0+ MCU families for single chip smart meter implementations. Coming 2013 (samples now) Leading Performance - Low Power - Scalability - Industrial-grade reliability temp Coming 2013 (samples now) Freescale Bundled IDE, RTOS Middleware - Rapid prototyping Platform - Broad ARM Ecosystem Support UEE 3303 5 YL Huang Spring‘14 © NCTU K Series: MCU Family Compatibility + Ethernet, Encryption, Tamper Detect, DRAM Controller I I I I I I I I K20 Family 50-120MHz 32KB-1MB 32-144pin I I I I I K60 Family 100-150MHz 256KB-1MB 100-256pin I I I I I I I I I I I I I I I I I I + Graphics LCD Entry Point + Analog Measurement Engine, I I I I I I I I K30 Family 72-100MHz 64-512KB 64-144pin + USB K10 Family 50-120MHz 32KB-1MB 32-144pin I I I I I I I I I I I I I I I I I I K70 Family 120-150MHz 512KB-1MB 196-256pin I I I I I I I I I I I I I I I I I I + Segment LCD K40 Family 72-100MHz 64-512KB 64-144pin I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I K50 Family 72-100MHz 128-512KB 64-144pin I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I + Segment LCD + USB Ethernet, Encryption UEE 3303 6 YL Huang Spring‘14 © NCTU Kinetis K60 Family Core Arm® Cortex™- M4 100/120/150 MHz Debug Interfaces DSP Interrupt Controller System Memories Clocks Internal and External Watchdogs Memory Protection Unit (MPU) DMA Low–Leakage Wake-Up Unit Program Flash (256 to 1 MB) FlexMemory (256 to 512KB) (4 to 16 KB EE) Serial Programming Interface (EZPort) SRAM (64 to 128 KB) External Bus Interface (FlexBus) Phase-Locked Loop Flequency -Locked Loop Low/High -Frequency Oscillators Internal Reference Clocks Float Point Unit (FPU) NAND Flash Controller Cache DDR Controller Security Analog Timers Communication HM I and Integrity Interfaces Cyclic Redundancy Check (CRC) 16-bit ADC PGA Analog Comparator with 6-bit DAC 12-bit DAC Voltage Reference I2S GPIO Secure Digital Host Controller (SDHC) I2C UART (ISO 7816) SPI CAN Xtrinsic Low -Power Touch –Sensing Interface Random Number Generator Cryptographic Acceleration Unit (CAU) Hardware Tamper Detection Unit FlexTimer Carrier Modulator Transmitter Programmable Delay Block Periodic Interrupt Timers Low-Power Timer Independent Real-Time Clock (RTC) IEEE® 1588 Timer Standard Feature Optional Feature USB On-the -Go (LS/FS) USB On-the -Go (HS) USB Device Charger Detect (DCD) USB Voltage Regulator IEEE 1588 Ethernet MAC UEE 3303 7 YL Huang Spring‘14 © NCTU Kinetis Part Numbering Scheme M K 20 D X 256 (Z) V LQ 10 (R) Qualification status Kinetis Family Core / Key Attribute FlexMemory Flash Size Tape and Reel (TR) Speed/10 Package Identifier Temperature range Reserved for Silicon Revision Number Memory Flash Size Silicon Rev Temperature Package Speed TR Options Description Options Description Options Description Options Description Options Description Options Description Options Description D M4 w/ DSP N Non-FlexMemory 8 8KB Z Initial Revision C -40 to 85C 16TSSOP 4 48MHz Blank Non TR F M4 w/ DSPFPU X Flexmemory 16 16KB 2nd Revision V -40 to 105C 24QFN 5 50MHz R TR 32 32KB A 3rd Revision M -40 to 125C 32CSP 7 72MHz 64 64KB B 4th Revision FM 32QFN 10 100MHz 96 96KB … … FT 48QFN 12 120MHz 128 128KB LF 48LQFP 15 150MHz 256 256KB 18 180MHz 512 512KB MP 64MAPBGA 1M0 1MB LH 64LQFP 1M5 1.5MB LK 80LQFP 2M0 2MB LL 100LQFP 2M5 2.5MB AB 120WLCSP … … MC 121MAPBGA AA 143WLCSP LQ 144LQFP MD 144MAPBGA MJ 256MAPBGA * 196MAPBGA package removed Key Attribute Options Attribute UEE 3303 8 YL Huang Spring‘14 © NCTU
3 Kinetis K/L Series: Packaging 32QFN 5 x 5 mm 0.5mm pitch (K10/20) (KL0/1/2) Common Packages Kinetis K Series Package Kinetis L Series Package 64MAPBGA 5 x 5 mm 0.5mm pitch (K10/20) (KL1*/2*/3*/4*) 48LQFP 7 x 7 mm 0.55mm pitch (K10/20) (KL0/1*/2*) 64LQFP 10 x 10 mm 0.5mm pitch (K10/20/30/40/50) (KL1/2/3/4) 80LQFP 12 x 12 mm 0.5mm pitch (K10/20/30/40/50) (KL1/2/3*/4*) 100LQFP 14 x 14 mm 0.5mm pitch (K10/20/30/40/50/60) (KL3/4) Kinetis L Series Only Kinetis K Series Only 90WLCSP 3.9x4.4x0.56 mm 0.4mm pitch (K10/20*) 144LQFP 20 x 20 mm 0.5mm pitch (K10/20/30/40/50/60) 48QFN 7 x 7 mm 0.5mm pitch (K10/20) (KL0/1*/2*) 110WLCSP 3.9x4.4x0.56 mm 0.4mm pitch (K10/20*) 144MAPBGA 13 x 13 mm 1.0mm pitch 120WLCSP 5.3x5.3x0.56 mm 0.4mm pitch (K10/20/60) (K10/20/30/40/50/60) 121MAPBGA 8 x 8 mm 0.65mm pitch (K10/20/30/40/50/60) (KL2/3/4) 143WLCSP 6.5x5.6x0.56 mm 0.4mm pitch (K61) 256MAPBGA 17 x 17 mm 1.0mm pitch (K60/70) 35WLCSP 2.55x3x0.56 mm 0.4mm pitch (KL1*/2*) 32LQFP 7 x 7 mm 0.8mm pitch (KL0) 25WLCSP 2.3x2.3x0.56 mm 0.4mm pitch (KL0*) 20WLCSP 2x2x0.56 mm 0.4mm pitch (KL0) 24QFN 4 x4x1 mm 0.5mm pitch (KL0x) 16QFN 3x3x1 mm 0.5mm pitch (KL02) UEE 3303 9 YL Huang Spring‘14 © NCTU *proposed (Development Tools) ENABLEMENT OVERVIEW UEE 3303 10 YL Huang Spring‘14 © NCTU Kinetis Tower System: Reusable, modular development platform www.freescale.com/tower www.towergeeks/org MCU Families Supported TWR Part Number Contents Price (SRP) K20 TWR-K20D50M 64 LQFP MCU module. USB communication supported without TWR-SER (recommended for UART) $99 TWR-K20D72M 100 LQFP MCU module. USB communication supported without TWR-SER $119 TWR-K21D50M 81 MAPBGA MCU module. Hardware security features supported. $119 K30/40 TWR-K40X256 TWR-K40D100M TWR-K40X256 Rev 1.0 (144MBGA), TWRPI-SLCD TWR-K40D100M Rev 2.0 Silicon (144MBGA) $69 TWR-K40X256-KIT TWR-K40X256 (144MBGA), TWRPI-SLCD TWR-SER, TWR-ELEV $139 K50 TWR-K53N512 TWR-K53N512 (144MBGA), TWRPI-SLCD $109 TWR-K53N512-KIT TWR-K53N512 (144MBGA), TWRPI-SLCD, TWR-SER, TWR-ELEV $179 K10/20/60 TWR-K60N512 TWR-K60D100M TWR-K60N512 Rev 1.0 Silicon (144MBGA) TWR-K60D100M Rev 2.0 Silicon (144MBGA) TWR-K60N512-KIT TWR-K60N512 (144MBGA), TWR-SER, TWR-ELEV $139 TWR-K60N512-IAR TWR-K60N512-KIT (144MBGA), TWR-PROTO, Segger J-Link Lite Debug Probe, IAR EWARM IDE (eval. version) NEW TWR-K60N512-KEIL TWR-K60N512-KIT (144MBGA), UNLINK-ME Debug Probe, KEIL MDK IDE (eval. version) • IDEs: FSL CodeWarrior, IAR Embedded Workbench, Keil MDK, • Freescale MQX RTOS • OSJTAG Debug circuitry – program debug with USB cable $69 $99 $239 $199 TWR-SENSOR -PAK TWR-LCD TWR-WIFI-RS2101 • Low power touch sensing plug-in socket for expansion: Sensors, Radio, etc… • Fully compatible with all Tower peripheral modules UEE 3303 12 YL Huang Spring‘14 © NCTU UEE 3303 11 YL Huang Spring‘14 © NCTU Kinetis IDE Support Availability 1. Freescale (CodeWarrior 10.1) [available now] - Includes MQX Task Aware Debug plug-in option - MCU v10.4 [available now] 2. IAR (Embedded Workbench) [available now] - EWARM: Supports all ARM7/9 and all Cortex Devices - EWARM-BaseLine (BL): All the features of EWARM but is limited in code space up to 256KB - EWARM-CM: Supports any Cortex-M series devices including (M4) - EWARM-CM-FSL: Supports any Kinetis Cortex-M4 series device – Will be re-sold via FSL Buy Direct program only. $2500 for 1 year license – Includes MQX Task Aware Debug plug-in option – http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=EWARM-CM-FSLfsrch=1sr=2 3. Keil (MDK) [available now] - MQX Task Aware Debug plug-in planned . 4. Greenhills (MULTI) [available now] 5. CodeSourcery (Sourcery G++) [available now] - MQX Task Aware Debug plug-in planned.
4 NanoSSL™/ NanoSSH™ Client for Freescale MQX Security options with significant cost savings ° Secure Shell (SSH) encrypts communications between hosts over an insecure network, and it’s great for logging into and executing commands on networked computers. It’s also useful for tunneling, port-forwarding and secure file transfers using the SFTP protocol. • Super-fast, super-small embedded SSH and SSL clients from Mocana • One-time “unlocking” fee of $199 to access source code with unlimited binary distribution • Available via Buy Direct www.freescale.com/embeddedcomponents ° Secure Sockets Layer/Transport Layer Security (SSL/TLS) - authenticates endpoints and encrypts channels to provide session privacy and security on the Internet. The standard operates at a higher level in the OSI stack than IPsec, and supports peer negotiation for algorithm selection, public key based exchange of secret session keys and X.509 certificates. » Ultra-small at less than one fifth the size of a typical SSL/SSH client. » Minimal impact on device performance » Minimal impact on flash ROM utilization Addition Upgrades: http://mocana.com/mqx/ Royalty-Free for MQX Users! ° Freescale’s super-fast, super-small embedded SSH/SSL client by Mocana • Kinetis NANOSSL, NANOSSH and CAU libraries due end May / start June • “How-to-use CAU Library” App Note is currently in development for Kinetis. Available Now UEE 3303 13 YL Huang Spring‘14 © NCTU PE Micro Universal Multilink (U-MULTILINK) http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=UMultilink Features • Easy-to-use debug and programming interface which allows the PC to communicate with a target processor through the USB port of the PC. • Controls the MCU/MPU by accessing the debug port of the target. • Can communicate with multiple MCUs using multiple headers - flip open the plastic case. Ribbon cables for the supported MCUs are conveniently included. • Supported by recent versions of CodeWarrior, current PE software applications, and Kinetis tool chains from IAR, Keil, and Mentor Graphics. • Draws power directly from the USB port – no external power supply needed • Multi-voltage support for targets ranging from 1.6 to 5.25 Volts • Multilink Universal FX: a high-speed version of the USB Multilink Universal with additional enhancements. Supports: Replaces: • Kinetis N/A • HCS08 USBMULTILINK08 • HC(S)12(X) USBMULTILINKBDM • ColdFire(+) V1 USBMULTILINKBDM • ColdFire V2-4 USBMLCF • Qorivva USBMLPPCNEXUS Freescale U-MULTILINK $119 PE USB-ML-UNIVERSAL $119 UEE 3303 14 YL Huang Spring‘14 © NCTU KINETIS KL25 UEE 3303 15 YL Huang Spring‘14 © NCTU Kinetis L Series: Enabling Differentiation in Entry-Level Products 32-bit 8-bit Energy-efficiency Class-leading Coremark/mW Scalability Integration Kinetis L to K Series (Cortex M0+ to M4) Enablement Freescale bundle + ARM ecosystem Ultra Low Static 1uA Low cost From $0.50 Ease-of-use Freedom Platform, Processor Expert MCU Solution Advisor Kinetis L Series The evolution of the entry-level MCU UEE 3303 16 YL Huang Spring‘14 © NCTU
5 ARM Cortex-M0+ Processor Fetch Decode Execute Fetch De code Exe Shorter Pipeline optimized for energy efficiency From Cortex-M3 Re-locatable Vector Table Memory Protection Unit (MPU) New Fast I/O Port Micro Trace Buffer (MTB) More Options Full ARMv6-M compatible UEE 3303 17 YL Huang Spring‘14 © NCTU ARM Cortex-M0+ Processor Energy-Efficiency • 2-stage pipeline – reduced cycles per instruction (CPI) enabling faster branch instruction and ISR entry • Program memory access on alternate cycles Single-Cycle I/O Port • 50% higher GPIO toggling frequency than standard I/O • Improves reaction time to external events allowing bit -banding and software protocol emulation • Save precious cycles, e.g. set faster peripherals for low-power access • Access GPIO/peripherals while processor fetches the next instruction Processing • Only 56 Instructions, mostly coded on 16-bit. Option for fast MUL 32x32 bit in 1 cycle • Cortex-M0/3/4 compatible • 1.77CM/MHz • Best-in-class code density vs. 8/16-bit architectures – reduced cost, power consumption and pin-count Micro Trace Buffer • Powerful, lightweight trace solution enabling fast debug • Non-intrusive – trace information stored in small area of MCU SRAM (size defined by programmer) • Trace read over Serial Wire /JTAG (CPU stopped) UEE 3303 18 YL Huang Spring‘14 © NCTU ARM Cortex-M0+ powering Kinetis L Series 90nm TFS Memory Bit Mani-pulation Engine RGPIO eDMA Crossbar Integration Flash Memory Controller Micro Trace Buffer sLCD USB Smart Evolution Instead of Revolution ⇒ Reduce # of Cycles ⇒ Reduce Overall Power Consumption ⇒ Comprehensive Compatibility ⇒ Improved Performance ⇒ Autonomous Precise Low Power Peripherals UEE 3303 19 YL Huang Spring‘14 © NCTU Kinetis L Series: Reduce cycles with parallelization and acceleration schemes ! Support concurrent access from DMA/Core to memory and peripherals – offload CPU ! Kinetis L-Series devices support DMA operation in low power modes Rapid GPIOs Master Slave Bit Manipulation Engine ARM® Cortex™-M0+ Direct Memory Access Flash Memory Controller Any operation involving a DMA channel follows the same three steps: 1. Channel initialization 2. Data transfer 3. Channel termination The FMC supports 8-bit, 16-bit, and 32-bit read operations from the program flash memory. In addition, the FMC provides two separate mechanisms for accelerating the interface between bus masters and program flash memory. A 32-bit speculation buffer can prefetch the next 32-bit flash memory location, and a 4-way, 4-set program flash memory cache. UEE 3303 20 YL Huang Spring‘14 © NCTU
6 Moving from 8/16-bit to 32-bit ARM Cortex-M0+ Benefits • Linear 4GB address space • Full-featured interrupt controller • Huge scalability • Huge ARM ecosystem • Micro Trace Buffer • 12-35kgates (similar to 8/16bit) • Excellent code density • 2x to 40x more than 8/16- bit, 9% more than Cortex- M0 • Fast 32-bit math processing • Fast single-cycle access to I/O • 2x CoreMark/mA than closest 8/16-bit MCU, +30% / CM0 Performance Ease-of- Development Energy- Low Cost Efficiency UEE 3303 21 YL Huang Spring‘14 © NCTU K L M W E X Kinetis L Series: Reduce cycles for optimized power efficiency ! Supported operations • Decorated Stores • Logical AND, OR, XOR • Bit field insert (BFI) ! Supported operations • Load-and-Clear 1 bit (LAC1) • Load-and-Set 1 bit (LAS1) • Unsigned Bit Field Extract (UBFX) Task Normal C Code Size BME Code Size Improvement Logical XOR operation 12Bytes 6Bytes 50% Bit Field Insert 24Bytes 6Bytes 75% GPIOA_PDOR ^= 0x02; // Logical XOR 0000005E 0x.... LDR R0,? ?DataTable6_5 ;; 0x400ff000 00000060 0x6800 LDR R0,[R0, #+0] 00000062 0x2102 MOVS R1,#+2 00000064 0x4041 EORS R1,R1,R0 00000066 0x.... LDR R0,? ?DataTable6_5 ;; 0x400ff000 00000068 0x6001 STR R1,[R0, #+0] Uses 12 Bytes // Macro used to generate hardcoded XOR address #define BME_XOR_ADDR(ADDR) (*(volatile uint32_t * )(((uint32_t)ADDR) | (326))) BME_XOR_ADDR(GPIOA_PDOR) = 0x02; 00000014 0x.... LDR R0,??DataTable6_6 ;; 0x4c0ff000 00000016 0x2102 MOVS R1,#+2 00000018 0x6001 STR R1,[R0, #+0] Uses 6 Bytes UEE 3303 22 YL Huang Spring‘14 © NCTU ARM Cortex-M0+ Processor: Fast I/O Port ARM Cortex-M0+ Fast IO Port ! Single access Processor ! Most suited to critical GPIO and Peripherals Advantages for the application ! Higher GPIO toggling frequency ! Bit-bang the I/O as on a 8-bit ! Save precious cycles, e.g. set faster peripherals for low -power ! “Harvard-like”: access GPIO /Peripheral while processor fetch the next instruction UEE 3303 23 YL Huang Spring‘14 © NCTU ARM Cortex-M0+ Processor: A faster route to a bug free application ARM Micro Trace Buffer (MTB) ! Lightweight Trace ! Trace stored in RAM ! Non intrusive ! Read over Serial Wire /JTAG Freescale extensions: ! Additional address (and optionally data) watch points ! Define specific memory references were the trace start and stop AHB MTB Controller RAM I/F store trace information SRAM Appl.Data + Trace Data read trace information UEE 3303 24 YL Huang Spring‘14 © NCTU
7 Kinetis L Series Energy Efficiency • ARM Cortex-M0+ Processor • 90nm low-power flash technology • Bit Manipulation Engine • 50uA/MHz, 3.8CM/mW • Peripheral Bridge Crossbar • Zero Wait State Flash Memory Controller Ultra-efficient processing • 90nm low-leakage flash technology • Multiple RUN, WAIT and STOP modes • 4us wake-up from deep sleep modes • Clock power gating, low-power boot options • 2uA Deep Sleep Idd with register retention, LVD active and 4.3us wake-up Ultra low-power modes • Smart peripherals function in deep sleep modes and can make intelligent decisions and process data without waking up the core – ADMA, UART, Timers, ADC, Segment LCD, Touch Sensing... Energy-saving peripherals Most Innovative Process Technology Kinetis ARM® Cortex-M4 MCUs UEE 3303 25 YL Huang Spring‘14 © NCTU Kinetis L Series vs. Kinetis K Series Category Kinetis L Series Kinetis K Series Core, Performance ARM Cortex-M0+ (48MHz) ARM Cortex-M4 (50-150MHz) Flash 8-256KB 32KB-1MB Features Mixed-Signal, USB, Seg. LCD FlexMemory, Mixed-Signal, USB, Seg. LCD, CAN, Ethernet, Gra. LCD, DRAM, Crypto, Tamper Detect, DRAM Pin-count 16-121pin 32-256pin Low Power ~40uA/MHz (VLPR) ~200uA/MHz (VLPR) Price From $0.49 (MKL02, 8KB, 16QFN) From $0.99 (MK10, 32KB, 32QFN) Target Applications 816-bit replacement Low/mid/high –end 32-bit UEE 3303 26 YL Huang Spring‘14 © NCTU + Ethernet, Encryption, Tamper Detect, DRAM Controller I I I I I I I I K20 Family 50-120MHz 32KB-1MB 32-144pin I I I I I K60 Family 100-150MHz 256KB-1MB 100-256pin I I I I I I I I I I I I I I I I I I KL2x Family I I I I I I I I I I 48MHz I I I I I I I I 32KB-256KB 32-121pin I I I I I I I I I I I I I I I I K30 Family 72-100MHz 64-512KB 64-144pin + USB K10 Family 50-120MHz 32KB-1MB 32-144pin I I I I I I I I I I I I I I I I I I K70 Family 120-150MHz 512KB-1MB 196-256pin I I I I I I I I I I I I I I I I I I + Segment LCD K40 Family 72-100MHz 64-512KB 64-144pin I I I I I KL4x Family I I I I I I I I I I I I I I I I I I KL3x Family ARM Cortex-M4 KL1x Family I I I I I I I I I I I I I I I 48MHz 64-256KB 64-121pin I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I 48MHz I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I + Graphics LCD K50 Family 72-100MHz 128-512KB 64-144pin I I I I I I I I I I I I I I I I I I I I I I I 48MHz 128-256KB 64-121pin I I I I I I I I I I I I I I I I I I I I I I I I I I I I I 32KB-256KB 32-80pin I I I I I I I I + Segment LCD I I I I I I I I + USB + Analog Measurement Engine, Ethernet, Encryption I I I I I I I I Entry Point 8-bit MCU Compatible ARM Cortex-M0+ I I I I I I I I KL0x Family I I I I I I I I I I 48MHz 8KB-32KB 24-48pin I I I I I I I I UEE 3303 27 YL Huang Spring‘14 © NCTU System ARM Cortex-M0+ Core Ultra-low power 48MHz bus freq. Flash 32-256K RAM 4-32K Analog Interfaces KL24/5/6 Family Block Diagram Clock Management LPO (1KH z) FLL Crystal Oscillator (low high range) PLL Peripheral Bus Energy Management Voltage Regulator Power On Reset Low Voltage Detector Unique ID COP RST DMA 4-ch Timers PIT 2ch, 32bit SRTC Debug (SWD) 16b LPTPM 6ch x1, 2ch x 2 Temp. Compensated LS Osc (32KHz) ULP Osc (4MHz) Connectivity Connectivity I/O Ports LPU ART x1 SPI x 2 USB FS/LS Transceiver USB Controller UAR Tx2 IIS x1 LPTMR Inpu t I2C x 2 ADC (SAR w/ DMA) 12/16-bit, up to 16ch 12-bit DAC HSCMP Up to 80 GPIO (4 High Dive) w/ 25 interrupt TSI x 16ch RST/ Operation in: Run Wait VLL S1 VLL S0 Stop/ VLPS VLL S3 V Regulator Packages: 32QFN, 48QFN, 64LQFP, 80LQFP, 100LQFP, 121MBGA UEE 3303 28 YL Huang Spring‘14 © NCTU
8 Freescale EcoMAPS: Kinetis SW Dev Tools Customer Application HW and SW Engineering Services Application Specific • Freescale Motor Control Libs • Freescale Medical USB Stacks • Mocana Middleware • Freescale eGUI • Freescale TSS • Freescale PEG (Swell) • Arcturus Networks • ARM CMSIS Libs • IXAAT • Stonestreet one • CMX Systems • HCC Embedded • Quadros Systems • MapuSoft • Motomic Software • SEGGER Operating Systems • Freescale MQX™ • CMX Systems • Emcraft Systems • Embedded Access • ExpressLogic • FreeRTOS • Green Hills Software • Keil (ARM) • Micrium • Quadros Systems • SEGGER Processor/MCU/DSP Common Occasional IDH ODM SBC/SOM SSI • Novtech • Embedded Access MQX • App Notes • Demos Ref Designs More Standard More Custom • Freescale CodeWarrior • Freescale Freemaster • Atollic • Green Hills Software • Hitex • IAR Systems • Keil (ARM) • Rowley Associates HW Dev Tools • Freescale Tower System • Freescale KWIKSTIK • Green Hills Software • Hitex • IAR Systems • iSYSTEM • Keil (ARM) • Lauterbach • PE Micro Systems • SEGGER • Kinetis SBC: Single Board Computers IDH: Independent Design House BDM: Background Debug Module SOM: System on Modules ODM: Original Design Manufacturer Training Training Partners • Embedded Access MQX • AC6 • Hilf GmbH SSI: Software and Solution Integrators IDE: Integrated Development Environment JTAG: Joint Test Action Group UEE 3303 29 YL Huang Spring‘14 © NCTU Kinetis L Series: Entry-level Enablement Hardware IDE Code Generation Run-Time Software Freescale Freedom Platform FRDM-KL25Z New New www.freescale.com/FRDM-KL25Z ° Low -cost/power platform for entry-level developers ($12.95 / €10 SRP) ° Integrates a fully featured debugger, that works with all featured tool chains. Freescale Tower System TWR-KL25Z48M www.freescale.com/TWR-KL25Z48M ° Modular, open-source development platform with reusable peripheral modules offering connectivity, analog, graphics LCD and motor control functionality Product Selector Freescale MQX Lite RTOS www.freescale.com/mqx • Free, light-weight MQX kernel customised for small resource MCUs • Packaged as a Processor Expert component • Upwards compatible with MQX RTOS Solution Advisor www.freescale.com/sa • Web-based interactive MCU selector • Filters for operating characteristics, packaging, memory configuration peripherals. Verifies muxing compatibility • Save, download and print summary reports and pin muxing configurations Freescale 3rd party IDEs • Freescale CodeWarrior v10.3: free 64KB • Keil MDK: free 32KB • IAR EWARM: free 32KB • Atollic TrueStudio: free 8KB • GCC ARM Embedded via Launchpad.net • Additional tool support from Code Red and others in Q412 Freescale Processor Expert Code Generator • Free software generation tool for device drivers / start-up code • 7 steps from project creation to debug – dramatically reduces development time • Available within CodeWarrior or as a standalone plug-in for IAR/Keil/GNU IDEs GNU UEE 3303 30 YL Huang Spring‘14 © NCTU Kinetis L Series: Freedom Platform www.freescale.com/FRDM-KL25Z FRDM-KL25Z Features: ! MKL25Z128VLK4 MCU – 48MHz, 128KB Flash, 16KB SRAM, USB OTG (FS), 80LQFP ! Capacitive touch “slider”, MMA8451Q accelerometer, Tri-color LED ! Flexible power supply options – USB, coin cell battery, external source ! Easy access to MCU I/O ! Battery-ready, power-measurement access points ! Form factor compatible with Arduino platform ! New, sophisticated OpenSDA debug interface ! Mass storage device flash programming interface (default) – no tool installation required to evaluate demo apps ! PE Multilink interface provides run-control debugging and compatibility with IDE tools ! Open-source Data Logging application provides an example for customer, partner and enthusiast development on the OpenSDA circuit Packed with software: ! Processor Expert: stand-alone or IDE integrated ! MQX Lite RTOS (via Processor Expert) ! Ecosystem partner support: IAR, Keil, Atollic, Rowley, Free GNU command-line tools with GDB server FRDM-KL05Z ! MKL05Z32VFM4 MCU – 48MHz, 32KB Flash, 32QFN ! Available now GNU Available now $12.95 / €10 UEE 3303 31 YL Huang Spring‘14 © NCTU Kinetis L Series: Tower System www.freescale.com/TWR-KL25Z48M TWR-KL25Z48M Features ! MKL25Z128VLK4 MCU – 48MHz, 128KB Flash, 16KB SRAM, USB OTG (FS) ! New, sophisticated OpenSDA debug interface ! Mass storage device flash programming interface (default) – no tool installation required to evaluate demo apps ! PE Multilink interface provides run-control debugging and compatibility with IDE tools ! Open-source Data Logging application provides an example for customer, partner and enthusiast development on the OpenSDA circuit ! 4 user LEDs, 2 capacitive touch buttons ! Freescale MMA8451QR1 accelerometer ! Flexible power supply options ! USB connector, elevators, 3.3v or 1.8v ! Current input measurement jumper ! Compatible with most TWR peripheral board Packed with software: ! Processor Expert: stand-alone or IDE integrated ! MQX Lite RTOS (via Processor Expert) ! Ecosystem partner support: IAR, Keil, Atollic, Rowley, Free GNU command-line tools with GDB server ! TWR-ELEV TWR peripheral modules should be ordered separately if required. No –KIT version planned GNU Available now $99.00 UEE 3303 32 YL Huang Spring‘14 © NCTU
9 Kinetis L Series: SOFTWARE Development Platforms Tool Free Version Limits CodeWarrior 10.4 64KB code size No MQX TAD IAR EWARM 30-day free trial KickStart: 16KB Option to pre-build libraries that don’t count Keil uVision 30-day free trial MDK-Lite: 32KB Atollic TrueSTUDIO 30-day free trial 8KB code size UEE 3303 33 YL Huang Spring‘14 © NCTU Kinetis L Series Enablement: CodeWarrior for MCUs v10.4 ° Freescale's CodeWarrior for MCU's v10.4 integrates the development tools for the ColdFire, ColdFire+, DSC, Kinetis, Qorivva, RS08, S08 and S12Z architectures into a single product based on the Eclipse open development platform ° Special Edition – Free. The following limitations apply – - unlimited assembly code - up to 32KB of C code for HC(S)08/RS08 derivatives - up to 64KB of C code for V1 ColdFire/ColdFire+ Kinetis L derivatives - up to 128KB of C code for V2-V4 ColdFire and Kinetis K derivatives ° Adding GCC compiler for ARM Cortex-M Series (M0+, M4) - FSL will provide support for the gcc compiler integrated with CodeWarrior - No support will be provided for non-integrated gcc compilers - Continuing to provide FSL ARM compiler (M4 only) An application note will be provided to help customers migrate existing FSL ARM ompiler based projects to ARM gcc compiler. Free Compiler up to 64KB! UEE 3303 34 YL Huang Spring‘14 © NCTU Processor Expert: Key Components Project Panel Tree Components Library Component Inspector Target CPU View Problems View UEE 3303 35 YL Huang Spring‘14 © NCTU Processor Expert: Software Design in just 7 Steps www.processorexpert.com Create Project Configure Components • Use Inspector to set all component settings 5 Generate Code • Processor Expert generates components Software Development Timeline 3 2 4 Add Components • Add components to the project from Components Library Verify Settings • Verify no design-time errors in the project 1 7 Build Debug • Build the application • Debug the application Write Application Code • Write application code using code generated for components 6 UEE 3303 36 YL Huang Spring‘14 © NCTU
10 Processor Expert: On-line Training CodeWarrior version Microcontroller Driver Suite UEE 3303 37 YL Huang Spring‘14 © NCTU New Freescale MQX Lite RTOS: Overview www.freescale.com/mqx ° Very light MQX kernel for resource-limited • Targeted at the Kinetis L family initially • Packaged as a Processor Expert ° I/O capability provided by Processor • USB via FSL bare-metal stack, also a • No POSIX-like drivers or file access ° Programming model allows upward code • A true subset of the full MQX RTOS • Code built with MQX Lite will move to full • Same task templates, same API – some ° Available as a component within the following Freescale s/ware offerings: • Processor Expert software, MCU driver suite – Supports IAR, Keil, and GCC compilers / build chains • CodeWarrior Development Studio V10.3 GNU Tools Processor Expert: Introduction (Driver Suite) Processor Expert: Working with Components (Driver Suite) Processor Expert: The Code Model (Driver Suite) Processor Expert: Creating an MQX Lite Project (Driver Suite) Processor Expert: An MQX Lite Example (Driver Suite) Processor Expert: Exporting and Importing Templates (Driver Suite) Processor Expert: Integrating with IAR Embedded Processor Expert: Integrating with Keil Microvision Processor Expert: Introduction (CodeWarrior) Processor Expert: Working with Components (CodeWarrior) Processor Expert: The Code Model (CodeWarrior) Processor Expert: Creating an MQX Lite Project (CodeWarrior) Processor Expert: An MQX Lite Example (CodeWarrior) Processor Expert: Exporting and Importing Templates (CodeWarrior) (Standalone / 3rd party version) View in slideshow mode to enable hyperlinks MCUs component Expert Processor Expert component migration MQX RTOS easily very minor differences Attribute MQX RTOS MQX Lite RTOS Delivery Mechanism Traditional installer with full source for Kernel, services and BSPs Processor Expert (PEx) Kernel and services component, configurable software generated by PEx I/O Drivers MQX POSIX compatible drivers with option for using PEx drivers PEx drivers only Configurability User selects needed services from full or lightweight versions Reduced services available; lightweight options only UEE 3303 38 YL Huang Spring‘14 © NCTU New Freescale MQX Lite RTOS: Benefits www.freescale.com/mqx Easy to configure Packaged as a Processor Expert component; with configurable options: set name of task function, priority, stack size (all the same parameters as an MQX task) Easy to add existing application Just drop in the MQX Lite RTOS component, and get started in minutes Very light-weight Minimal app (Hello task, idle task, interrupt stack) – less than 4 KB RAM; optimized for resource-limited MCUs like Kinetis L Series family I/O capability provided by Processor Expert software Take advantage of the broad spectrum of MCU logical device drivers; with access to libraries/stacks like USB Processor Expert component Real-time, priority-based pre-emptive task switching Threads execute in order of priority, allowing high-priority threads to meet their deadlines consistently, no matter how many other threads are competing for CPU time Programming model allows upward code migration MQX Lite RTOS is a true subset of the full MQX RTOS: code built with MQX Lite RTOS will easily move to the full MQX RTOS MQX Lite with CodeWarrior Processor Expert Processor Expert: Creating an MQX Lite Project (CodeWarrior) MQX Lite with Microcontroller Driver Suite Processor Expert Processor Expert: Creating an MQX Lite Project (Driver Suite) Processor Expert: An MQX Lite Example (CodeWarrior) Processor Expert: An MQX Lite Example (Driver Suite) UEE 3303 39 YL Huang Spring‘14 © NCTU
1 UEE3303 Introduction to Embedded Systems Lecture 9 MQX YuLun Huang http://rtes.cn.nctu.edu.tw UEE 3303 1 YL Huang Spring‘14 © NCTU Objectives ° This session describes basic RTOS concepts using the MQX RTOS ° It will cover tasks, scheduling, semaphores and more with hands-on examples ° You’ll learn how to use a RTOS and the advantages that using one provides UEE 3303 2 YL Huang Spring‘14 © NCTU Module Agenda ° What is an RTOS ° MQX Basics: Tasks • Hands-on ° MQX Basics: Scheduling • Hands-on ° MQX Basics: Task Synchronization • Semaphores • Hands-on ° Additional Resources ° Review UEE 3303 3 YL Huang Spring‘14 © NCTU Module Agenda ° Recall: What is an RTOS? ° MQX Basics: Tasks • Hands-on ° MQX Basics: Scheduling • Hands-on ° MQX Basics: Task Synchronization • Semaphores • Hands-on ° Additional Resources ° Review UEE 3303 4 YL Huang Spring‘14 © NCTU
2 Topic I: Operating Systems User Application Operating System HARDWARE ° The term “operating system” can be used to describe the collection of software that manages a system’s hardware resources ° This software might include a file system module, a GUI and other components ° Often times, a “kernel” is understood to be a subset of such a collection ° Characteristics ! Resource management ! Interface between application and hardware ! Library of functions for the application UEE 3303 5 YL Huang Spring‘14 © NCTU Embedded Operating Systems ► Fusion of the application and the OS to one unit User Operating System + Application HARDWARE ► Characteristics ! Resource management Primary internal resources ! Less overhead ! Code of the OS and the application mostly reside in ROM UEE 3303 6 YL Huang Spring‘14 © NCTU Real Time Operating Systems ° A real-time operating system (RTOS) manages the time of a microprocessor or microcontroller ° Features of an RTOS: ! Allows multi-tasking ! Scheduling of the tasks with priorities ! Synchronization of the resource access ! Inter-task communication ! Time predictable ! Interrupt handling UEE 3303 7 YL Huang Spring‘14 © NCTU Why use an RTOS? ° Plan to use drivers that are available with an RTOS ° Would like to spend your time developing application code and not creating or maintaining a scheduling system ° Multi-thread support with synchronization ° Portability of application code to other CPUs ° Resource handling ° Add new features without affecting higher priority functions ° Support for upper layer protocols such as: ! TCP/IP, USB, Flash Systems, Web Servers, ! CAN protocols, Embedded GUI, SSL, SNMP UEE 3303 8 YL Huang Spring‘14 © NCTU
3 Freescale MQX ° We will be using Freescale MQX to demonstrate these RTOS concepts ° Freescale MQX Software can be downloaded: ! http://www.freescale.com/mqx ° Default Freescale MQX folder: ! C:Program FilesFreescaleFreescale MQX 3.5 UEE 3303 9 YL Huang Spring‘14 © NCTU MQX Directory Structure ° Described in the MQX Release Notes ° Folders are: ! config ! demo ! doc ! lib ! mqx ! tools ! And then the RTCS, USB, and MFS stacks UEE 3303 10 YL Huang Spring‘14 © NCTU MQX Directory Structure (Cont.) ° The “mqx” directory is heart of MQX ° Folders are: ! build ! examples ! source - bsp - io - psp - MQX API source UEE 3303 11 YL Huang Spring‘14 © NCTU Changing Configuration Options ° User configuration options are set in mqx_install/config/board/user_config.h ° Change the default serial port to UART1: #define BSP_DEFAULT_IO_CHANNEL ttyb: #define BSP_DEFAULT_IO_CHANNEL_DEFINED #define BSPCFG_ENABLE_TTYB 1 ° Always need to re-build all the libraries with this new configuration UEE 3303 12 YL Huang Spring‘14 © NCTU
4 Topic II: MQX RTOS Tasks ° A system consists of multiple tasks ° Tasks take turns running ° Only one task is active (has the processor) at any given time ° MQX manages how the tasks share the processor (context switching) ° Task Context • Data structure stored for each task, including registers and a list of owned resources UEE 3303 13 YL Huang Spring‘14 © NCTU Typical Task Coding Structure UEE 3303 14 YL Huang Spring‘14 © NCTU Task States ° A task is in one of these logical states: ! blocked - the task is blocked and therefore not ready - it’s waiting for a condition to be true ! active - the task is ready and is running because it’s the highest -priority ready task ! ready - the task is ready, but it’s not running because it isn’t the highest-priority ready task ! terminated - the task has finished all its work, or was explicitly destroyed UEE 3303 15 YL Huang Spring‘14 © NCTU Active Context Switch Higher-priority Task becomes Ready Time Slice Expires Interrupt comes in Ready Blocking Call Blocked Object Available Timeout Expires Task States Task Finishes Explicit Termination Terminated Task Starts UEE 3303 16 YL Huang Spring‘14 © NCTU
5 Topic III: MQX Scheduling (Priorities) ° Each task is assigned a priority • Higher number means lower priority • 0 is highest priority ° Used by scheduler to determine which task to run next ° User tasks should run at priority 8 or higher. UEE 3303 17 YL Huang Spring‘14 © NCTU Scheduler ° Common Scheduling Configurations: ! FIFO (also called priority-based preemptive) - The active task is the highest-priority task that has been ready the longest ! Round Robin - The active task is the highest-priority task that has been ready the longest without consuming its time slice UEE 3303 18 YL Huang Spring‘14 © NCTU Priority Based FIFO Scheduling high priority low FIFO list of ready tasks Ready CPU Scheduler processor time active UEE 3303 19 YL Huang Spring‘14 © NCTU Priority Based FIFO Scheduling high priority low FIFO list of ready tasks Ready CPU Scheduler processor time active UEE 3303 20 YL Huang Spring‘14 © NCTU
6 Priority Based FIFO Scheduling high priority low FIFO list of ready tasks Ready CPU Scheduler processor time active UEE 3303 21 YL Huang Spring‘14 © NCTU Round-Robin Scheduling 75ms Task 1 Task 2 50ms Same Priority Time Slice = 50ms Task 3 60ms Ready time Task1 Task2 Task3 Task1 Task3 T0 50ms 100ms 150ms 200ms time UEE 3303 22 YL Huang Spring‘14 © NCTU MQX Tasks ° Tasks can be automatically created when MQX Starts; also, any task can create another task by calling _task_create() or _task_create_blocked() ° The function _task_create() puts the child task in the ready state and the scheduler puts the higher priority task to run ° If _task_create_blocked is used the task is not ready until _task_ready() is called _task_abort _task_destroy Terminated _task_create Active Ready _task_block Blocked _task_ready UEE 3303 23 YL Huang Spring‘14 © NCTU Creating a Task ° When creating a task you have to: ! Make the task prototype and index definition #define INIT_TASK 5 extern void init_task(uint_32); ! Add the task in the Task Template List TASK_TEMPLATE_STRUCT MQX_template_list[] = { { TASK_INDEX, TASK, STACK, TASK_PRIORITY, TASK_NAME, TASK_ATTRIBUTES, CREATION_PARAMETER, TIME_SLICE} } Using the init_task example: TASK_TEMPLATE_STRUCT MQX_template_list[] = { {INIT_TASK, init_task, 1500, 9, init, MQX_AUTO_START_TASK, 0, 0}, } UEE 3303 24 YL Huang Spring‘14 © NCTU
7 Creating a Task ° When creating a task you have to: ! Make the task definition void init_task(void) { /* Put the Task Code here */ } ! During execution time, create the task using task_create() (if it is not an autostart task) UEE 3303 25 YL Huang Spring‘14 © NCTU MQX_Template_List { WORLD_ID, world_task, 0x3000, 9, world_task, MQX_AUTO_START_TASK, 0L, 0}, { HELLO_ID, hello_task, 0x1000, 8, “hello_task, MQX_TIME_SLICE_TASK, 0L, 100}, { LED_ID, led_task, 0x2000, 10, “LED Task, MQX_AUTO_START_TASK | MQX_TIME_SLICE_TASK, 0L, 50}, UEE 3303 26 YL Huang Spring‘14 © NCTU MQX - Task Management Example void init_task(void) { _task_create(0,TASK_A,0); ... _task_ready(Task_B); ... } {INIT_TASK, init_task, 1500, 11, init, MQX_AUTO_START_TASK, 0, 0}, void Task_A(void) { ... _task_create_blocked(0,TASK_B,0); ... _task_abort(TASK_A); } void Task_B(void) { ... _task_abort(TASK_B); } init_task is created when MQX starts CPU Time {TASK_A, Task_A, 1500, 10, “Task A, 0, 0, 0}, {TASK_B, Task_B, 1500, 9, “Task B, 0, 0, 0}, UEE 3303 27 YL Huang Spring‘14 © NCTU Freescale MQX™ Documentation ° MQXUG User Guide ° MQXRM Reference Manual ° MQXUSBHOSTAPIRM USB Host API Reference Manual ° MQXUSBDEVAPI USB Device API Reference ° MQXUSBHOSTUG USB Host User Guide ° MQXRTCSUG RTCS User Guide ° MQXMFSUG File System User Guide ° MQXIOUG I/O Drivers User Guide ° MQXFS Software Solutions Fact Sheets UEE 3303 28 YL Huang Spring‘14 © NCTU
8 Further Reading and Training ° TWR-MCF51CN-KIT Lab Document ° MCF5225x – Lab Document ° MQX Release Notes ° MQX User’s Guide ° Writing First MQX Application (AN3905) ° Using MQX: RTCS, USB, and MFS (AN3907) ° How to Develop I/O Drivers for MQX (AN3902) UEE 3303 29 YL Huang Spring‘14 © NCTU Further Reading and Training (Cont.) ° Videos: www.freescale.com/mqx ! MCF5225x Freescale MQX introduction ! Getting started with MCF5225x and Freescale MQX Lab Demos ! And more ° vFTF technical session videos www.freescale.com/vftf ! Introducing a modular system, Serial-to-Ethernet V1 ColdFire® MCU and Complimentary MQX™ RTOS ! Writing First MQX Application ! Implementing Ethernet Connectivity with the complimentary Freescale MQX™ RTOS UEE 3303 30 YL Huang Spring‘14 © NCTU In Summary By now, you should be able to: ° Understand what an RTOS is and how they can be used ° Create tasks and schedule them using MQX ° Create your own MQX applications UEE 3303 31 YL Huang Spring‘14 © NCTU 31

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嵌入式系統 課程講義

  • 1.
    1 UEE1076 Introductionto Embedded Systems Lecture 1 Introduction YuLun Huang http://rtes.cn.nctu.edu.tw UEE 3303 <1> YL Huang Spring‘14 © NCTU What is a computer? ° Components: • Input (mouse, keyboard) • Output (display, printer) • Memory (disk drives, DRAM, SRAM, CD) • Network ° Our primary focus: the processor (datapath and control) • Implemented using millions of transistors • Impossible to understand by looking at each transistor • We need … UEE 3303 <2> YL Huang Spring‘14 © NCTU What are embedded computing systems? ° Processing Unit: CPU • On-chip memory • Off-chip memory ° Input: mouse, keyboard ° Output: screen ° Memory and storage ° Communication (data): NIC ° Software UEE 3303 <3> YL Huang Spring‘14 © NCTU Definition ° Embedded computing system: • Any device that includes a programmable computer but is not itself a general-purpose computer ° Take advantage of application characteristics to optimize the design: • Don’t need all the general-purpose bells and whistles UEE 3303 <4> YL Huang Spring‘14 © NCTU
  • 2.
    2 Embedding acomputer CPU output analog input mem analog embedded computer UEE 3303 <5> YL Huang Spring‘14 © NCTU The History ° System ° Systom on Board ° System on Chip (SoC) ° … ° MCU • Memory embedded ° MPU • High frequency • External memory required UEE 3303 <6> YL Huang Spring‘14 © NCTU Examples ° Cell phone ° Printer ° Automobile: engine, brakes, dash, etc ° Airplane: engine, flight controls ° Digital television ° Household appliances UEE 3303 <7> YL Huang Spring‘14 © NCTU Early history ° Late 1940’s: MIT Whirlwind computer was designed for real-time operations • Originally designed to control an aircraft simulator ° First microprocessor was Intel 4004 in early 1970’s. ° HP-35 calculator used several chips to implement a microprocessor in 1972 ° Automobiles used microprocessor-based engine controllers starting in 1970’s • Control fuel/air mixture, engine timing, etc. • Multiple modes of operation: warm-up, cruise, hill climbing, etc. • Provides lower emissions, better fuel efficiency UEE 3303 <8> YL Huang Spring‘14 © NCTU
  • 3.
    3 Instruction SetArchitecture ° A very important abstraction • interface between hardware and low-level software • standardizes instructions, machine language bit patterns, etc. • advantage: different implementations of the same architecture • disadvantage: sometimes prevents using new innovations True or False: Binary compatibility is extraordinarily important? ° Modern instruction set architectures: • IA-32, PowerPC, MIPS, SPARC, ARM, and others UEE 3303 <9> YL Huang Spring‘14 © NCTU CISC vs. RISC ° CISC emphasizes hardware complexity. RISC emphasizes compiler complexity. CISC emphasizes hardware complexity. RISC emphasizes compiler complexity. RISC processor: simpler; the core can operate at higher clock frequencies. CISC processor: more complex and operate at lower clock frequencies. UEE 3303 <10> YL Huang Spring‘14 © NCTU The Instruction Set: a Critical Interface instruction set software hardware R12 = R14 – R15 11100000010011101100000000001111 UEE 3303 <11> YL Huang Spring‘14 © NCTU MIPS R3000 Instruction Set Architecture (Summary) ° Instruction Categories • Load/Store • Computational • Jump and Branch • Floating Point - coprocessor • Memory Management • Special Registers R0 - R31 PC HI LO 3 Instruction Formats: all 32 bits wide OP OP OP rs rt rd sa funct rs rt immediate jump target UEE 3303 <12> YL Huang Spring‘14 © NCTU
  • 4.
    4 ISA ina System Application Compiler Operating System Firmware Instr. Set Proc. I/O system Datapath & Control Digital Design Circuit Design Instruction Set Architecture Layout ° Coordination of many levels of abstraction ° Under a rapidly changing set of forces ° Design, Measurement, and Evaluation UEE 3303 <13> YL Huang Spring‘14 © NCTU
  • 5.
    1 DCN2561 ComputerArchitecture Lecture 2 Instructions: Language of the Computer YuLun Huang rtes.cn.nctu.edu.tw UEE 3303 <1> YL Huang Spring‘14 © NCTU von Neumann architecture ° Central processing unit (CPU) fetches instructions from memory. • Separate CPU and memory distinguishes programmable computer. ° CPU registers help out: program counter (PC), instruction register (IR), general-purpose registers, etc. ° Memory holds data and instructions. UEE 3303 <2> YL Huang Spring‘14 © NCTU Registers vs. Memory ° MIPS: arithmetic instructions operands must be registers, — only 32 registers provided ° Compiler associates variables with registers ° What about programs with lots of variables Control Datapath Memory Input Output Processor I/O UEE 3303 <3> YL Huang Spring‘14 © NCTU Memory Organization ° Viewed as a large, single-dimension array, with an address. ° A memory address is an index into the array ° "Byte addressing" means that the index points to a byte of memory. 0 1 2 3 4 5 6 ... 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data UEE 3303 <4> YL Huang Spring‘14 © NCTU
  • 6.
    2 Memory Operands ° Complex data structures – array/structures – are kept in memory ° Arithmetic operations occur only on registers in MIPS instr. • MIPS must include instructions that transfer data between memory and registers - Data transfer instructions • To access a word in memory, the instruction must supply the memory ‘address’ UEE 3303 <5> YL Huang Spring‘14 © NCTU Byte vs. Word ° Bytes are nice, but most data items use larger "words" ° For MIPS, a word is 32 bits or 4 bytes. 0 4 8 12 ... 32 bits of data Word must start at addr 32 bits of data the are multiples of 4 32 bits of data 32 bits of data Registers hold 32 bits of data ° 232 bytes with byte addresses from 0 to 232-1 ° 230 words with byte addresses 0, 4, 8, ... 232-4 ° Words are aligned i.e., what are the least 2 significant bits of a word address? - Left most: big endian - Right most: little endian UEE 3303 <6> YL Huang Spring‘14 © NCTU Instructions ° Load and store instructions ° Example: C code: A[12] = h + A[8]; MIPS code: lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 48($s3) 1. h is associated with $s2 2. base addr of array A is in $s3 ° Can refer to registers by name (e.g., $s2, $t2) instead of number ° Store word has destination last ° Remember arithmetic operands are registers, not memory! Can’t write: add 48($s3), $s2, 32($s3) UEE 3303 <7> YL Huang Spring‘14 © NCTU So far ° Instruction Meaning add $s1,$s2,$s3 $s1 = $s2 + $s3 sub $s1,$s2,$s3 $s1 = $s2 – $s3 lw $s1,100($s2) $s1 = Memory[$s2+100] sw $s1,100($s2) Memory[$s2+100] = $s1 bne $s4,$s5,L Next instr. is at Label if $s4 ≠ $s5 beq $s4,$s5,L Next instr. is at Label if $s4 = $s5 j Label Next instr. is at Label ° Formats: ? op rs rt rd shamt funct op rs rt 16 bit address op 26 bit address R I J R: register I: immediate UEE 3303 <8> YL Huang Spring‘14 © NCTU
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    3 Assembly Languagevs. Machine Language ° Assembly provides convenient symbolic representation • much easier than writing down numbers • e.g., destination first ° Machine language is the underlying reality • e.g., destination is no longer first ° Assembly can provide 'pseudoinstructions' • e.g., “move $t0, $t1” exists only in Assembly • would be implemented using “add $t0,$t1,$zero” ° When considering performance you should count real instructions UEE 3303 <9> YL Huang Spring‘14 © NCTU Other Issues ° Discussed in your assembly language programming lab: support for procedures linkers, loaders, memory layout stacks, frames, recursion manipulating strings and pointers interrupts and exceptions system calls and conventions ° Some of these we'll talk more about later ° We’ll talk about compiler optimizations when we hit chapter 4. UEE 3303 <10> YL Huang Spring‘14 © NCTU Overview of MIPS ° simple instructions all 32 bits wide ° very structured, no unnecessary baggage ° only three instruction formats op rs rt rd shamt funct op rs rt 16 bit address op 26 bit address R I J ° rely on compiler to achieve performance — what are the compiler's goals? ° help compiler where we can UEE 3303 <11> YL Huang Spring‘14 © NCTU
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    1 UEE3303 Introductionto Embedded Systems Lecture 3 ARM YuLun Huang http://rtes.cn.nctu.edu.tw Ď UEE 3303 <1> YL Huang Spring ‘14 © NCTU ARM instruction set ° ARM versions ° ARM assembly language ° ARM programming model ° ARM memory organization ° ARM data operations ° ARM flow of control UEE 3303 <2> YL Huang Spring ‘14 © NCTU ARM versions ° ARM architecture has been extended over several versions • ARM7 • ARM9/9E • ARM10E • ARM11 • Cortex • SecurCore ° We will concentrate on ARM7 UEE 3303 <3> YL Huang Spring ‘14 © NCTU ARM11 FamilyĎ CatchĎ Tightly Couple MemoryĎ Memory ManagementĎ AHBĎ Thumb Ď DSP Ď Jazelle Ď ARM11MP Core Ď MM U+cache coherency Ď 1× or 2×AMBA AXI Ď v Ď v Ď v Ď ARM1136J (F)-S Ď variable Ď v Ď MMU Ď 5×AHB Ď vĎ v Ď v Ď ARM1156T 2(F)-S Ď variable Ď v Ď MPU Ď 3×AXI Ď v Ď v Ď x Ď ARM1176J Z(F)-S Ď variable Ď v Ď MMU+ TrustZone Ď 4×AXI Ď v Ď v Ď v Ď UEE 3303 <4> YL Huang Spring ‘14 © NCTU
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    2 ARM DesignPhilosophy Ď° Many physical features drove the ARM processor design: • Portability (require some form of battery power): smaller - reduce power consumption and extend battery operation -essential for applications (eg. PDAs). - more available space for specialized peripherals (low cost) • Limited Memory (due to cost and/or physical size restrict) - High code density • Price sensitive: - Use slow and low-cost memory devices ° ARM core: not a pure RISC architecture due to the constraints of its primary application - the embedded system. • In some sense, the strength of the ARM core is that it does not take the RISC concept too far. ° The key is not raw processor speed but total effective system performance and power consumption. UEE 3303 <6> YL Huang Spring ‘14 © NCTU UEE 3303 <5> YL Huang Spring ‘14 © NCTU ARM vs. MIPSĎ ° ⎰Ἕ㊯Ẍ • MIPS ㊯Ẍ⣒忶䯉╖炻ARM㊯Ẍ▿娎⎴㗪⬴ㆸ怷廗嗽䎮冯䦣 ỵ嗽䎮 ° 忋临屯㕁嗽䎮 • 慵㕘姕妰ġlw/swġ㊯Ẍ炻ἧ℞⎗ẍ忋临⁛廠屯㕁炻㍸ὃ屯㕁䘬 ⁛廠㓰䌯 ° 㡅ẞ⺷㊯Ẍ • ὅ㒂⇵朊➟埴䳸㝄㰢⭂㗗⏎➟埴娚㊯Ẍ炻啱ẍ㍸檀㊯Ẍ䘬➟ 埴㓰䌯 ° 䯉妨ᷳ, ARM ㍉䓐悐↮ġRISC 姕妰㤪⾝: • Load-store architecture • Fixed-length 32-bit instructions • 3-address instruction format ARM Design Philosophy Ď° The ARM instruction set differs from the pure RISC definition in several ways that make the ARM instruction set suitable for embedded applications: • Variable cycle execution for certain instructions • Inline barrel shifter leading to more complex instructions • Thumb 16-bit instruction set • Conditional execution • Enhanced instructions ° These additional features have made the ARM processor one of the most commonly used 32-bit embedded processor cores. Ď UEE 3303 <7> YL Huang Spring ‘14 © NCTU High Code Density?Ď ° Two types of instruction sets - Subset of ARM instructions ARMĎ ThumbĎ • ARM instructions: 32 bit • Thumb instructions: 16 bits Length/instructionĎ 32 bitĎ 16 bitĎ Number of Instr.Ď NĎ 1.4NĎ Code sizeĎ K Ď 0.7KĎ Code DensityĎ LowĎ High Performance (16bit memory)Ď PĎ 1.43P (faster) UEE 3303 <8> YL Huang Spring ‘14 © NCTU
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    3 Different ARMcores: StrongARM vs. XscaleĎ CatchĎ Tightly Couple MemoryĎ Memory Mangem entĎ AHBĎ Thumb Ď DSP Ď Jazelle Ď Strong ARM Ď 16K/8K Ď xĎ MMU Ď N/A Ď xĎ xĎ xĎ XScale Ď 32K/32K Ď xĎ MMU Ď N/A Ď vĎ vĎ xĎ UEE 3303 <9> YL Huang Spring ‘14 © NCTU ARM ArchitectureĎ ° 7 modes • usr – normal execution • sys – privileged OS tasks • fiq – fast interrupt • irq – general interrupt • svc – protected mode for OS • abt – vir mem (mem protect) • und – for s/w emulation ° 37 registers • 30: general purpose • 6: status • 1: program counter UEE 3303 <10> YL Huang Spring ‘14 © NCTU ModesĎ ModeĎ CodeĎ DescriptionĎ User (usr)Ď 10000Ď Normal mode; only condition flags in cpsr can be changedĎ FIQ (fiq)Ď 10001Ď Fast interruptĎ IRQ (irq)Ď 10010Ď Normal interruptĎ Supervisor (svc)Ď 10011Ď OS kernelĎ Abort (abt)Ď 10111Ď Memory protectionĎ Undefined (und)Ď 11011Ď Software emulationĎ System (sys)Ď 11111Ď Normal mode, but be able to r/w cpsrĎ UEE 3303 <11> YL Huang Spring ‘14 © NCTU RegistersĎ ° ARM 嗽䎮☐㚱ġ37ġᾳ㙓⬀☐炻⊭㊔ • [15] 30ᾳ忂䓐㙓⬀☐ • [1] 1 PC • [1] 6ġᾳ䉨ン㙓⬀☐烉CPSR x 1 + SPSR x 5 ° ARM 㚱ġ7ġ䧖ⶍἄ㧉⺷ • 㭷ᶨ䧖㧉⺷ᶳ悥㚱ᶨ䳬䚠⮵䘬㙓⬀☐冯ᷳ⮵ㅱ UEE 3303 <12> YL Huang Spring ‘14 © NCTU
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    4 ARM RegisterOrganizationĎ UEE 3303 <13> YL Huang Spring ‘14 © NCTU ARM registersĎ ° There are up to 17 active registers: • 16 data registers and 2 processor status registers • data registers are visible to the programmer as R0 to R15 - R0 ~ R7：不分組暫存器，真正的通用暫存器。 - R8 ~ R14：分組暫存器，與處理器模式有關。 ° three special registers: R13, R14, and R15 • R13 - stack pointer (sp), stores the head of the stack in the current processor mode • R14 - link register (lr), where the core puts the return address whenever it calls a subroutine • R15 - program counter (pc), contains the address of the next instruction to be fetched by the processor ° R13 and R14 can also be used as general-purpose registers, but DANGEROUS!! ° One more register: PSR Ď UEE 3303 <14> YL Huang Spring ‘14 © NCTU ARM registersĎ ° two program status registers (PSR): CPSR and SPSR • current program status registers烉⃚⬀䚖⇵䉨ン炻⏓㕿㧁ˣᷕ㕟ỵ⃫… • saved program status registers烉ᾅ䔁ġCPSRġ䘬䉨ン ° The register file contains all the registers available to a programmer ° Which registers are visible to the programmer depend upon the current mode of the processor. UEE 3303 <15> YL Huang Spring ‘14 © NCTU Example: When FIQ Exception Occurs..Ď UEE 3303 <16> YL Huang Spring ‘14 © NCTU
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    5 Then, theARM processorĎ ° When an exception occurs, the ARM core: • SPSR_fiq ← CPSR • Set CPSR bits - T: thumb or arm - Mode = 10001 (fiq) - Disable interrupt, if appropriate • Map registers • LR_fiq ← PC • PC ← 0x0000 001c (vector address) ° To return, the exception handler need to: • CPSR ← SPSR_fiq • PC ← LR_fiqĎ UEE 3303 <17> YL Huang Spring ‘14 © NCTU ARM programming model R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC) 31 0 CPSR N Z C V N: Negative/Less Than Z: Zero C: Carry/Borrow/Extend V: OverflowĎ T:ġ嬻嗽䎮☐⎗ẍ冒䓙⛘⛐ ARMġ␴ġThumbġᷳ攻↯㎃Ď UEE 3303 <18> YL Huang Spring ‘14 © NCTU Endianness ° Relationship between bit and byte/word ordering defines endianness: bit 31 bit 0 bit 0 bit 31 byte 3 byte 2 byte 1 byte 0 byte 0 byte 1 byte 2 byte 3 little-endian big-endian UEE 3303 <19> YL Huang Spring ‘14 © NCTU ARM data types ° Word is 32 bits long ° Word can be divided into four 8-bit bytes ° ARM addresses cam be 32 bits long ° Address refers to byte • Address 4 starts at byte 4 ° Can be configured at power-up as either little- or big-endian mode UEE 3303 <20> YL Huang Spring ‘14 © NCTU
  • 13.
    6 ARM statusbits ° Every arithmetic, logical, or shifting operation sets CPSR bits: • N (negative), Z (zero), C (carry), V (overflow) ° Examples: • -1 + 1 = 0: NZCV = 0101 • 231-1+1 = 231: NZCV = 0000 • -2 + -5 = -7: NZCV = 1010 • N is set as bit 31 • Z is set result is 0 • V is set when the register cannot properly represent the result as a signed value (you overflowed into the sign bit). • C is set when the register cannot properly represent the result as an unsigned value (no sign bit required). Ď UEE 3303 <21> YL Huang Spring ‘14 © NCTU Carry vs. Overflow (8-bit examples): generic conceptĎ ° Unsigned operation: 0x70 + 0x68 = 0xD8 • No carry, no oVerflow ° Unsigned operation: 0xC0 + 0xD8 = 0x98 • Carry, but no oVerflow • Sign of the result is correct • The "correct" answer is actually 0x198. ° Signed operation: -0x40 + -0x28 = -0x68 • No carry, no "oVerflow" • Result of the arithmetic is correct ° Signed operation: 0x70 + -0x98 = 0x28 • No carry, but oVerflow • The answer is obviously wrong • The V flag reveals that the "correct" answer is -0x28.Ď UEE 3303 <22> YL Huang Spring ‘14 © NCTU ARM InstructionsĎ UEE 3303 <23> YL Huang Spring ‘14 © NCTU ARM ASM Ď .text ; Executable code follows _start: .global _start ; "_start" is required by the linker .global main ; "main" is our main program b main ; Start running the main program main: ; Entry to the function "main" ; Insert your code here mov pc,lr ; Return to the caller .endĎ UEE 3303 <24> YL Huang Spring ‘14 © NCTU
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    7 Types ofARM InstructionsĎ ° Arithmetic operations ° Comparisons (no results - just set condition codes) ° Logical operations ° Data movement between registersĎ UEE 3303 <25> YL Huang Spring ‘14 © NCTU Arithmetic OperationsĎ ° Syntax • <Operation>{<cond>}{S} Rd, Rn, Operand2 ° Operations are • ADD operand1 + operand2 • ADC operand1 + operand2 + carry • SUB operand1 - operand2 • SBC operand1 - operand2 + carry -1 ° Examples ADD r0, r1, r2 SUBGT r3, r3, #1 UEE 3303 <26> YL Huang Spring ‘14 © NCTU ComparisonsĎ ° The only effect of the comparisons is to • UPDATE THE CONDITION FLAGS. (no need to set S bit.) ° Syntax: • <Operation>{<cond>} Rn, Operand2 ° Operations are: • CMP operand1 - operand2, but result not written • CMN operand1 + operand2, but result not written • TST operand1 AND operand2, but result not written • TEQ operand1 EOR operand2, but result not written ° Examples: CMP r0, r1 TSTEQ r2, #5Ď UEE 3303 <27> YL Huang Spring ‘14 © NCTU Logical OperationsĎ ° Syntax: • <Operation>{<cond>}{S} Rd, Rn, Operand2 ° Operations are: • AND operand1 AND operand2 • EOR operand1 EOR operand2 • ORR operand1 OR operand2 • BIC operand1 AND NOT operand2 [ie bit clear] ° Examples AND r0, r1, r2 BICEQ r2, r3, #7 EORS r1,r3,r0Ď UEE 3303 <28> YL Huang Spring ‘14 © NCTU
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    8 Data MovementĎ ° Syntax: • <Operation>{<cond>}{S} Rd, Operand2 ° Operations are: • MOV operand2 • Note that it makes no use of operand1. ° Examples: MOV r0, r1 MOVS r2, #10 UEE 3303 <29> YL Huang Spring ‘14 © NCTU GCD in CĎ int gcd(int a, int b){ int c; while ( a != b) { if (a > b) c = a - b; else c = b-a; b = a; a = c; } return a; } UEE 3303 <30> YL Huang Spring ‘14 © NCTU Convert & Replace variables with registersĎ UEE 3303 <31> YL Huang Spring ‘14 © NCTU ARM CodeĎ gcd cmp r0, r1 ;reached the end? beq stop blt less ;if r0 > r1 sub r0, r0, r1 ;subtract r1 from r0 bal gcd less sub r1, r1, r0 ;subtract r0 from r1 bal gcd stop UEE 3303 <32> YL Huang Spring ‘14 © NCTU
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    9 ARM ConditionalAssembler Ďgcd cmp r0, r1 ;if r0 > r1 subgt r0, r0, r1 ;subtract r1 from r0 sublt r1, r1, r0 ;else subtract r0 from r1 bne gcd ;reached the end?Ď UEE 3303 <33> YL Huang Spring ‘14 © NCTU QEMU EMULATORĎ UEE 3303 <34> YL Huang Spring ‘14 © NCTU ARM EmulatorĎ ° QEMU • an emulator that emulate real machines • supported platforms: arm MIPS x86…. ° QEMU Tools • Qemu.exe àemulator • Qemu-img.exe àdisk image tool xx.binĎ Realview-ebĎ xx.binĎ Realview-ebĎ Qemu Ď Qemu Ď UbuntuĎ VMPlayer/Virtual X86Ď BoxĎ WindowsĎ UbuntuĎ UEE 3303 <35> YL Huang Spring ‘14 © NCTU So, after launch VMPlayerĎ ° You login to ubuntu ° Launch QEMU • qemu-system-arm • qemu-arm ° You need to specify the target to be emulated ° You also need to specify the kernel image for the targetĎ UEE 3303 <36> YL Huang Spring ‘14 © NCTU
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    10 Our QEMUsupports..Ď codeĎ targetĎ codeĎ targetĎ syborgĎ Symbian Virtual PlatformĎ borzoiĎ PDA, PXA270Ď musicpalĎ Marvell 88w8618Ď terrierĎ PDA, PXA270Ď mainstoneĎ PXA27xĎ connexĎ Gumstix PXA255Ď N800, n810Ď Nokia N800/N810 tabletĎ verdexĎ Gumstix PXA270Ď cheetahĎ Palm TungstenĎ lm3s811evbĎ StellarisĎ sx1Ď Siemens SX1 v2Ď lm3s6965evbĎ StellarisĎ sx1-v1Ď Siemens SX1 v1Ď realview-ebĎ ARM926Ď tosaĎ PDA, PXA255Ď realview-eb-mpcore Ď ARM11Ď akitaĎ PDA, PXA270Ď realview-pb-a8Ď Cortex-A8Ď spitzĎ PDA, PXA270Ď versatilepbĎ …Ď UEE 3303 <37> YL Huang Spring ‘14 © NCTU 忚ℍġqemu ᷳ⼴Ď ° ⛐➟埴ġQEMU ⼴炻㚫↢䎦ˬ(qemu)˭ġ䘬㍸䣢ˤ⛐忁ᾳ㍸䣢ᶳ⎗ẍ廠ℍ ᶨṃ㊯ẌἮ㑵ἄġQEMUˤ ° QEMU ㊯Ẍ • help ㆾġ? [cmd]: 栗䣢婒㖶㔯⫿Ď • info: 栗䣢䲣䴙䉨ンˤἳ烉Ď • info network - 栗䣢䵚嶗ṳ朊䉨ンĎ • info block - 栗䣢⃚⬀墅伖䉨ンĎ • info registers - 栗䣢ġCPU 䘬㙓⬀☐䉨ンĎ • info history - 栗䣢㬟⎚㊯ẌĎ • What else? UEE 3303 <38> YL Huang Spring ‘14 © NCTU infoĎ ° info version -- show the version of QEMU ° info network -- show the network state ° info chardev -- show the character devices ° info block -- show the block devices ° info blockstats -- show block device statistics ° info registers -- show the cpu registers ° info cpus -- show infos for each CPU ° info history -- show the command line history ° info irq -- show the interrupts statistics (if available) ° info pic -- show i8259 (PIC) state ° info pci -- show PCI info ° info jit -- show dynamic compiler info ° info kvm -- show KVM information ° info numa -- show NUMA information ° info usb -- show guest USB devices ° info usbhost -- show host USB devices ° info profile -- show profiling information ° info capture -- show capture information ° info snapshots -- show the currently saved VM snapshots ° info status -- show the current VM status (running|paused) ° info pcmcia -- show guest PCMCIA status ° info mice -- show which guest mouse is receiving events ° info vnc -- show the vnc server status ° info name -- show the current VM name ° info uuid -- show the current VM UUID ° info usernet -- show user network stack connection states ° info migrate -- show migration status ° info balloon -- show balloon information ° info qtree -- show device tree ° info qdm -- show qdev device model list ° info roms -- show roms UEE 3303 <39> YL Huang Spring ‘14 © NCTU 忚ℍġqemu ᷳ⼴Ď ° q ㆾġquit:ġ斄攱㧉㒔☐ ° eject [-f] device烉徨↢墅伖ˤġ-f 堐䣢⻟⇞徨↢ ° change device filename:ġ㚜㎃㉥⍾⺷⨺橼炻⤪庇䡇䇯ㆾ⃱䡇䇯ˤ ° screendump filename: ㇒⍾坊ⷽ䔓朊炻⃚⬀ㆸġPPM ⼙⁷ˤġlog item1[,...]: ⮯㇨㊯⭂䘬枭䚖ᷳġLOG ⮓ℍġ/tmp/qemu.log ᷕˤ ° savevm filename: ⮯㔜ᾳ㧉㒔☐䉨ン⃚⬀军㨼㟰ᷕ ° loadvm filename: 䓙㨼㟰ᷕ庱ℍ㧉㒔☐䉨ン ° Stop:  㬊㧉㒔 ° c ㆾġcont: 两临㧉㒔 ° sendkey keys: ⁛復㝸ᾳkey䴎㧉㒔☐ˤἧ䓐ġ- Ἦ忋䳸墯⎰挝ˤ • ἳ烉``sendkey ctrl-alt-f1”ġ堐䣢⁛復ġ<Ctrl><Alt><F1> 䴎㧉㒔☐ˤ ° system_reset:ġ慵㕘┇≽䲣䴙ˤĎ UEE 3303 <40> YL Huang Spring ‘14 © NCTU
  • 18.
    A R M組合語言與指令集介紹 ! !!!㛔䪈ṳ䳡 BSN ㊯Ẍ普ˣUivnc ㊯Ẍ普炻ẍ⍲⎬栆㊯Ẍ⮵ㅱ䘬⭂⛨㕡⺷炻忂忶⮵ 㛔䪈䘬教嬨炻ⶴ㛃嬨侭傥䝕妋 BSN ⽖嗽䎮☐㇨㓗㎜䘬㊯Ẍ普⍲℟橼䘬ἧ䓐㕡㱽ˤ! !!!! 1 A R M 指令集的分類與格式 BSN ⽖嗽䎮☐䘬㊯Ẍ普㗗Ⱄ㕤!庱ℍ0⬀⚆!✳䘬炻ḇ⌛㊯Ẍ普傥嗽䎮㙓⬀ ☐ᷕ䘬屯㕁炻侴ᶼ嗽䎮䳸㝄悥天㓦⚆㙓⬀☐ᷕ炻侴⮵䲣䴙姀ㅞ橼䘬⬀⍾⇯暨天忂 忶⮰攨䘬!庱ℍ0⬀⚆!㊯ẌἮ⬴ㆸˤ! BSN⽖嗽䎮☐䘬㊯Ẍ普⎗ẍ↮䁢嶛廱㊯Ẍˣ屯㕁嗽䎮㊯Ẍˣ䦳⺷䉨ン㙓⬀☐ 炷QTS炸嗽䎮㊯Ẍˣ庱ℍ0⬀⚆㊯Ẍˣ庼≑忳䬿☐㊯Ẍ␴ἳ⢾䓊䓇㊯Ẍℕ⣏栆炻℟ 橼䘬㊯Ẍ⍲≇傥⤪堐3.2㇨䣢炷堐ᷕ㊯Ẍ䁢➢㛔BSN㊯Ẍ炻ᶵ⊭㊔埵䓇䘬BSN㊯Ẍ炸ˤ! BSN 䘬㊯Ẍ普⣏农ᶲ⎗ẍ↮䁢ℕ⣏栆烉! l 嶛廱㊯Ẍ)Csbodi!Jotusvdujpot*烉! 忂ⷠ㗗䓐Ἦ 䦳⺷㳩䦳㍏⇞ˤ! l 屯㕁嗽䎮㊯Ẍ)Ebub.qspdfttjoh!Jotusvdujpot*烉! ᶨ凔䘬㙓⬀☐忳䬿㊯Ẍˤ! l 庱ℍ⬀⚆㊯Ẍ)Mpbe!boe!Tupsf!Jotusvdujpot*烉! ⮵姀ㅞ橼␴㙓⬀☐ᷳ攻䘬屯㕁㏔䦣㊯Ẍˤ! l 䉨ン㙓⬀☐⬀⍾㊯Ẍ)Tubuvt!Sfhjtufs!Usbotgfs!Jotusvdujpot*烉! ⬀⍾ DQTS ␴ TQTS 㙓⬀☐䘬䚠斄㊯Ẍˤ! l 庼≑忳䬿☐)⋼⎴嗽䎮☐*㊯Ẍ)Dpqspdfttps!Jotusvdujpot*烉! ⬀⍾⋼⎴嗽䎮☐ㆾ冯⋼⎴嗽䎮☐㹅忂ᷳ㊯Ẍˤ! l ἳ⢾䓊䓇㊯Ẍ)Fydfqujpo.hfofsbujoh!Jotusvdujpot*烉! 䓊䓇庇橼ᷕ㕟␴℞Ṿἳ⢾䘬㊯Ẍˤ! ! ㊯Ẍ䫎嘇! ㊯Ẍ≇傥㍷徘! 㔠⬠忳䬿)Bsjuinfujd!jotusvdujpo* ! BED! 䲵ℍ忚ỵ㕿㧁䚠≈㊯Ẍ! BEE! ≈㱽㊯Ẍ! DNO! 㭼庫⍵嘇㊯Ẍ! DNQ! 㭼庫㊯Ẍ! TVC! 㷃㱽㊯Ẍ! TVD! 䲵ℍ忚ỵ㕿㧁䚠㷃㊯Ẍ! NMB! 43 ỵ⃫䚠Ḁ᷎䚠≈㊯Ẍ! NVM! 43 ỵ⃫Ḁ㱽㊯Ẍ! STC! ⮵婧䚠㷃㊯Ẍ! STD! 䲵ℍ忚ỵ㕿㧁⮵婧䚠㷃㊯Ẍ! 怷廗忳䬿)Mphjd!jotusvdujpo* ! BOE! BOE 忳䬿㊯Ẍ! ! 第2 頁!
  • 19.
    CJD! ỵ⃫㶭暞)cju!dmfbs*㊯Ẍ! FPS!Fydmvtjwf!ㆾ!忳䬿㊯Ẍ! PSS! PSS 忳䬿㊯Ẍ! UFR! 䚠䫱㷔娎㊯Ẍ! UTU! ỵ⃫㷔娎㊯Ẍ! 嶛廱㊯Ẍ)Csbodi!Jotusvdujpo* ! C! 嶛廱㊯Ẍ! CM! ⷞ彼⚆䘬嶛廱㊯Ẍ! CMY! ⷞ彼⚆␴䉨ン↯㎃䘬嶛廱㊯Ẍ! CY! ⷞ䉨ン↯㎃䘬嶛廱㊯Ẍ! 庱ℍ㊯Ẍ)Mpbe!Jotusvdujpo* ! MEN! 庱ℍ⣂ᾳ㙓㊯Ẍ! MES! 姀ㅞ橼⇘㙓⬀☐䘬屯㕁⁛廠㊯Ẍ! ㏔䦣㊯Ẍ)Npwf!jotusvdujpo* ! NPW! 屯㕁⁛復)㏔䦣*㊯Ẍ! NWO! 屯㕁⍾⍵㏔䦣㊯Ẍ! NST! ⁛復 DQTS ㆾ TQTS 䘬㔠ῤ⇘ᶨ凔㙓⬀☐㊯Ẍ! NTS! ⁛復ᶨ凔㙓⬀☐⇘ DQTS ㆾ TQTS 䘬㊯Ẍ! 庼≑忳䬿☐)⋼⎴嗽䎮☐*!)Dpqspdfttps!jotusvdujpo* ! NDS! ⽆ BSN 㙓⬀☐䘬㔠ῤ⇘庼≑忳䬿☐)⋼⎴嗽䎮☐*㙓⬀☐䘬屯㕁⁛廠㊯Ẍ! NSD! ⽆庼≑忳䬿☐)⋼⎴嗽䎮☐*㙓⬀☐䘬㔠ῤ⇘ BSN 㙓⬀☐䘬屯㕁⁛廠㊯Ẍ! MED! ⽆庼≑忳䬿☐)⋼⎴嗽䎮☐*㙓⬀☐䘬㔠ῤ⇘姀ㅞ橼䘬屯㕁⁛廠㊯Ẍ! TUD! ⽆姀ㅞ橼ℏ䘬㔠ῤ⇘庼≑忳䬿☐)⋼⎴嗽䎮☐*㙓⬀☐䘬屯㕁⁛廠㊯Ẍ! DEQ! 庼≑忳䬿☐屯㕁㑵ἄ㊯Ẍ! 庇橼ᷕ㕟)Tpguxbsf!Joufssvqu!jotusvdujpo* ! TXJ! 妠䘤庇橼ᷕ㕟㊯Ẍ! TCD! ⷞῇỵ㷃㱽㊯Ẍ! ⃚⬀㊯Ẍ)Tupsx!jotusvdujpo* ! TUN! ⣂慵姀ㅞ橼⮓ℍ㊯Ẍ! TUS! 㙓⬀☐⇘姀ㅞ橼䘬屯㕁⁛廠㊯Ẍ! ℞Ṿ㊯Ẍ)Puifst*! OPQ! 䃉㊯Ẍ! TXQ! 㙓⬀☐冯姀ㅞ橼㔠ῤṌ㎃㊯Ẍ! 堐 3 . 2 !!!B S N ㊯Ẍ⍲≇傥㍷徘! ! 1.1 ARM 條件式指令 ᶨ凔 BSN ㊯Ẍ䘬℠✳㊯Ẍ䶐䡤㟤⺷⤪ᶳ㇨䣢烉! 42! 39! 38! 36! 35! 32! 31! 2:! 27! 26! 23! 22! 1! dpoe! y!y!y! pqdpef! T! So! Se! tijgufs`pqfsboe! ! ℞ᷕ烉! ! dpoe! ! ! ㊯Ẍ➟埴䘬㡅ẞ⺷䶐䡤! ! pqdpef!! ! ㊯Ẍ㑵ἄ䫎嘇! ! T! ! ! ! ㊯⭂㗗⏎⛐忳䬿➟埴㗪枮ὧ㚜㕘 DQST 䘬㕿㧁! ! 第3 頁!
  • 20.
    ! So! !! ! ⊭⏓䫔ᶨᾳ忳䬿⃫䘬䚖㧁㙓⬀☐䘬䶐嘇! ! Se! ! ! ! 屯㕁Ἦ㸸㙓⬀☐䘬䶐嘇! ! tijgufs`pqfsboe! 䫔Ḵᾳ屯㕁Ἦ㸸忳䬿⃫! ! BSN 䘬㊯Ẍ⊭⏓ᶨᾳ⎗怠䘬㡅ẞ䡤ˤ⎒㚱⛐ DQTS ᷕ䘬㡅ẞ䡤㕿㧁㺧嵛㊯⭂䘬 㡅ẞ㗪炻ⷞ㡅ẞ䡤䘬㊯Ẍㇵ⎗ẍ➟埴ˤḇ⎗ẍ㟡㒂ᶨ㡅㊯Ẍ姕伖䘬㕿㧁炻㚱㡅ẞ ⛘➟埴⎎ᶨ㡅㊯Ẍˤ㭷ᶨ㡅 BSN ㊯Ẍ⊭⏓ 5 ỵ⃫䘬㡅ẞ䡤炻ỵ㕤㊯Ẍ䘬㚨檀 5 ỵ⃫42;39^ˤ㭷䧖㡅ẞ䡤⎗䓐ℑᾳ⫿⃫堐䣢炻忁ℑᾳ⫿⃫⎗ẍ㶣≈⛐㊯䫎嘇䘬 ⼴朊␴㊯Ẍ⎴㗪ἧ䓐ˤἳ⤪炻嶛廱㊯Ẍ C ⎗ẍ≈ᶲ⯦䡤 FR 嬲䁢 CFR 堐䣢Ⱦ䚠䫱 ⇯嶛廱ȿ炻⌛䔞 DQTS ᷕ䘬 [ 㕿㧁䁢 2 㗪䘤䓇嶛廱ˤ㡅ẞ䶐䡤㚱⤪ᶳ⸦䧖烉! ! 䶐䡤 4 2 ; 3 9 ^ ! 㡅ẞ㍷ 徘! 䉨ン㕿㧁! 忳䬿⏓佑! ㊯Ẍ䭬ἳ! 1111! FR! [!>!2! 䚠䫱! CFR! 1112! OF! [!>!1! ᶵ䫱ῤ! COF! 1121! DT0IT! D!>2! ⣏㕤䫱㕤! CDT! 1122! DD0MP! D!>!1! ⮷㕤! CDD! 1211! NJ! O!>2! 屈ῤ! CNJ! 1212! QM! O!>1! 㬋㔠ㆾ暞! CQM! 1221! WT! W!>!2! 㹊ỵ! CWT! 1222! WD! W!>!1! 䃉㹊↢! CWD! 2111! IJ! D!>!2!boe![!>!1! ⣏㕤! CIJ! 2112! MT! D!>!1!ps![!w! ⮷㕤䫱㕤! CMT! 2121! HF! O!>W!! ⣏㕤䫱㕤! CHF! 2122! MU! O!ɽ!W!! ⮷㕤! CMU! 2211! HU! [!>!1!boe!O!>!W! ⣏㕤! CHU! 2212! MF! [!>!2炻ps!O!ɽ!W! ⮷㕤ㆾ䫱㕤! CMF! 2221! BM! Boz! 枸姕ῤ! CBM! !!!!!!!!!!!!!!!!!!!!!!!!!!!!堐 3 . 3 !㡅ẞ⺷⭂佑ˣ䶐䡤冯嶛廱㊯Ẍ䭬ἳ! ! BSN ㊯Ẍ⎗㟡㒂➟埴䳸㝄Ἦ怠㑯㗗⏎㚜㕘㡅ẞ㕿㧁ỵ⃫ˤ劍天㚜㕘㡅ẞ㕿㧁ỵ ⃫炻枰⛐㊯Ẍᷕ⊭⏓⯦䡤ȾTȿˤ! ᶨṃ㊯Ẍᶵ暨天⯦䡤ȾTȿ炻⤪ DNQˣDNOˣUTU ␴ UFRˤ⬫Ᾱ䘬≇傥㛔Ἦ⯙㗗 㚜㕘㡅ẞ㕿㧁ỵ⃫䘬ˤ! 2 A R M 指令的定址方式 ⭂⛨㕡⺷⯙㗗嗽䎮☐㟡㒂㊯Ẍᷕ䴎↢䘬ỵ⛨屯妲Ἦ⮳㈦⮎晃ỵ⛨䘬㕡⺷ˤ䚖 ⇵ BSN ㊯Ẍ䘬⭂⛨㕡⺷)⭂⛨㱽*➢㛔ᶲ⎗ẍ↮䁢ẍᶳ⸦䧖烉! ! 2/!䩳⌛⭂⛨! ㊯Ẍᷕ⶚⊭⏓Ḯ忳䬿⃫炻⌛䩳⌛㔠ˤἳ⤪烉! BEE!S1炻S1炻炲2! ! ! 烊S1ɤS1為2! ! 第4 頁!
  • 21.
    BEE!S1炻S1炻炲1y4g! ! 烊S1ɤS1為1y4g! ! ⛐ẍᶲℑ㡅㊯Ẍᷕ炻䫔Ḵᾳ屯㕁Ἦ㸸忳䬿⃫)㔠ῤ*⌛䁢䩳⌛㔠炻᷎天㯪ẍ Ⱦ炲ȿ䁢⋨↮炻⮵㕤ẍ⋩ℕ忚ỵ堐䣢䘬䩳⌛㔠炻怬天㯪⛐Ⱦ炲ȿ⼴≈ᶲȾ1yȿㆾ Ⱦ'ȿˤ! ! ! 3/!㙓⬀☐䚜㍍⭂⛨! ㊯Ẍᷕ䘬ỵ⛨䶐䡤悐↮䴎↢㝸ᶨ㙓⬀☐䶐嘇炻忳䬿⃫)㔠ῤ*⛐㙓⬀☐ᷕˤἳ ⤪烉! BEE!S1-S2-S3! <S2,S3àS1! 娚㊯Ẍ䘬➟埴枮⸷䁢⮯㙓⬀☐S2␴S3䘬㔠ῤ䚠≈炻⮯℞䳸㝄⬀㓦⛐㙓⬀☐S1 ᷕˤ! ! 4/ 㙓⬀☐攻㍍⭂⛨! 㙓⬀☐攻㍍⭂⛨⯙㗗ẍ㙓⬀☐ᷕ䘬ῤἄ䁢忳䬿⃫䘬ỵ⛨炻侴忳䬿⃫㛔幓⬀㓦 ⛐姀ㅞ橼ᷕˤἳ⤪烉! MES!!S1-!S2^! <S2^àS1!!00⮯ S2 ㊯⎹䘬姀ㅞ橼ᷕ䘬ℏ⭡庱ℍ⇘ S1 ᷕˤ! TUS!!S1炻S2^! 烊S2^ɤS1!00⮯ S1 䘬ῤ⁛復⇘ẍ S2 䘬ῤ䁢ỵ⛨䘬姀ㅞ橼 ᷕˤ! ! 5/ 㙓⬀☐䦣ỵ⭂⛨! 䫔Ḵᾳ㙓⬀☐ᷕ⬀㓦䘬忳䬿⃫⃰忚埴䦣ỵ㑵ἄ炻䃞⼴冯䫔ᶨᾳ忳䬿⃫䳸⎰ˤ ἳ⤪烉! BEE!S1-!S2-!S3!MTM!$4!! <S2,S3+9àS1!!00S3 ᷕ䘬忳䬿⃫ⶎ䦣 4 ỵ⃫! ! ⎗ẍ㍉䓐䘬䦣ỵ㊯Ẍ㚱ẍᶳ⸦䧖烉! MTM)Mphjdbm!Tijgu!Mfgu*烉怷廗ⶎ䦣ˤ㙓⬀☐ᷕ䘬忳䬿⃫ⶎ䦣ᶨỵ炻MTM ⽆! cju!1 Ỷỵ墄 1 忚Ἦˤ! MTS)Mphjdbm! Tijgu! Sjhiu*烉怷廗⎛䦣ˤ㙓⬀☐ᷕ䘬忳䬿⃫⎛䦣ᶨỵ炻 MTS! ⽆ cju!42 檀ỵ墄 1!忚Ἦˤ! BTS)Bsjuinfujd!Tijgu!Sjhiu*烉䬿埻⎛䦣ˤBsjuinfujd!Tijgu ẋ堐ᾅ 䔁㬋! 屈嘇㪬ỵ℞Ṿ ỵ䦣≽ἄˤ⚈㬌䦣ỵ⃫䘬忶䦳ᷕㅱᾅ㊩忳䬿⃫䘬䫎嘇ᶵ嬲ˤ! 㙓⬀☐ᷕ䘬忳䬿⃫⎛䦣ᶨỵˤ劍忳䬿⃫䁢㬋㔠炻⇯ cju!42 墄 1ˤ劍忳䬿⃫䁢! 屈㔠炻⇯ cju!42!墄忚 2ˤ! SPS)Spubuf!Sjhiu*烉徜⚰⎛䦣ˤ㙓⬀☐ᷕ䘬忳䬿⃫⎛䦣ᶨỵ炻㚨檀ỵ⃫ 䨢! ↢ỵ⃫᷎䦣ℍ㚨Ỷỵ䦣↢䘬ỵ⃫ˤ! SSY)Spubuf!Sjhiu!fYufoefe*烉⺞Ỡ SPS 䘬徜⚰⎛䦣ˤ㙓⬀☐ᷕ䘬忳䬿 ⃫⎛! 䦣ᶨỵ炻㚨檀ỵ⃫䨢↢ỵ⃫⼴䓐⍇Ἦ DQTS 䘬㕿㧁ỵ⃫ᷕ䘬ῤ⠓ℍˤ! ! ! 第5 頁!
  • 22.
    6/ ⣂㙓⬀☐⭂⛨! 䓐㬌㕡⺷⎗ᶨ㫉⁛怆⸦ᾳ㙓⬀☐ᷕ䘬ῤˤ⃩姙⛐ᶨ㡅㊯Ẍᷕ㚨⣂⁛復27 ᾳ ᶨ凔㙓⬀☐䘬ảỽ⫸普ˤἳ⤪烉! MENJB!!S1-!|S2-!S3-!S4~! <!S1^àS2! !! ! ! ! ! ! !!!!<!S1,5^àS3! !! ! ! ! ! ! !!!<!S1,9^àS4! 娚㊯Ẍ䘬⯦⶜䘬 JB 堐䣢㭷㫉➟埴⬴ᶳ庱0⬀⚆㑵ἄ⼴炻S1 ㊱ Xpse 攟⹎⡆≈炻! ⚈㬌㊯Ẍ⎗⮯忋临姀ㅞ橼䘬ῤ⁛復⇘ S2S4ˤ! ! 7/ ➢⛨⭂⛨! 㬌㕡⺷㗗⮯➢⛨㙓⬀☐ᷕ䘬ℏ⭡冯㊯Ẍᷕ䘬ῷ䦣慷䚠≈炻⼿⇘忳䬿⃫䘬⬀㓦 ỵ⛨ˤ➢⛨⭂⛨䓐㕤⬀⍾➢⸽ỵ⛨旬役䘬姀ㅞ橼ˤἳ⤪烉! MES!S1-!S2-!$9^! ! ! <S2,9^àS1! MES!S1-!S2,S3^! ! ! <S2,S3^àS1! ! ➢⛨⭂⛨⊭㊔⇵䳊⺽␴⼴䳊⺽⭂⛨ˤ! ⇵䳊⺽⭂⛨㊯⮯➢⸽ỵ⛨≈ᶲῷ䦣慷ᷳ⼴䓊䓇䘬ỵ⛨ἄ䁢㚱㓰ỵ⛨ˤἳ⤪烉! MES!S1-!S2-!$9^! ! ! <S2,9^àS1! ! ⼴䳊⺽⭂⛨㊯⮯ᶵⷞ㚱ῷ䦣慷䘬➢⸽ỵ⛨ἄ䁢㚱㓰ỵ⛨ˤ! MES!S1-!S2^-!$9! ! ! <S2^àS1! !! ! ! ! ! ! !!!<S2,9àS2! ! ⎎⢾炻䫎嘇Ⱦ炰ȿ⎗ẍ䓐Ἦἧ㊯Ẍ➟埴⬴⼴㚜㕘➢⸽ỵ⛨ˤἳ⤪烉! MES!S1-!S2-!$9^"!! ! <S2,9^àS1! !! ! ! ! ! ! !!!!<S2,9àS2! ! 8/ ➮䔲⭂⛨! ➮䔲⭂⛨⌛⇑䓐➮䔲㊯㧁炻㊱䈡⭂枮⸷⬀⍾姀ㅞ橼╖⃫炻ἧ䓐 qvti ㊯Ẍ⎹➮! 䔲⮓屯㕁ˤἧ䓐 qpq ㊯Ẍ⽆➮䔲ᷕ嬨㔠㒂ˤ! ➮䔲⎗↮䁢ℑ䧖烉! 怆⡆➮䔲)btdfoejoh!tubdl*炻⌛➮䔲⎹檀ỵ⛨㕡⎹Ỡ⯽烊! 怆㷃➮䔲)eftdfoejoh!tubdl*炻⌛➮䔲⎹Ỷỵ⛨㕡⎹Ỡ⯽烊! ➮䔲㊯㧁㊯⎹㚨⼴⡻ℍ➮䔲䘬㚱㓰屯㕁炻䧙䁢㺧➮䔲)gvmm!tubdl*ˤ➮䔲㊯!!!!! 㧁㊯⎹ᶳᶨᾳ㚱㓰屯㕁⮯天⬀㓦䘬ỵ伖炻䧙䁢䨢➮䔲)fnquz!tubdl*ˤ! ㊱㬌䳬⎰炻⎗䓊䓇 5 䧖栆✳䘬➮䔲烉! 㺧怆⡆烉!!㺧➮䔲炻怆⡆➮䔲! 䨢怆⡆烉!!䨢➮䔲炻怆⡆➮䔲! 㺧怆㷃烉!!㺧➮䔲炻怆㷃➮䔲! 䨢怆㷃烉!!䨢➮䔲炻怆㷃➮䔲! ! 9/ 䚠⮵⭂⛨! !!!㈲ QD ㊯㧁ἄ䁢➢⸽ỵ⛨ˤ妰䬿↢䚖䘬⛘⛨␴䎦埴㊯Ẍỵ⛨ᷳ攻䘬ῷ䦣慷ˤ!!!!! !!!➢⸽ỵ⛨≈ῷ䦣慷⌛⼿⇘㚨䳪䘬㚱㓰ỵ⛨ˤἳ⤪烉! ! 第6 頁!
  • 23.
    CM!TVCS! ! <嶛廱⇘TVCS! Ƀ! ! !!!TVCS! Ƀ! ! ! ! <∗䦳⺷ℍ⎋! NPW!QD-!S25! ! <彼⚆! 3 A R M 指令分類介紹 ⇵朊⶚䞍 BSN ㊯Ẍ⎗↮䁢ℕ⣏栆烉㍍ᶳἮ䁢忁ℕ⣏栆㊯Ẍ忚埴娛䳘䘬妋婒ˤ!! 3.1 記憶體存取指令 2/!MES ␴ TUS烉䓐㕤╖ᶨ xpse ␴䃉䫎嘇ỵ⃫䳬)Votjhofe!Czuf*㗪ˤ! 庱ℍ㙓⬀☐㊯Ẍ)MES*⮯屯㕁⽆姀ㅞ橼庱ℍ⇘㙓⬀☐ᷕˤ⃚⬀㙓⬀☐㊯Ẍ)TUS* ⮯屯㕁⽆㙓⬀☐⬀㓦⇘姀ㅞ橼ᷕˤ⎗䓐㕤 43 ỵ⃫ xpse ㆾ 9 ỵ⃫䃉䫎嘇ỵ⃫䳬ˤ ỵ⃫䳬庱ℍ㚫䓐Ⱦ1ȿ⺞Ỡ军 43 ỵ⃫ˤ! MES ␴ TUS 悥㚱⤪ᶳ 5 䧖⼊⺷烉! l 暞ῷ䦣慷){fsp!pggtfu*! pq|dpoe~|C~|U~!Se炻So^! So 䘬ῤἄ䁢⁛復屯㕁䘬ỵ⛨ˤ! ! l ⇵䳊⺽ῷ䦣)qsf.joefyfe!pggtfu*! pq|dpoe~|C~!Se炻So炻Gmfypggtfu^|"~! ⛐屯㕁⁛復ᷳ⇵炻⮯ῷ䦣慷≈⇘ So ᷕˤ℞䳸㝄ἄ䁢⁛復屯㕁䘬姀ㅞ橼 ỵ⛨ˤ劍ἧ䓐⯦䡤Ⱦ"ȿ炻⇯䳸㝄⮓⚆⇘ So ᷕ炻ᶼ So ᶵ⃩姙㗗 S26ˤ! ! l 䦳⺷䚠⮵ῷ䦣)qsphsbn!sfmbujwf*! pq|dpoe~|C~!Se炻mbcfm! 䦳⺷䚠⮵ῷ䦣㗗⇵䳊⺽⼊⺷䘬⎎ᶨ䧖䇰㛔ˤ⽆ QD 妰䬿ῷ䦣慷炻᷎⮯ QD ἄ䁢 So 䓊䓇⇵䳊⺽㊯Ẍˤᶵ傥ἧ䓐⯦䡤Ⱦ"ȿˤ! ! l ⼴䳊⺽ῷ䦣)qptu.joefyfe!pggtfu*! pq|dpoe~|C~|U~!Se炻So^炻Gmfypggtfu! So 䘬ῤ䓐 ⁛復屯㕁䘬姀ㅞ橼ỵ⛨ˤ⛐屯㕁⁛復⼴炻⮯ῷ䦣慷≈⇘ So! ᷕˤ䳸㝄⮓⚆⇘ SoˤSo ᶵ⃩姙㗗 S26ˤ! ! ℞ᷕ烉! pq! 㑵ἄ䡤炻㊯Ẍ MES ㆾ TUSˤ! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! C! ⎗怠㑯⯦䡤ˤ劍㚱 C炻⇯⁛復 Se 䘬㚨Ỷ㚱㓰ỵ⃫䳬ˤ劍 pq 㗗 MES炻⇯⮯ Se 䘬℞Ṿỵ⃫䳬㶭昌䁢暞ˤ! U! ⎗怠㑯⯦䡤ˤ劍㚱 U炻恋湤⌛ἧ嗽䎮☐㗗⛐䈡㬲㧉⺷ᶳ炻⃚⬀ 䲣䴙ḇ⮯⬀⍾䚳ㆸ嗽䎮☐㗗⛐ἧ䓐侭㧉⺷ᶳˤU ⛐ἧ䓐侭㧉⺷ ᶳ䃉㓰炻ᶵ傥冯⇵䳊⺽ῷ䦣ᶨ崟ἧ䓐 Uˤ! Se! 䓐㕤庱ℍㆾ⃚⬀䘬 BSN 㙓⬀☐ˤ! So! 姀ㅞ橼䘬➢⸽㙓⬀☐ˤ劍㊯Ẍ㗗℟㚱⮓⚆)xsjufcbdl*䘬⇵䳊 ! 第7 頁!
  • 24.
    ⺽ㆾ⼴䳊⺽)⯦䡤䁢Ⱦ"ȿ*炻ㆾἧ䓐⯦䡤 U炻⇯ᶵ⃩姙 So冯 Se 䚠⎴ˤ! Gmfypggtfu! ≈⇘ So ᶲ䘬曰㳣䘬ῷ䦣慷ˤ! Mbcfm! 䦳⺷䚠⮵ῷ䦣忳䬿⺷ˤmbcfm ⽭枰㗗⛐䚖⇵㊯Ẍ䘬㬋屈 5LC 䭬 ⚵ℏˤ! "! ⎗怠⯦䡤ˤ劍㚱Ⱦ"ȿ炻⇯⮯⊭⏓ῷ䦣慷䘬ỵ⛨⮓⚆⇘ Soˤ劍 So 㗗 S26炻⇯ᶵ傥ἧ䓐⯦䡤Ⱦ"ȿˤ! ! Gmfypggtfu 䓐㱽烉! !!!!⇵䳊⺽␴⼴䳊⺽⎗ẍ㗗ẍᶳℑ䧖⼊⺷ᷳᶨ烉! !!!!$fyqs! !!!!|ᶨ~Sn|炻tijgu~! !!!!℞ᷕ烉! ᶨ! ⎗怠屈嘇ˤ劍ⷞ䫎嘇Ⱦᶨȿ炻⇯⽆ So ᷕ㷃⍣ῷ䦣慷ˤ⏎⇯炻 ⮯ῷ䦣慷≈⇘ So ᷕˤ! fyqs! 忳䬿⺷炻⍾ῤ䭬⚵㗗.51:6 ⇘,51:6 䘬㔜㔠ˤ! Sn! ℏ⏓ῷ䦣慷䘬㙓⬀☐ˤSn ᶵ⃩姙㗗 S26ˤ! tijgu! Sn 䘬⎗怠䦣ỵ㕡㱽ˤ⎗ẍ㗗ᶳ↿⼊⺷䘬ảỽᶨ䧖烉! BTS!o!!䬿埻⎛䦣 o ỵ)2=>o=>43*! MTM!o!!怷廗ⶎ䦣 o ỵ⃫)2=>o=>42*! MTS!o!!怷廗⎛䦣 o ỵ⃫)2=>o=>43*! SPS!o!!徜⚰⎛䦣 o ỵ)2=>o=>42*! SSY!!!徜⚰⎛䦣 2 ỵ炻ⷞ㚱⺞Ỡ! ! ἳ⫸烉! MES!!S9炻S1^! ! ! ! 烊S1^à!S9! MESOF!!S3炻S6炻$:71^"!! 烊 ) 㚱 㡅 ẞ ⛘ *! S6,:71^à! S3 烊 S6,:71àS6! TUS!!S6炻$S8^炻$..9! ! 烊S6àS8^炻S8.9àS8! ! 3/ MES ␴ TUS烉䓐㕤╖ᶨ ibmuxpse ␴ⷞ䫎嘇ỵ⃫䳬)Tjhofe!Czuf*㗪ˤ! 庱ℍ㙓⬀☐炻䓐㕤ⷞ䫎嘇䘬 9 ỵ⃫ỵ⃫䳬ˣⷞ䫎嘇␴䃉䫎嘇䘬 27 ỵ⃫ ibmuxpseˤ! ⃚⬀㙓⬀☐炻䓐㕤 27 ỵ⃫ ibmuxpseˤ! ⷞ䫎嘇庱ℍ㗗㊯ⷞ䫎嘇⺞Ỡ军 43 ỵ⃫ˤ䃉䫎嘇 ibmuxpse 庱ℍ㗗㊯䓙暞⺞Ỡ ⇘ 43 ỵ⃫ˤ! 忁ṃ㊯Ẍ㚱 5 䧖⎗傥䘬⼊⺷烉暞ῷ䦣ˣ⇵䳊⺽ῷ䦣ˣ䦳⺷䚠⮵ῷ䦣␴⼴䳊⺽ ῷ䦣ˤẍ⎴㧋䘬枮⸷炻5 䧖⼊⺷䘬⎍㱽䁢烉! pq|dpoe~uzqf!!Se炻So^! pq|dpoe~uzqf!!Se炻So炻pggtfu^|"~! pq|dpoe~uzqf!!Se炻mbcfm! pq|dpoe~uzqf!!Se炻So^炻pggtfu! ! ℞ᷕ烉! ! 第8 頁!
  • 25.
    pq! 㑵ἄ䡤炻㊯Ẍ MESㆾ TUSˤ! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! uzqf! ! ⽭枰㗗ẍᶳ㇨↿䘬℞ᷕᷳᶨ烉! TI! ! ⮵ⷞ䫎嘇 ibmuxpse)⮵ MES*! I!! ⮵䃉䫎嘇 ibmuxpse! TC! ! ⮵ⷞ䫎嘇ỵ⃫䳬)⮵ MES*! 2bcfm! 䦳⺷䚠⮵ῷ䦣忳䬿⺷ˤmbcfm ⽭枰㗗⛐䚖⇵㊯Ẍ䘬.366 军,366 ỵ⃫ 䳬䭬⚵ℏˤ! pggtfu!≈⛐ So ᶲ䘬ῷ䦣慷ˤ! Se! ! 䓐㕤庱ℍㆾ⃚⬀䘬 BSN 㙓⬀☐ˤ! So! 姀ㅞ橼䘬➢⛨㙓⬀☐ˤ劍㊯Ẍ㗗ⷞ㚱⮓⚆)xsjufcbdl*䘬⇵䳊⺽ㆾ ⼴䳊⺽)⯦䡤䁢Ⱦ"ȿ*炻⇯ᶵ⃩姙 So 冯 Se 䚠⎴ˤ! ἳ⫸烉! MESI!!S2炻S1炻$31^! 烊S1,31^àS2炻庱ℍ 27 ỵ ibmuxpse炻䓙暞 ⺞Ỡ⇘ 43 ỵ⃫ˤ! TUSI!!S3炻S1炻S2^"! 烊S1,S2^àS3炻⃚⬀㚨Ỷ䘬㚱㓰 ibmuxpse ⇘ S1,Sm ỵ⛨攳⥳䘬ℑᾳỵ⃫䳬炻ỵ⛨⮓⚆ ⇘ S1ˤ! ! 4/ MES ␴ TUSȹ䓐㕤暁 xpse 㗪ˤ! 庱ℍℑᾳ䚠惘䘬㙓⬀☐炻75 ỵ⃫暁 xpseˤ! ⃚⬀ℑᾳ䚠惘䘬㙓⬀☐炻75 ỵ暁⃫ xpseˤ! 忁ṃ㊯Ẍ㚱 5 䧖⎗傥䘬⼊⺷烉暞ῷ䦣ˣ⇵䳊⺽ῷ䦣ˣ䦳⺷䚠⮵ῷ䦣␴⼴䳊⺽ ῷ䦣ˤẍ⎴㧋䘬枮⸷炻5 䧖⼊⺷䘬⎍㱽䁢烉! pq|dpoe~E!!Se炻So^! pq|dpoe~E!!Se炻So炻pggtfu^|"~! pq|dpoe~E!!Se炻mbcfm! pq|dpoe~E!!Se炻So^炻pggtfu! ! ℞ᷕ烉! pq! 㑵ἄ䡤炻㊯Ẍ MES ㆾ TUSˤ! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! Se! 庱ℍㆾ⃚⬀䘬㙓⬀☐ᷕ䘬ᶨᾳ炻⎎ᶨᾳ㗗 S)e,2*ˤSe ⽭枰㗗„㔠 㙓⬀☐炻ᶼᶵ㗗 S25ˤ! So! 昌朆㊯Ẍ䁢暞ῷ䦣炻ㆾᶵⷞ㚱⮓⚆䘬⇵䳊⺽炻⏎⇯ So ᶵ⃩姙冯 Se ␴ S)e,2*䚠⎴ˤ! Pggtfu! ≈⛐ So ᶲ䘬ῷ䦣慷ˤ! Mbcfm! 䦳⺷䚠⮵ῷ䦣忳䬿⺷ˤmbcfm ⽭枰㗗⛐䚖⇵㊯Ẍ䘬²363 ỵ⃫䳬䭬⚵ ℏˤ! "! ⎗怠⯦䡤ˤ劍㚱Ⱦ"ȿ炻⇯⮯⊭⏓ῷ䦣慷䘬㚨⼴䘬ỵ⛨⮓⚆⇘ Soˤ! ! ἳ⫸烉! MESE!!S7炻S22^! TUSE!!S1炻S:炻.S3^"! ! 第9 頁!
  • 26.
    ! 5/ MEN␴ TUN! 庱ℍ⣂ᾳ㙓⬀☐)MpbE! Nvmujqmf! sfhjtufst*␴⃚⬀⣂ᾳ㙓⬀☐)TUpsf! Nvmujqmf!sfhjtufst*ˤ⎗ẍ⁛復 S1S26 䘬ảỽ䳬⎰ˤ! ! ⎍㱽烉! pq|dpoe~npef!!So|"~炻sfhmjtu|_~! ! ℞ᷕ烉! pq! 㑵ἄ䡤炻㊯Ẍ MEN ㆾ TUNˤ! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! npef! 㗗ᶳ↿ね㱩ᷳᶨ烉! JB! 㭷㫉⁛復⼴ỵ⛨≈ 2! JC! 㭷㫉⁛復⇵ỵ⛨≈ 2! EB! 㭷㫉⁛復⼴ỵ⛨㷃 2! EC! 㭷㫉⁛復⇵ỵ⛨㷃 2! GE! 㺧怆㷃➮䔲! FE! 䨢怆㷃➮䔲! GB! 㺧怆⡆➮䔲! FB! 䨢怆⡆➮䔲! So! ➢⸽㙓⬀☐炻墅㚱⁛復屯㕁䘬⇅⥳ỵ⛨ˤSo ᶵ⃩姙㗗 S26ˤ! "! ⎗怠⯦䡤ˤ劍㚱Ⱦ"ȿ炻⇯㚨⼴䘬ỵ⛨⮓⚆⇘ Soˤ! Sfhmjtu! 庱ℍㆾ⃚⬀䘬㙓⬀☐↿堐炻⊭⏓⛐㊔⻏ᷕˤ⬫ḇ⎗ẍ⊭⏓㙓⬀☐䘬 䭬⚵ˤ劍⊭⏓⣂㕤 2 ᾳ㙓⬀☐ㆾ⊭⏓㙓⬀☐䭬⚵炻⇯⽭枰䓐徿嘇↮ 攳ˤ! _! ⎗怠⯦䡤炻ᶵ⃩姙⛐ἧ䓐侭㧉⺷ㆾ䲣䴙㧉⺷ᶳἧ䓐ˤ⬫㚱ℑᾳ䚖䘬烉! 2/!劍 pq 㗗 MEN ᶼ sfhmjtu ᷕ⊭⏓ QD)S26*炻恋湤昌Ḯ㬋ⷠ䘬⣂㙓 ⬀☐⁛復⢾炻⮯ TQTS ḇ㊟居⇘ DQTS ᷕˤ忁䓐㕤⽆ἳ⢾嗽䎮彼⚆炻 ⛐ἳ⢾㧉⺷ᶳἧ䓐ˤ! 3/!屯㕁⁛ℍㆾ⁛↢䘬㗗ἧ䓐侭㧉⺷䘬㙓⬀☐炻侴ᶵ㗗䚖⇵㧉⺷䘬 㙓⬀☐ˤ! ! ⷞ㚱⮓⚆䘬庱ℍㆾ⃚⬀➢⸽㙓⬀☐烉! ⤪㝄 So ⊭⏓⛐㙓⬀☐↿堐ᷕ炻ᶼ䓐⯦䡤Ⱦ炰ȿ㊯㖶天⮓⚆)xsjufcbdl*炻恋 湤烉! ..!劍 pq 㗗 TUN炻ᶼ So 㗗㙓⬀☐↿堐ᷕ㔠⫿㚨⮷䘬㙓⬀☐炻⇯⮯ So 䘬⇅ ῤᾅ⬀ˤ! ..!So 䘬庱ℍ␴⃚⬀ῤ⇯ᶵ⎗枸㷔ˤ! ! ἳ⫸烉! MENJB!!S9炻|S1炻S3炻S8~! TUNEC!!S2"炻|S4 ᶨ S7炻S22炻S23~! ! 6/ TXQ! ! 第: 頁!
  • 27.
    ⛐㙓⬀☐␴姀ㅞ橼ᷳ攻忚埴屯㕁Ṍ㎃ˤ! ⎗ἧ䓐 TXQ)TXbQ*Ἦ⮎䎦ᾉ嘇慷)tfnbqipsf*ˤ! ⎍㱽烉! TXQ|dpoe~|C~!!Se炻Sn炻So^! !!!℞ᷕ烉! dpoe!⎗怠㑯䘬㡅ẞ䡤ˤ! C! ⎗怠㑯⯦䡤ˤ劍㚱 C炻⇯Ṍ㎃ỵ⃫䳬ˤ⏎⇯Ṍ㎃ 43 ỵ xpseˤ! Se! 屯㕁⽆姀ㅞ橼庱ℍ⇘ Seˤ! Sn!!Sn 䘬ℏ⭡⃚⬀⇘姀ㅞ橼ˤSn ⎗ẍ冯 Se 䚠⎴ˤ⛐忁䧖ね㱩ᶳ炻㙓⬀☐䘬 ℏ⭡冯姀ㅞ橼䘬ℏ⭡忚埴Ṍ㎃ˤ! So!!!So 䘬ℏ⭡㊯⭂天忚埴屯㕁Ṍ㎃䘬姀ㅞ橼䘬ỵ⛨ˤSo ⽭枰冯 Se ␴ Sn ᶵ ⎴ˤ! ! 2.3.2 資料處理指令 2/ 曰㳣䘬䫔Ḵ忳䬿⃫! ⣏⣂㔠 BSN 忂䓐屯㕁嗽䎮㊯Ẍ㚱ᶨᾳ曰㳣䘬䫔Ḵ忳䬿⃫ˤ⛐㭷ȹᾳ㊯Ẍ䘬⎍ 㱽㍷徘ᷕẍȾPqfsboe3ȿ堐䣢ˤ! Pqfsboe3 㚱⤪ᶳℑ䧖⎗傥䘬⼊⺷烉! $jnnfe`9s! Sn!|炻tijgu~! ! ℞ᷕ烉! jnnfe`9s! 䩳⌛ῤ䁢㔠⫿ⷠ㔠䘬忳䬿⺷ˤ! ⎰㱽ⷠ㔠烉! 1yGGˣ1y215ˣ1yGG1ˣ1yGG111ˣ1yGG111111ˣ1yG111111Gˤ! 朆㱽ⷠ㔠烉! 1y212 ˣ 1y213 ˣ 1yGGm ˣ 1yGG15 ˣ 1YGG114 ˣ 1yGGGGGGGG ˣ 1yG111112Gˤ! Sn! ⃚⬀䫔Ḵ忳䬿⃫屯㕁䘬 BSN 㙓⬀☐ˤ! Tijgu! Sn 䘬⎗怠㑯䦣ỵ㕡㱽ˤ⎗ẍ㗗ẍᶳ㕡㱽䘬ảỽᶨ䧖烉! BTS!o! 䬿埻⎛䦣 o ỵ)2=>o=>43*! MTM!o! 怷廗ⶎ䦣 o ỵ⃫)2=>o=>42*! MTS!o! 怷廗⎛䦣 o ỵ⃫)2=>o=>43*! SPS!o! 徜⚰⎛䦣 o ỵ)2=>o=>42*! SSY! ⷞ㚱⺞Ỡ䘬徜⚰⎛䦣 2 ỵ! uzqf!St! ℞ᷕ烉! uzqd! BTSˣMTMˣMTS ␴ SPS ᷕ䘬ᶨ䧖ˤ! St! ㍸ὃ䦣ỵ慷䘬 BSN 㙓⬀☐炻ἧ䓐㚨Ỷ㚱㓰 ỵ⃫䳬ˤ! ! ⛐㊯Ẍᷕ䦣ỵ⃫㑵ἄ䘬䳸㝄䓐  pqfsboe3炻Ữ Sn 㛔幓ᶵ嬲ˤ! ! 3/ BEEˣTVCˣSTCˣBEDˣTCD ␴ STD! ≈ˣ㷃ˣ⍵㷃炻≈ᶲ!ⷞㆾᶵⷞ忚ỵˤ! ! 第21 頁!
  • 28.
    ⎍㱽烉! pq!|dpoe~|T~!!Se炻So炻Pqfsboe3! ℞ᷕ烉! pq! 㑵ἄ䡤ˤBEEˣTVCˣSTCˣBEDˣTCD ␴ STD ℞ᷕȹᾳˤ! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! T! ⎗怠㑯䘬⯦䡤ˤ劍㊯⭂ T炻⇯㟡㒂㑵ἄ䳸㝄㚜㕘㡅ẞ䡤㧁娴)Oˣ[ˣ D ␴ W*ˤ! Se! BSN 䳸㝄㙓⬀☐ˤ! So! ᾅ⬀䫔ᶨ忳䬿⃫䘬 BSN 㙓⬀☐ˤ! Pqfsboe3! 䫔Ḵ忳䬿⃫ˤ! ! 䓐㱽烉! 炽BEE)BEE*㊯Ẍ䓐㕤⮯ So ␴ Pqfsboe3 䘬ῤ䚠≈ˤ! 炽TVC)TVCusbdu*㊯Ẍ䓐㕤⽆ So 䘬ῤᷕ㷃⍣ Pqfsboe3 䘬ῤˤ! 炽STC)Sfwfstf!TvCusbdu*㊯Ẍ䓐㕤⽆ Pqfsboe3 䘬ῤᷕ㷃⍣ So 䘬ῤˤ䓙㕤 Pqfsboe3 䘬⎗怠䭬⚵⮔炻㇨ẍ忁㡅㊯Ẍ⼰㚱䓐ˤ! 炽BED)BEe!xjui!Dbssz*㊯Ẍ⮯ So ␴ Pqfsboe3 ᷕ䘬ῤ䚠≈炻᷎ⷞ㚱忚ỵ⃫ 㧁娴ˤ! 炽TCD)TvCusbdu!xjui!Dbssz*㊯Ẍ⽆ So 䘬ῤᷕ㷃⍣ Pqfsboe3 䘬ῤˤ劍忚ỵ ⃫㧁娴㗗㶭昌䁢暞-⇯䳸㝄㷃 mˤ! 炽STD)Sfwfstf!Tvcusbdu!xjui!Dbssz*㊯Ẍ⽆ Pqfsboe3 䘬ῤᷕ㷃⍣ So 䘬ῤˤ 劍忚ỵ⃫㧁娴㗗㶭昌䁢暞炻⇯䳸㝄㷃 2ˤ! 炽BEDˣTCD ␴ STD 䓐㕤⣂ᾳ⫿䘬䬿埻忳䬿ˤ! 炽劍㊯⭂ T炻恋湤忁ṃ㊯Ẍ㟡㒂䳸㝄㚜㕘㧁娴 Oˣ[ˣD ␴ Wˤ! ! ἳ⫸烉! BEE!!S3炻S2炻S4! TVCT!!S9炻S7炻$351! 烊㟡㒂䳸㝄姕伖㧁娴! STC!!S5炻S5炻$2391! 烊2391.S5! BEDIJ!!S22炻S1炻S4! 烊⎒㚱㧁娴 D 伖ỵ⃫ᶼ㧁娴 [ 㶭昌䁢暞 㗪ㇵ➟埴! STDMFT!!S1炻S6炻S1炻MTM!S5! 烊㚱㡅ẞ➟埴炻姕伖㧁娴! ! 4/ BOEˣPSSˣFPS ␴ CJD! 怷廗忳䬿..Ⱦ冯ȿˣȾㆾȿˣȾ䔘ㆾȿ␴Ⱦỵ⃫㶭昌䁢暞ȿˤ! ⎍㱽烉! pq|dpoe~|T~!!Se炻So炻Pqfsboe3! ! ℞ᷕ! pq! 㑵ἄ䡤ˤBOEˣPSSˣFPS ␴ CJD ℞ᷕȹᾳˤ! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! T! ⎗怠㑯䘬⯦䡤ˤ劍㊯⭂ T炻⇯㟡㒂㑵ἄ䳸㝄㚜㕘㡅ẞ䡤㧁娴)Oˣ[ˣ D ␴ W*ˤ! Se! BSN 䳸㝄㙓⬀☐ˤ! ! 第22 頁!
  • 29.
    So! ᾅ⬀䫔ᶨ忳䬿⃫䘬 BSN㙓⬀☐ˤ! Pqfsboe3! 䫔Ḵ忳䬿⃫ˤ! ! BOEˣFPS ␴ PSS ㊯Ẍ↮⇍⬴ㆸ怷廗忳䬿⫸Ⱦ冯)BOE*ȿˣȾ䔘ㆾ)Fydmvtjwf! PS*ȿ␴Ⱦㆾ)PS*ȿ㑵ἄ炻忳䬿⃫㗗 So ␴ Pqfsboe3 䘬ῤˤ! CJD)CJu!Dmfbs*㚫⮯ So 冯䫔ᶱ⍫㔠䘬墄㔠ἄ BOE 忳䬿炻䃞⼴⮯䳸㝄⬀ℍ Seˤ ℞㓰㝄⯙⁷㗗⮯ Se ᷕ冯䚠⮵ㅱ䫔ᶱ⍫㔠墉䁢 2 䘬ỵ⃫㶭昌䁢暞ˤ! 劍㊯⭂ T炻⇯忁ṃ㊯Ẍ⮯烉荛㟡㒂䳸㝄㚜㕘㧁娴 O ␴ [烊荜⛐妰䬿 Pqfsboe3 㗪㚜㕘㧁娴 D烊荝ᶵ⼙枧㧁娴 Wˤ! ἳ⫸烉! BOE!!S:炻S3炻$1yGG11! PSSFR!!S3炻S1炻S6! FPST!!S1炻S1炻S4炻SPS!S7! CJDOFT!!S9炻S21炻S1炻SSY! ! 5/ NPW ␴ NWO! ⁛復␴朆⁛復ˤ! ⎍㱽烉! pq|dpoe~|T~!!Se炻Pqfsboe3! ℞ᷕ烉! pq! 㑵ἄ䡤ˤNPW ␴ NWO ᷕȹᾳˤ! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! T! ⎗怠㑯䘬⯦䡤ˤ劍㊯⭂ T炻⇯㟡㒂㑵ἄ䳸㝄㚜㕘㡅ẞ䡤㧁娴)Oˣ[ˣ D ␴ W*ˤ! Se! BSN 䳸㝄㙓⬀☐ˤ! Pqfsboe3! 䫔Ḵ忳䬿⃫ˤ! ! NPW)NPWf*㊯Ẍ⮯ Pqfsboe3 䘬ῤ㊟居⇘ SeˤNWO)NpWf!Opu*㊯Ẍ⮵ Pqfsboe3 䘬ῤ忚埴㊱ỵ⃫怷廗朆㑵ἄ炻䃞⼴⮯䳸㝄復⇘ Seˤ! !! ἳ⫸烉! !!NPW!!S3炻S2! !!NPW!!S2炻$1y234567! !!NPWT!!S1炻S1炻BTS!S4! ! 6/ DNQ ␴ DNO! 㭼庫␴⍵嘇㭼庫ˤ! ⎍㱽烉! pq|dpoe~!!So炻Pqfsboe3! ! ℞ᷕ烉! pq! 㑵ἄ䡤ˤDNQ ␴ DNO ᷕȹᾳˤ! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! So! ᾅ⬀䫔ᶨ忳䬿⃫䘬 BSN 㙓⬀☐ˤ! ! 第23 頁!
  • 30.
    Pqfsboe3! 䫔Ḵ忳䬿⃫ˤ! ! ㊯Ẍ⮯㙓⬀☐䘬ῤ冯 Pqfsboe3 忚埴㭼庫ˤ⬫Ᾱ㟡㒂䳸㝄㚜㕘㡅ẞ䡤㧁娴炻 Ữ䳸㝄ᶵ㓦⇘ảỽ㙓⬀☐ᷕˤ! DNQ)DpNQbsf*㊯Ẍ⽆ So 䘬ῤᷕ㷃⍣ Pqfsboe3 䘬ῤˤ昌⮯䳸㝄᷇㡬⢾炻DNQ ㊯Ẍ⎴ TVCT ㊯Ẍᶨ㧋ˤ! DNO)DpNqbsf!Ofhbujwf*㊯Ẍ⮯ Pqfsboe3 䘬ῤ≈⇘ So 䘬ῤᷕˤ昌⮯䳸㝄᷇ 㡬⢾炻DNO ㊯Ẍ䘬䓐㱽⎴ BEET ᶨ㧋ˤ! DNQ ␴ DNO ㊯Ẍ㟡㒂䳸㝄㚜㕘㧁娴 Oˣ[ˣD ␴ Wˤ! ! ἳ⫸烉! DNQ!!S3炻S4! DNO!!S1炻$234! DNQHU!!S24炻S8炻MTM!$3! ! 7/ UTU ␴ UFR! 㷔娎␴㷔娎䚠䫱ˤ! ⎍㱽烉! pq|dpoe~!!So炻Pqfsboe3! ! ℞ᷕ烉! pq! 㑵ἄ䡤ˤUTU ␴ UFR ᷕȹᾳˤ! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! So! ᾅ⬀䫔ᶨ忳䬿⃫䘬 BSN 㙓⬀☐ˤ! Pqfsboe3! 䫔Ḵ忳䬿⃫ˤ! ! 忁ṃ㊯Ẍὅ㒂 Pqfsboe3 㷔娎㙓⬀☐ᷕ䘬ῤˤ⬫Ᾱ㟡㒂䳸㝄㚜㕘㡅ẞ䡤㧁娴炻 Ữ䳸㝄ᶵ㓦⇘ảỽ㙓⬀☐ᷕˤ! UTU)UfTU*㊯Ẍ⮵ So 䘬ῤ␴ Pqfsboe3 䘬ῤ忚埴ȾBOEȿ㑵ἄˤ昌䳸㝄᷇㡬 ⢾炻≇傥⎴ BOET ㊯Ẍᶨ㧋ˤ! UFR)Uftu!FRvjwbmfodf*㊯Ẍ⮵ So 䘬ῤ␴ Pqfsboe3 䘬ῤ忚埴ȾFPSȿ㑵ἄˤ 昌䳸㝄᷇㡬⢾炻℞≇傥⎴ FPST ㊯Ẍᶨ㧋ˤ! UTU ␴ UFR ㊯Ẍ㟡㒂䳸㝄㚜㕘㧁娴 Oˣ[ˣD ␴ Wˤ! ! ἳ⫸烉! UTU!!S1炻$1y4G9! UFRFR!!S21炻S:! UTUOF!!Sm炻S6炻BTS!Sm! ! 8/ DM[! ⇵⮶暞妰㔠ˤ! ⎍㱽烉! DM[|dpoe~!!Se炻Sn! ! ! 第24 頁!
  • 31.
    ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! Se! BSN 䳸㝄㙓⬀☐炻Se ᶵ⃩姙㗗 S26ˤ! Sn! 忳䬿⃫㙓⬀☐ˤ! ! DM[)Dpvou!Mfbejoh![fspt*㊯Ẍ⮵ Sn ᷕ㔠ῤ䘬⇵⮶暞)2fbejoh!{fspt*䘬ᾳ 㔠忚埴妰㔠炻䳸㝄㓦⇘ Se ᷕˤ劍⍇⥳㙓⬀☐ℐ䁢 1炻⇯䳸㝄䁢 43ˤ劍 cju42^ 䁢 m炻⇯䳸㝄䁢 1ˤ! 忁㡅㊯Ẍᶵ⼙枧㡅ẞ䡤㧁娴ˤ! ! ἳ⫸烉! DM[!!S5炻S:! DM[OF!!S3炻S4! ! 9/ NVM ␴ NMB! Ḁ㱽␴Ḁ≈ 43 ỵØ43 ỵ炻䳸㝄䁢Ỷ 43 ỵ⃫ˤ! ⎍㱽烉! NVM|dpoe~|T~!!Se炻Sn炻St! NMB|dpoe~|T~!!Se炻Sn炻St炻So! ! ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! T! ⎗怠㑯⯦䡤ˤ劍㊯⭂ T炻⇯㟡㒂㑵ἄ䳸㝄㚜㕘㡅ẞ䡤㧁娴)Oˣ [ˣD ␴ W*ˤ! Se! 䳸㝄㙓⬀☐ˤ! SnˣStˣSo! 忳䬿⃫㙓⬀☐ˤ! ! S26 ᶵ傥䓐  SeˣSnˣSt ㆾ SoˤSe ᶵ傥冯 Sn 䚠⎴ˤ! NVM)NVMujqmz*㊯Ẍ⮯ Sn ␴ St ᷕ䘬ῤ䚠Ḁ炻᷎⮯㚨Ỷ㚱㓰䘬 43 ỵ⃫䳸㝄㓦 ⇘ Se ᷕˤ! NMB)NvMujqmz!Bddvnvmbuf*㊯Ẍ⮯ Sn ␴ St ᷕ䘬ῤ䚠Ḁ炻ℵ≈ᶲ So 䘬ῤ炻᷎ ⮯㚨Ỷ㚱㓰䘬 43 ỵ⃫䳸㝄㓦⇘ Se ᷕˤ! !劍㊯⭂ T炻⇯忁ṃ㊯Ẍ⮯烉荛㟡㒂䳸㝄㚜㕘㧁娴 O ␴ [烊荜ᶵ⼙枧㧁娴 W烊 荝⛐ BSNw5! !!⍲ẍ⇵䇰㛔ᷕ㧁娴 D ᶵ⎗月烊荞⛐ BSNw6 ⍲ẍ⼴䇰㛔ᷕᶵ⼙枧㧁娴 Dˤ! ! !!ἳ⫸烉! !!NVM!!S21炻S3炻S2! !!NMB!!S21炻S3炻Sm炻S6! !!NVMT!!S21炻S3炻S2! !!NMBWDT!!S9炻S7炻S4炻S9! ! :/ VNVMMˣVNMBMˣTNVMM ␴ TNMBM! 䃉䫎嘇␴ⷞ䫎嘇攟㔜㔠Ḁ㱽␴Ḁ≈)43 ỵØ43 ỵ炻≈㱽ㆾ䳸㝄䁢 75 ỵ⃫*ˤ! ! 第25 頁!
  • 32.
    ⎍㱽烉! pq|dpoe~|T~!!SeMp炻SeIj炻Sn炻St! ! ℞ᷕ烉! pq! 㑵ἄ䡤ˤVNVMMˣVNMBMˣTNVMM ␴ TNMBM ᷕȹᾳˤ! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! T! ⎗怠㑯䘬⯦䡤ˤ劍㊯⭂ T炻⇯㟡㒂㑵ἄ䳸㝄㚜㕘㡅ẞ䡤㧁 娴)Oˣ[ˣD ␴ W*ˤ! SeMp炻SeIj! BSN 䳸㝄㙓⬀☐ˤ⮵㕤 VNMBM ␴ TNMBM炻忁ℑᾳ㙓⬀☐䓐㕤 ᾅ⬀≈㱽ῤˤ! Sn炻St! 忳䬿⃫㙓⬀☐ˤ! ! S26 ᶵ傥䓐㕤 SeMpˣSeIjˣSn ㆾ StˤSeMpˣSeIj ␴ Sn ⽭枰㗗ᶵ⎴䘬㙓⬀☐ˤ! VNVMM)Votjhofe!Mpoh!NVMujqmz*㊯Ẍ⮯ Sn ␴ St ᷕ䘬ῤ妋慳䁢䃉䫎嘇㔜㔠ˤ 娚㊯Ẍ⮯忁ℑᾳ㔜㔠䚠Ḁ炻᷎⮯䳸㝄䘬㚨Ỷ㚱㓰 43 ỵ⃫㓦⛐ SeMp ᷕ炻㚨檀㚱㓰 43 ỵ⃫㓦⛐ SeIj ᷕˤ! VNMBM)Votjhofe!Mpoh!NvMujqmz!Bddvnvmbuf*㊯Ẍ⮯ Sn ␴ St ᷕ䘬ῤ妋慳䁢 䃉䫎嘇㔜㔠ˤ娚㊯Ẍ⮯忁ℑᾳ㔜㔠䚠Ḁ炻᷎⮯ 75 ỵ⃫䳸㝄≈⇘ SeIj ␴ SeMp ᷕ 䘬 75 ỵ⃫䃉䫎嘇㔜㔠ᶲˤ! TNVMM)Tjhofe!Mpoh!NVMujqmz*㊯Ẍ⮯ Sn ␴ St ᷕ䘬ῤ妋慳䁢ⷞ䫎嘇䘬墄㔠 㔜㔠ˤ娚㊯Ẍ⮯忁ℑᾳ㔜㔠䚠Ḁ炻᷎⮯䳸㝄䘬㚨Ỷ㚱㓰 43 ỵ⃫㓦⛐ SeMp ᷕ炻⮯ 㚨檀㚱㓰 43 ⃫ỵ㓦⛐ SeIj ᷕˤ! TNMBM)Tjhofe!Mpoh!NvMujqmz!Bddvnvmbuf*㊯Ẍ⮯ Sn ␴ St ᷕ䘬ῤ妋慳䁢ⷞ 䫎嘇䘬墄㔠㔜㔠ˤ娚㊯Ẍ⮯忁ℑᾳ㔜㔠䚠Ḁ炻᷎⮯ 75 ỵ⃫䳸㝄≈⇘ SeIj ␴ SeMp ᷕ䘬 75 ỵ⃫ⷞ䫎嘇墄㔠㔜㔠ᶲˤ! 劍㊯⭂ T炻⇯忁ṃ㊯Ẍ⮯烉荛㟡㒂䳸㝄㚜㕘㧁娴 O ␴ [烊荜⛐ BSNw5 ⍲ẍ⇵ 䇰㛔ᷕ㧁娴 D ᶵ⎗月烊荝⛐ BSNw6 ⍲ẍ⼴䇰㛔ᷕᶵ⼙枧㧁娴 D ㆾ Wˤ! ! ἳ⫸烉! VNVMM!!S1炻S5炻S6炻S7! VNMBMT!!S5炻S6炻S4炻S9! TNMBMMFT!!S9炻S:炻S8炻S7! TNVMMOF!!S1炻Sm炻S:炻S1! ! 21/ TNVMyz! ⷞ㚱䫎嘇Ḁ㱽)27 ỵØ27 ỵ炻䳸㝄䁢 43 ỵ⃫*ˤ! ⎍㱽烉! TNVM烋y烍烋z烍|dpoe~!!Se炻Sn炻St! ℞ᷕ烉! 烋y烍! C ㆾ UˤC シ␛叿ἧ䓐 Sn 䘬Ỷ昶)cju26;1^*炻U シ␛叿ἧ䓐 Sn 䘬檀昶)cju42;27^*ˤ! 烋z烍! C ㆾ UˤC シ␛叿ἧ䓐 St 䘬Ỷ昶)cju26;1^*炻U シ␛叿ἧ䓐 St 䘬檀昶)cju42;27^*ˤ! Se! 䳸㝄㙓⬀☐ˤ! ! 第26 頁!
  • 33.
    Sn炻St! Ḁ㔠㙓⬀☐ˤ! ! S26 ᶵ傥䓐㕤 SeˣSn ␴ StˤSeˣSn ␴ St ⎗䓐䚠⎴䘬㙓⬀☐ˤ! TNVMyz)Tjhofe!NVMujqmz*㊯Ẍ䓐ẍ⮯ Sn ␴ St ᷕ⎬怠㑯ᶨ⋲䘬 27 ỵ⃫ⷞ㚱 䫎嘇㔜㔠䚠Ḁ炻⮯ 43 ỵ⃫䳸㝄㓦⛐ Se ᷕˤ! 忁㡅㊯Ẍᶵ⼙枧ảỽ㡅ẞ䡤㧁娴ˤ! ! ἳ⫸烉! TNVMUCFR!!S9炻S8炻S:! ! 22/ TNMByz! ⷞ䫎嘇Ḁ≈)27 ỵ⃫Ø27 ỵ炻≈㱽䁢 43 ỵ⃫*ˤ! ⎍㱽烉! TNMB烋y烍烋z烍|dpoe~!!Se炻Sn炻St炻So! ℞ᷕ烉! 烋y烍! C ㆾ UˤC シ␛叿ἧ䓐 Sn 䘬Ỷ昶)cju26;1^*炻U シ␛叿ἧ䓐 Sn 䘬檀昶)cju42;27^*ˤ! 烋z烍! C ㆾ UˤC シ␛叿ἧ䓐 St 䘬Ỷ昶)cju26;1^*炻U シ␛叿ἧ䓐 St 䘬檀昶)cju42;27^*ˤ! Se! 䳸㝄㙓⬀☐ˤ! Sn炻St! Ḁ㔠㙓⬀☐ˤ! So! ≈㔠㙓⬀☐ˤ! ! S26 ᶵ傥䓐  SeˣSnˣSt ㆾ SoˤSeˣSnˣSt ␴ So ⎗䓐䚠⎴䘬㙓⬀☐ˤ! TNMByz)Tjhofe!NvMujqmz!Bddvnvmbuf*㊯Ẍ䓐ẍ⮯ Sn ␴ St ᷕ⎬怠㑯ᶨ⋲䘬 27 ỵ⃫ⷞ䫎嘇㔜㔠䚠Ḁ炻⮯ 43 ỵ⃫䳸㝄≈ᶲ So ᷕ䘬 43 ỵῤ炻㚨䳪䳸㝄㓦⛐ Se ᷕˤ! 忁㡅㊯Ẍᶵ㚫㶭昌㧁娴 Rˤ天㶭昌㧁娴 R炻枰ἧ䓐 NTS ㊯Ẍˤʉ! ! ἳ⫸烉! TNMBUU!!S9炻S22炻S1炻S9! TNMBCCOF!!S1炻S3炻Sm炻S21! ! 23/ NVMXz! ⷞ䫎嘇Ḁ)43 ỵ⃫Ø43 ỵ炻䳸㝄䁢檀 43 ỵ*ˤ! ⎍㱽烉! TNVMX烋z烍|dpoe~!!Se炻Sn炻St! ! ℞ᷕ烉! 烋z烍! C ㆾ UˤC シ␛叿ἧ䓐 St 䘬Ỷ昶)cju26;1^*炻U シ␛叿ἧ䓐 St 䘬檀昶)cju42;27^*ˤ! Se! 䳸㝄㙓⬀☐ˤ! Sn炻St! Ḁ㔠㙓⬀☐ˤ! ! ! 第27 頁!
  • 34.
    S26 ᶵ傥䓐  SeˣSnˣㆾSt 䘬ảỽᶨᾳˤảỽ SeˣSn ㆾ St 悥⎗䓐䚠⎴䘬 㙓⬀☐ˤ! TNVMXz)Tjhofe!NVMujqmz*㊯Ẍ䓐ẍ⮯ St ᷕ怠㑯ᶨ⋲䘬ⷞ㚱䫎嘇㔜㔠冯 Sn 䘬ⷞ㚱䫎嘇㔜㔠䚠Ḁ炻⮯ 59 ỵ⃫䳸㝄䘬檀 43 ỵ⃫㓦⛐ Se ᷕˤ! ! ἳ⫸烉! TNVMXC!!S3炻S5炻S8! TNVMXUWT!!S1炻S1炻S:! ! 24/!TNMBXz! ⷞ㚱䫎嘇Ḁ≈)43 ỵ⃫Ø27 ỵ炻䓐檀 43 ỵ⃫忚埴≈㱽*ˤ! ⎍㱽烉! TNMBX烋z烍|dpoe~!!Se炻Sn炻St炻So! ! ℞ᷕ烉! 烋z烍! C ㆾ UˤC シ␛叿ἧ䓐 St 䘬Ỷ昶)cju26;1^*炻U シ␛叿ἧ䓐 St 䘬檀昶)cju42;27^*ˤ! Se! 䳸㝄㙓⬀☐ˤ! Sn炻St! Ḁ㔠㙓⬀☐ˤ! So! ≈㔠㙓⬀☐ˤ! ! S26 ᶵ傥䓐  SeˣSnˣSt ㆾ So 䘬ảỽᶨᾳˤảỽ SeˣSnˣSt ㆾ So ⎗䓐䚠 ⎴䘬㙓⬀☐ˤ! TNMBXz)Tjhofe!NvMujqmz!Bddvnvmbuf*㊯Ẍ䓐ẍ⮯ St ᷕ怠㑯ᶨ⋲䘬ⷞ㚱䫎 嘇㔜㔠冯 Sn ᷕ䘬ⷞ㚱䫎嘇㔜㔠䚠Ḁ炻ℵ⮯ 43 ỵ䳸㝄≈⇘ So ᷕ䘬 43 ỵῤᶲ炻㚨 䳪䳸㝄㓦⛐ Se ᷕˤ! 忁㡅㊯Ẍᶵ⼙枧㧁娴 Oˣ[ˣD ㆾ Wˤ! 劍≈㱽↢䎦㹊↢炻⇯伖ỵ⃫㧁娴 Rˤἧ䓐 NST ㊯ẌἮ嬨㧁娴 R 䘬䉨ンˤ! 忁㡅㊯Ẍᶵ㚫㶭昌 R 㧁娴ˤ天㶭昌 R 㧁娴炻枰ἧ䓐 NTS ㊯Ẍˤ! ! ἳ⫸烉! TNMBXC!!S3炻S5炻S8炻Sm! TNMBXUWT!!S1炻S1炻S:炻S3! ! 25/ TNMBMyz! ⷞ㚱䫎嘇Ḁ≈)27 ỵ⃫Ø27 ỵ炻≈㱽䁢 75 ỵ*ˤ! ⎍㱽烉! TNMBM烋y烍烋z烍|dpoe~!!SeMp炻SeIj炻Sn炻St! ℞ᷕ烉! 烋y烍! C ㆾ UˤC シ␛叿ἧ䓐 Sn 䘬Ỷ昶)cju26;1^*炻U シ␛叿ἧ 䓐 Sn 䘬檀昶)cju42;27^*ˤ! 烋z烍! C ㆾ UˤC シ␛叿ἧ䓐 St 䘬Ỷ昶)cju26;1^*炻U シ␛叿ἧ 䓐 St 䘬檀昶)cju42;27^*ˤ! SeIj炻SeMp! 䳸㝄㙓⬀☐ˤ⬫Ᾱḇᾅ⬀ bee.jo ῤˤ! ! 第28 頁!
  • 35.
    Sn炻St! Ḁ㔠㙓⬀☐ˤ! ! TNMBMyz)Tjhofe!NvMujqmz!Bddvnvmbuf*㊯Ẍ䓐ẍ⮯ Sn ␴ St ᷕ⎬怠㑯ᶨ⋲ 䘬ⷞ㚱䫎嘇㔜㔠䚠Ḁ炻ℵ⮯ 43 ỵ䳸㝄≈⇘ SeIj ␴ SeMp ᷕ䘬 75 ỵ⛨ᶲˤ! 忁㡅㊯Ẍᶵ⼙枧ảỽ㧁娴ˤ! 忁㡅㊯Ẍᶵ㚫⺽崟ἳ⢾ˤ劍➟埴忁㡅㊯Ẍ㗪䘤䓇㹊↢炻⇯䳸㝄䑘丆)xsbqt! spvoe*侴ᶵ䘤↢ảỽ嬎⏲ˤ! ! ἳ⫸烉! TNMBMUC!!S3炻S4炻S8炻S2! TNMBMCUWT!!S1炻Sm炻S:炻S3! ! 26/ RBEEˣRTVCˣREBEE ␴ RETVC! 梥␴≈ˣ梥␴㷃ˣ梥␴Ḁ 3 ≈!␴!梥␴Ḁ 3 㷃ˤ! ⎍㱽! pq|dpoe~!!Se炻Sn炻So! ! ℞ᷕ烉! Se! 䳸㝄㙓⬀☐ˤ! SnˣSo! 忳䬿⃫㙓⬀☐ˤ! !! RBEE)tbuvsbujoh!BEE*㊯Ẍ⮯ Sn ␴ So 䘬ῤ䚠≈ˤ! RTVC)tbuvsbujoh!TVCusbdu*㊯Ẍ⽆ Sn 䘬ῤᷕ㷃⍣ So 䘬ῤˤ! REBEE)tbuvsbujoh!Epvcmf!boe!BEE*㊯Ẍ妰䬿 TBU)Sn,TBU)So+3**ˤ梥␴⎗ 䘤䓇⛐≈᾵㑵ἄˣ≈㱽ᶲ炻ㆾℑ䧖ね㱩ᶳ⎴㗪䘤䓇ˤ劍梥␴䘤䓇⛐≈᾵㑵ἄᶲ炻 ⇯㧁娴 R 伖ỵ⃫炻Ữ㚨⼴䳸㝄㗗ᶵ梥␴䘬ˤ! RETVC)tbuvsbujoh!Epvcmf!boe!TVCusbdu*㊯Ẍ妰䬿 TBU)Sn.TBU)So+3**ˤ梥 ␴⎗䘤䓇⛐≈᾵㑵ἄˣ≈㱽ᶲ炻ㆾℑ䧖ね㱩ᶳ⎴㗪䘤䓇ˤ劍梥␴䘤䓇⛐≈᾵㑵 ἄᶲ炻⇯㧁娴 R 伖ỵ⃫炻Ữ㚨⼴䳸㝄㗗ᶵ梥␴䘬ˤ! 忁ṃ㊯Ẍ㈲㇨㚱ῤ䚳 ⷞ㚱䫎嘇䘬墄㔠㔜㔠ˤ! 忁ṃ㊯Ẍᶵ⼙枧㧁娴 Oˣ[ˣD ␴ Wˤ劍↢䎦梥␴炻⇯伖ỵ⃫㧁娴 Rˤἧ䓐 NST ㊯ẌἮ嬨㧁娴 R 䘬䉨ンˤ! ⌛ἧ㗗梥␴ᶵ↢䎦炻忁ṃ㊯Ẍḇ⽆ᶵ㶭昌 R 㧁娴ˤἧ䓐 NTS ㊯Ẍ㶭昌 R 㧁娴ˤ! ! ἳ⫸烉! RBEE!!S1炻Sm炻S:! RETVCMU!!S:炻S1炻Sm! ! 3.3 跳轉指令 2/ C ␴ CM! 嶛廱␴ⷞ㚱捰䳸嶛廱ˤ! ⎍㱽烉! C|dpoe~!!mbcfm! ! 第29 頁!
  • 36.
    CM|dpoe~!!mbcfm! ! ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! 2bcfm! 䦳⺷䚠⮵ῷ䦣忳䬿⺷ˤ! ! C)Csbodi*㊯Ẍ⺽崟嗽䎮☐廱䦣⇘ 2bcfmˤ! CM)Csbodi!xjui!Mjol*㊯Ẍ⮯ᶳᶨ㡅㊯Ẍ䘬ỵ⛨㊟居⇘ S25)捰䳸㙓⬀☐*炻 ᷎廱䦣⇘ 2bcfmˤ! 㨇☐䳂䘬 C ␴ CM ㊯Ẍ旸⇞⛐䚖⇵㊯Ẍ䘬²43Nc 䭬⚵ℏˤỮ㗗炻⌛ἧ mbcfm 崭 ↢Ḯ娚䭬⚵炻ḇ⎗ẍἧ䓐忁ṃ㊯Ẍˤ! ! ἳ⫸烉! C!!MppqB! CMF!!oh,9! !! 3/ CY! 嶛廱᷎⎗怠㑯⛘Ṍ㎃㊯Ẍ普ˤ! ⎍㱽烉! CY|dpoe~!!Sn! ! ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! Sn! ⏓㚱廱䦣ỵ⛨䘬㙓⬀☐ˤSn 䘬 cju1^ᶵ䓐Ἦἄ䁢⛘⛨䘬ᶨ悐↮ˤ劍 Sn 䘬 cju1^䁢 m炻⇯㊯Ẍ⮯ DQTS ᷕ䘬㧁娴 U 伖ỵ⃫炻ᶼ⮯䚖㧁ỵ⛨ 䘬ẋ䡤妋慳䁢 Uivnc ẋ䡤ˤ劍 Sn 䘬 cju1^䁢 1炻⇯ cju2^⯙ᶵ傥䁢 mˤ! ! ➟埴 CY)Csbodi!boe!pqujpobmmz!fYdibohf*㊯Ẍ⮯⺽崟嗽䎮☐廱䦣⇘ Sn ᷕ 䘬ỵ⛨ˤ劍 Sn 䘬 cju1^䁢 2炻⇯㊯Ẍ普嬲㎃⇘ Uivncˤ! ! ἳ⫸烉! CY!!S8! CYWT!!S1! ! 4/ CMY! ⷞ㚱捰䳸嶛廱᷎⎗怠⛘Ṍ㎃㊯Ẍ普ˤ忁㡅㊯Ẍ㚱⤪ᶳ 3 䧖⼊⺷烉! 2/!ⷞ㚱捰䳸䃉㡅ẞ廱䦣⇘䦳⺷䚠⮵ῷ䦣ỵ⛨ˤ! 3/!ⷞ㚱捰䳸㚱㡅ẞ廱䦣⇘㙓⬀☐ᷕ䘬䳽⮵ỵ⛨ˤ! ⎍㱽烉! CMY|dpoe~!!Sn! CMY!!mbcfm! ! ℞ᷕ烉! ! 第2: 頁!
  • 37.
    dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! Sn!⏓㚱廱䦣ỵ⛨䘬㙓⬀☐ˤSn 䘬 cju1^ᶵ䓐Ἦἄ䁢⛘⛨䘬ᶨ悐↮ˤ 劍 Sn 䘬 cju1^䁢 2炻⇯㊯Ẍ⮯ DQTS ᷕ䘬㧁娴 U 伖ỵ⃫炻ᶼ⮯䚖㧁 ỵ⛨䘬ẋ䡤妋慳䁢 Uivnc ẋ䡤ˤ劍 Sn 䘬 cju1^䁢 1炻⇯ cju2^⯙ ᶵ傥䁢 2ˤ! Mbcfm! 䦳⺷䚠⮵ῷ䦣忳䬿⺷ˤ! ! ȾCMY!mbcfmȿᶵ傥㗗㚱㡅ẞ䘬ˤ⬫⥳䳪⺽崟嗽䎮☐↯㎃⇘ Uivnc 䉨ンˤ! CMY)Csbodi!xjui!Mjol!boe!pqujpobmmz!fYdibohf*㊯Ẍ㚱⤪ᶳ䓐㱽烉! 2/ ⮯ᶳᶨ㡅㊯Ẍ䘬ỵ⛨㊟居⇘ S25 ᷕ)捰䳸㙓⬀☐*ˤ! 3/ 廱䦣⇘ mbcfm ㆾ Sn ᷕ䘬⛘⛨ˤ! 4/ 劍ᶳ朊ℑ㡅ᷕ䘬ảỽᶨ㡅ㆸ䩳炻⇯⮯㊯Ẍ普↯㎃⇘ Uivnc烉! ..!Sn 䘬 cju1^䁢 2! !!!!!!!!..!ἧ䓐ȾCMY!mbcfmȿ⼊⺷! 㨇☐䳂䘬ȾCMY!mbcfmȿ㊯Ẍᶵ傥廱䦣⇘䚖⇵㊯Ẍ⛇ 43NC 䭬⚵ᷳ⢾䘬ỵ⛨ˤ! !!!!! ἳ⫸烉! CMY!!S3! CMYOF!!S1! CMY!!uivnctvc! ! 3.4 輔助運算器指令 2/ DEQ ␴ DEQ3! 庼≑忳䬿☐屯㕁㑵ἄ)DEQ炻Dpqspdfttps!Ebub!pQfsbujpo*ˤ! ⎍㱽烉! DEQ|dpoe~!!dpqspd炻pqdpef2炻DSe炻DSo炻DSn|炻pqdpef3~! DEQ3!!dpqspd炻pqdpef2炻DSe炻DSo炻DSn|炻pqdpef3~! ! ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! dpqspd! ㊯Ẍ㑵ἄ䘬庼≑忳䬿☐⎵䧙ˤ㧁㸾⎵䧙䁢 qo炻℞ᷕ o 䁢 1 ᶨ 26 䭬⚵ℏ䘬㔜㔠ˤ! Pqdpef2! 庼≑忳䬿☐䘬䈡⭂㑵ἄ䡤ˤ! DSe炻DSo炻DSn! 庼≑忳䬿☐㙓⬀☐ˤ! pqdpef3! ⎗怠㑯䘬庼≑忳䬿☐䈡⭂㑵ἄ䡤ˤ! !! 忁ṃ㊯Ẍ䘬ἧ䓐⍾㰢㕤庼≑忳䬿☐ˤ! DEQ3 ⥳䳪㗗䃉㡅ẞ䘬ˤ! ! 3/ NDSˣNDS3 ␴ NDSS! ⮯屯㕁⽆ BSN 㙓⬀☐⁛復⇘庼≑忳䬿☐ˤ⎗㊯⭂⎬䧖旬≈㑵ἄ炻ὅ㒂庼≑忳 䬿☐侴⭂ˤ! ⎍㱽烉! NDS|dpoe~!!dpqspd炻pqdpef2炻Se炻DSo炻DSn|炻pqdpef3~! ! 第31 頁!
  • 38.
    NDS3!!dpqspd炻pqdpef2炻Se炻DSo炻DSn|炻pqdpef3~! NDSS|dpoe~!!dpqspd炻pqdpef2炻Se炻So炻DSn! ! ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! dpqspd! ㊯Ẍ㑵ἄ䘬庼≑忳䬿☐⎵䧙ˤ㧁㸾⎵䁢 qo炻℞ᷕ o 䁢 1 ᶨ 26 䭬⚵ℏ䘬㔜㔠ˤ! Pqdpef2! 庼≑忳䬿☐䘬䈡⭂㑵ἄ䡤ˤ! Se炻So! ⍇⥳㙓⬀☐炻ᶵ⃩姙㗗 S26ˤ! DSo炻DSn! 庼≑忳䬿☐㙓⬀☐ˤ! pqdpef3! ⎗怠㑯䘬庼≑忳䬿☐䈡⭂㑵ἄ䡤ˤ! ! 忁ṃ㊯Ẍ䘬ἧ䓐⍾㰢㕤庼≑忳䬿☐ˤ! NDS3 ⥳䳪㗗䃉㡅ẞ䘬ˤ! ! B/ NSDˣNSD3 ␴ NSSD! ⮯屯㕁⽆庼≑忳䬿☐⁛復⇘ BSN 㙓⬀☐ˤ⎗㊯⭂⎬䧖旬≈㑵ἄ炻ὅ㒂庼≑忳 䬿☐侴⭂ˤ! ⎍㱽烉! NSD|dpoe~!!dpqspd炻pqdpef2炻Se炻DSo炻DSn|炻pqdpef3~! NSD3!!dpqspd炻pqdpef2炻Se炻DSo炻DSn|炻pqdpef3~! NSSD|dpoe~!!dpqspd炻pqdpef2炻Se炻So炻DSn! ! ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! dpqspd! ㊯Ẍ㑵ἄ䘬庼≑忳䬿☐⎵䧙ˤ㧁㸾⎵䁢 qo炻℞ᷕ o 䁢 1 ᶨ 26 䭬⚵ℏ䘬㔜㔠ˤ! Pqdpef2! 庼≑忳䬿☐䘬䈡⭂㑵ἄ䡤ˤ! Se炻So! ⍇⥳㙓⬀☐炻ᶵ⃩姙㗗 S26ˤ! DSo炻DSn! 庼≑忳䬿☐㙓⬀☐ˤ! pqdpef3! ⎗怠㑯䘬庼≑忳䬿☐䈡⭂㑵ἄ䡤ˤ! ! 忁ṃ㊯Ẍ䘬ἧ䓐⍾㰢㕤庼≑忳䬿☐ˤ! NSD3 ⥳䳪㗗䃉㡅ẞ䘬ˤ! ! C/ MED ␴ TUD! ⛐姀ㅞ橼␴庼≑忳䬿☐ᷳ攻⁛復屯㕁ˤ! ⎍㱽烉! 忁ṃ㊯Ẍ㚱 4 䧖⎗傥⼊⺷烉! 暞ῷ䦣烉pq|dpoe~|M~!!dpqspd炻DSe炻So^! ⇵䳊⺽ῷ䦣烉pq|dpoe~|M~!!dpqspd炻DSe炻So炻$|.~pggtfu^|"~! ⼴䳊⺽ῷ䦣烉pq|dpoe~|M~!!dpqspd炻DSe炻So^炻$|.~pggtfu! ! ℞ᷕ烉! ! 第32 頁!
  • 39.
    dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! M!⎗怠㑯⯦䡤炻㊯㖶㗗攟㔜㔠⁛復ˤ! dpqspd! ㊯Ẍ㑵ἄ䘬庼≑忳䬿☐⎵䧙ˤ㧁㸾⎵䧙䁢 qo炻℞ᷕ o 䁢 1ȹ26 䭬⚵ℏ䘬㔜㔠ˤ! DSe! 䓐㕤庱ℍㆾ⃚⬀䘬庼≑忳䬿☐㙓⬀☐ˤ! So! 姀ㅞ橼➢⛨㙓⬀☐ˤ劍㊯⭂ S26炻⇯ἧ䓐䘬ῤ㗗䔞⇵㊯Ẍỵ⛨≈ 9ˤ! pggtfu! 忳䬿⺷炻℞ῤ䁢 5 䘬㔜᾵㔠炻䭬⚵⛐ 1ȹ2131 ᷳ攻ˤ! !! 忁ṃ㊯Ẍ䘬ἧ䓐⍾㰢㕤庼≑忳䬿☐ˤ! ! D/ MED3 ␴ TUD3! ⛐姀ㅞ橼␴庼≑忳䬿☐ᷳ攻⁛復屯㕁䘬㊯Ẍˤ㟡㒂屯㕁⁛復㕡⎹⎗ẍ怠㑯ℑ 侭℞ᶨˤ! ⎍㱽烉! 忁ṃ㊯Ẍ㚱 4 䧖⎗傥䘬⼊⺷烉! 暞ῷ䦣烉pq!!dpqspd炻DSe炻So^! ⇵䳊⺽ῷ䦣烉pq!!dpqspd炻DSe炻So炻$|.~pggtfu^|"~! ⼴䳊⺽ῷ䦣烉pq!!dpqspd炻DSe炻So^炻$|.~pggtfu! ! ℞ᷕ烉! dpqspd! ㊯Ẍ㑵ἄ䘬庼≑忳䬿☐⎵䧙ˤ㧁㸾⎵䧙䁢 qo炻℞ᷕ o 䁢 1ȹ26 䭬⚵ℏ䘬㔜㔠ˤ! DSe! 䓐㕤庱ℍㆾ⃚⬀䘬庼≑忳䬿☐㙓⬀☐ˤ! So! 姀ㅞ橼➢⛨㙓⬀☐ˤ劍㊯⭂ S26炻⇯ἧ䓐䘬ῤ㗗䔞⇵㊯Ẍỵ⛨≈ 9ˤ! pggtfu! 忳䬿⺷炻℞ῤ䁢 5 䘬㔜᾵㔠炻䭬⚵⛐ 1ȹ2131 ᷳ攻ˤ! ! 忁ṃ㊯Ẍ䘬ἧ䓐⍾㰢㕤庼≑忳䬿☐ˤ! MED3 ␴ TUD3 ⥳䳪㗗䃉㡅ẞ䘬ˤ! ! 3.5 雜項指令 2/ TXJ! 庇橼ᷕ㕟ˤ! ⎍㱽烉! TXJ|dpoe~!!jnnfe`35! ! ℞ᷕ烉jnnfe`35 䁢忳䬿⺷ˤ℞ῤ䁢 1!ȹ!)335.2*!䭬⚵ℏ䘬㔜㔠)35 ỵ⃫㔜㔠*ˤ! ! TXJ)TpguXbsf!Joufssvqu*㊯Ẍ⺽崟 TXJ ἳ⢾ˤ忁シ␛叿嗽䎮☐㧉⺷嬲㎃䁢 䭉䎮㧉⺷炻DQTS ᾅ⬀⇘䭉䎮㧉⺷䘬 TQTS ᷕ炻➟埴廱䦣⇘ TXJ ⎹慷ˤ! 忁㡅㊯Ẍᶵ⼙枧㡅ẞ䡤㧁娴ˤ! ! ! 第33 頁!
  • 40.
    ἳ⫸烉! TXJ!!1y234567! ! 3/ NST! ⮯ DQTS ㆾ TQTS 䘬ℏ⭡⁛復⇘ᶨ凔䓐徼㙓⬀☐ˤ! ⎍㱽烉! NST|dpoe~!!Se炻qts! ! ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! Se! 䚖㧁㙓⬀☐ˤSe ᶵ⃩姙䁢 S26ˤ! qts! DQTS ㆾ TQTSˤ! ! NST 冯 NTS 惵⎰ἧ䓐炻ἄ䁢㚜㕘 QTS 䘬Ⱦ嬨ᶨᾖ㓡ȹ⮓ȿ⸷↿䘬ȹ悐↮ˤἳ ⤪烉㓡嬲嗽䎮☐㧉⺷ㆾ㶭昌㧁娴 Rˤ! 䔞嗽䎮☐⛐ἧ䓐侭㧉⺷ㆾ䲣䴙㧉⺷ᶳ㗪炻ᶨ⭂ᶵ傥娎⚾⬀⍾ TQTSˤ! 忁㡅㊯Ẍᶵ⼙枧㡅ẞ䡤㧁娴ˤ! ἳ⫸烉! NTS!!S4炻TQTS! ! B/ NTS! 䓐䩳⌛㔠ⷠ㔠ㆾᶨ凔䓐徼㙓⬀☐䘬ℏ⭡庱ℍ DQTS ㆾ TQTS 䘬㊯⭂⋨➇ˤ! ⎍㱽烉! NTS|dpoe~!!=qts?`=gjfmet?炻$jnnfe`9s! NTS|dpoe~!!=qts?`=gjfmet?炻Sn! ! ℞ᷕ烉! =qts?! DQTS ㆾ TQTSˤ! =gjfmet?! ㊯⭂⁛復䘬⋨➇ˤ=gjfmet?⎗ẍ㗗ẍᶳ䘬ȹ䧖ㆾ⣂䧖烉! d! ㍏⇞➇怖休ỵ⃫䳬)QTS8;1^*! y! 㒜⯽➇怖休ỵ⃫䳬)QTSm6;9^*! t! 䉨ン➇怖休ỵ⃫䳬)QTS34;27^*! g! 㧁娴➇怖休ỵ⃫䳬)QTS42;35^*! jnnfe`9s! ῤ䁢㔠⫿ⷠ㔠䘬忳䬿⺷ˤⷠ㔠⽭枰⮵ㅱ 9 ỵ溆昋⚾ˤ娚溆昋⚾ ⛐ 43 ỵ⃫ᷕ徜⚰䦣ỵ„㔠ỵˤ! Sn! Ἦ㸸㙓⬀☐ˤ! !! NST 冯 NTS 䚠惵⎰ἧ䓐炻ἄ䁢㚜㕘 QTS 䘬Ⱦ嬨ȹᾖ㓡ȹ⮓ȿ⸷↿䘬ȹ悐↮ˤ ἳ⤪烉㓡嬲嗽䎮☐㧉⺷ㆾ㶭昌㧁娴 Rˤ! 劍㊯⭂ g)gjfme*炻⇯㊯Ẍ栗⺷㚜㕘㧁娴ˤ! ! ἳ⫸烉! NTS!!DQTS`g炻S6! ! ! 第34 頁!
  • 41.
    C/ CLQU! ᷕ㕟溆㊯Ẍˤ! ⎍㱽烉! CLQU!!jnnfe`27! ! ℞ᷕ烉jnnfe`27 䁢忳䬿⺷ˤ℞ῤ䁢䭬⚵⛐ 1ȹ76647 ℏ䘬㔜㔠)27 ỵ⃫㔜㔠*ˤ! ! CLQU)CsfbLQpjoU*㊯Ẍ⺽崟嗽䎮☐忚ℍ昌拗㧉⺷ˤ昌拗ⶍ℟⎗ἧ䓐忁ᶨ溆⛐ ㊯Ẍ⇘忼䈡⭂䘬ỵ⛨㗪婧㞍䲣䴙䉨ンˤ! ! ἳ⫸烉! CLQU!!1yG13D! CLQU!!751! ! 3.6 虛擬指令 2/ BES! ⮯䦳⺷䚠⮵ῷ䦣ㆾ㙓⬀☐䚠⮵ῷ䦣ỵ⛨庱ℍ⇘㙓⬀☐ᷕˤ! ⎍㱽烉! BES|dpoe~!!sfhjtufs炻fyqs! ! ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! sfhjtufs! 庱ℍ䘬㙓⬀☐ˤ! Fyqs! 䦳⺷䚠⮵ῷ䦣ㆾ㙓⬀☐䚠⮵ῷ䦣忳䬿⺷炻⍾ῤ䁢! ..!朆 xpse ⮵㸾ỵ⛨炻⛐.366ȹ,366 ỵ⃫䳬䭬⚵ℏˤ! ..!xpse ⮵㸾ỵ⛨炻⛐.2131ȹ,2131 ỵ⃫䳬䭬⚵ℏˤ! ! ⮵㕤䦳⺷䚠⮵ῷ䦣忳䬿⺷炻䴎⭂䭬⚵㗗䚠⮵䚖⇵㊯Ẍỵ⛨⼴ℑᾳ⫿嗽ˤ! BES ⥳䳪⼁䶐ㆸ m 㡅㊯Ẍˤ⼁䶐☐娎⚾䓊䓇╖ᾳ BEE ㆾ TVC ㊯ẌἮ庱ℍỵ⛨ˤ 劍ỵ⛨ᶵ傥㓦Ṣ m 㡅㊯Ẍ炻⇯䓊䓇拗婌炻⼁䶐⣙㓿ˤ! ⚈䁢ỵ⛨㗗䦳⺷䚠⮵ῷ䦣ㆾ㙓⬀☐䚠⮵ῷ䦣炻BES 䓊䓇ỵ伖䃉斄䘬ẋ䡤ˤ! ἧ䓐 BESM 嘃㒔㊯Ẍẍ⼁䶐㚜⮔䘬㚱㓰ỵ⛨䭬⚵ˤ! 劍 fyqs 㗗䦳⺷䚠⮵ῷ䦣炻⇯⬫⽭枰⍾ῤㆸ冯 BES 嘃㒔㊯Ẍ⛐⎴ᶨẋ䡤⋨➇ 䘬ỵ⛨ˤ! ! ἳ⫸烉! tubsu! NPW!!S1炻$21! BES!!S5炻tubsu! ! 3/ BESM! ⮯䦳⺷䚠⮵ῷ䦣ㆾ㙓⬀☐䚠⮵ῷ䦣ỵ⛨庱ℍ⇘㙓⬀☐ᷕˤBESM 栆Ụ㕤 BES 嘃 㒔㊯ẌˤBESM ⚈䁢䓊䓇 3 ᾳ屯㕁嗽䎮㊯Ẍ炻㭼 BES ⎗庱ℍ㚜⮔䭬⚵䘬ỵ⛨ˤ! ⛐⼁䶐 Uivnc ㊯Ẍ㗪 BESM 䃉㓰ˤBESM 䓐⛐ BSN ẋ䡤ᷕˤ! ⎍㱽烉! ! 第35 頁!
  • 42.
    BESM|dpoe~!!sfhjtufs炻fyqs! ! ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! sfhjtufs! 庱ℍ䘬㙓⬀☐ˤ! fyqs! 䦳⺷䚠⮵ῷ䦣ㆾ㙓⬀☐䚠⮵ῷ䦣忳䬿⺷炻⍾ῤ䁢! ..!朆 xpse ⮵㸾⛘⛨炻⛐ 75LC 䭬⚵ℏˤ! ..!xpse ⮵㸾⛘⛨炻⛐ 367LC 䭬⚵ℏˤ! ! ⮵㕤䦳⺷䚠⮵ῷ䦣忳䬿⺷炻䴎⭂䭬⚵㗗䚠⮵䚖⇵㊯Ẍỵ⛨⼴ℑᾳ⫿嗽ˤʉ! BESM ⥳䳪⼁䶐ㆸ 3 㡅㊯Ẍˤ⌛ἧỵ⛨⎗㓦ℍ 2 㡅㊯Ẍ炻ḇ䓊䓇䫔 3 㡅∑检㊯ Ẍˤ劍⼁䶐☐ᶵ傥⮯ỵ⛨㓦ℍ 3 㡅㊯Ẍ炻⇯䓊䓇拗婌炻⼁䶐⣙㓿ˤ! ⚈䁢ỵ⛨㗗䦳⺷䚠⮵ῷ䦣ㆾ㙓⬀☐䚠⮵ῷ䦣炻BESM 䓊䓇ỵ伖䃉斄䘬ẋ䡤ˤ! 劍 fyqs 㗗䦳⺷䚠⮵ῷ䦣炻⇯⽭枰⍾ῤㆸ冯 BESM 嘃㒔㊯Ẍ⛐⎴ᶨẋ䡤⋨➇䘬 ỵ⛨烊⏎⇯捰䳸⼴⎗傥崭↢䭬⚵ˤ! ! ἳ⫸烉! tubsu! ! NPW!!S1炻$21! BESM!!S5炻tubsu,7111! ! B/ MES! 䓐 43 ỵ⃫ⷠ㔠ㆾᶨᾳỵ⛨庱ℍ㙓⬀☐ˤ! ⎍㱽烉! MES|dpoe~!!sfhjtufs炻>fyqs!}!mbcfm.fyqs^! ℞ᷕ烉! dpoe! ⎗怠㑯䘬㡅ẞ䡤ˤ! ! sfhjtufs! 庱ℍ䘬㙓⬀☐ˤ! fyqs! 䴎ῤㆸ㔠⫿ⷠ㔠ˤ! ..!劍 fyqs ῤ㗗⛐㊯Ẍ䘬䭬⚵ℏ炻⇯⼁䶐☐䓊䓇ᶨ㡅 NPW ㆾ NWO ㊯Ẍˤ! ..!劍 fyqs ῤᶵ⛐ NPW ㆾ NWO ㊯Ẍ䘬䭬⚵ℏ炻⇯⼁䶐☐⮯ⷠ㔠㓦 ℍ 2jufsbm!qppm炻᷎䓊䓇ᶨ㡅䦳⺷䚠⮵ῷ䦣䘬 MES ㊯Ẍ⽆ 2jufsbm!qppm 嬨ⷠ㔠ˤ! mbcfm.fyqs!䦳⺷䚠⮵ῷ䦣ㆾ⢾悐忳䬿⺷ˤ⼁䶐☐⮯ mbcfm.fyqs 䘬ῤ㓦ℍ 2jufsbm!qppm炻᷎䓊䓇ᶨ㡅䦳⺷䚠⮵ῷ䦣䘬 MES ㊯Ẍ⽆ mjufsbm! qppm ᷕ庱ℍῤˤ劍 mbcfm.fyqs 㗗⢾悐忳䬿⺷炻ㆾᶵ⊭⏓⛐䚖⇵ ⋨➇ℏ炻⇯⼁䶐☐⮯ᶨᾳ捰䳸☐⎗慵⭂ỵ㊯Ẍ㓦ℍ䚖㧁㨼ˤ捰䳸 ☐⛐捰䳸㗪䓊䓇ỵ⛨ˤ! ! MES)MpbE!Sfhjtufs*嘃㒔㊯Ẍ䓐㕤 3 ᾳᷣ天䚖䘬烉! 2/ 䔞䩳⌛㔠ῤ䓙㕤崭↢ NPW ␴ NWO ㊯Ẍ䭬⚵侴ᶵ傥庱ℍ⇘㙓⬀☐ᷕ㗪炻䓊 䓇㔯⫿ⷠ㔠ˤ! 3/ ⮯䦳⺷䚠⮵ῷ䦣ㆾ⢾悐ỵ⛨庱ℍ⇘㙓⬀☐ᷕˤỵ⛨ᾅ㊩㚱㓰侴冯捰䳸☐ ! 第36 頁!
  • 43.
    ⮯⊭⏓ MES 䘬FMG ⋨➇㓦⇘ỽ嗽䃉斄ˤ! 忁䧖㕡㱽庱ℍ䘬ỵ⛨⛐䄼㍍㗪㗗⚢⭂䘬炻⚈侴ẋ䡤冯ỵ伖㚱斄ˤ! ⽆ QD ⇘ mjufsbm!qppm ᷕῤ䘬ῷ䦣慷⽭枰⮷㕤 5LCˤ攳䘤侭⽭枰䡢ᾅ⛐㊯Ẍ 䭬⚵ℏ㚱ᶨᾳ mjufsbm!qppmˤ! ἳ⫸烉! MES!!S4炻>1ygg1! MES!!S2炻>qmbdf! ! C/ OPQ! OPQ 䓊䓇㇨暨䘬 BSN 䃉㑵ἄẋ䡤ˤ! ⎍㱽烉! OPQ! ! OPQ)Op!PQfsbujpo*ᶵ傥㚱㡅ẞἧ䓐ˤ➟埴␴ᶵ➟埴䃉㑵ἄ㊯Ẍ㗗ᶨ㧋䘬炻 ⚈侴ᶵ暨天㚱㡅ẞ➟埴ˤ! BMV 䉨ン㧁娴ᶵ⍿ OPQ ⼙枧ˤ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! 第37 頁!
  • 44.
    1 UEE3303 Introductionto Embedded Systems Lecture 4 Cortex Processors YuLun Huang http://rtes.cn.nctu.edu.tw UEE 3303 <1> YL Huang Spring ‘14 © NCTU Cortex Profiles ° 2004, ARM introduced new Cortex family of processors ° Three profiles • Cortex-A: high-end application processor • Cortex-R: real-time processor • Cortex-M: microcontroller UEE 3303 <2> YL Huang Spring ‘14 © NCTU Cortex-M Profiles ° Cortex-M0, Cortex-M0+ • Smallest processor in the family • Low-cost, low-power • Replacement of the existing 8-bit uC (still offering 32-bit performance) ° Cortex-M1 • Similar to M0, but designed as a soft core (running on FPGA) ° Cortex-M3 • High performance uC ° Cortex-M4 • +DSP • +FPU UEE 3303 <3> YL Huang Spring ‘14 © NCTU 8051 vs. Cortex-M0 ° M0 is a reduced version of M3, but keeps good performance model ° The example is a 16 x 16 mult • multiplies r1 & r0, and put the results in r0 UEE 3303 <4> YL Huang Spring ‘14 © NCTU
  • 45.
    2 Cortex-M0 vs.Cortex-M0+ ° Cortex-M0+ is fully compatible with Cortex-M0 ° Cortex-M0+ has more advanced features • More processing power and lower power consumption - 11 uW vs. 16 uW • 2-stage pipeline to reduce number of memory accesses and runtime energy consumption UEE 3303 <5> YL Huang Spring ‘14 © NCTU New peripheral I/O interface ° New I/O interface supports single cycle access to peripheral registers ° Cortex-M0+ can fetch instruction via AHB while making a data access to the peripheral registers UEE 3303 <6> YL Huang Spring ‘14 © NCTU Cortex-M3 ° The mainstay of the Cortex-M family ° High-performance 32-bit uC ° 3-stage pipeline: Fetch, Decode, Execute ° Like the ARM7, it is a RISC processor: most instructions execute in a single cycle ° Manufactured at a very low cost UEE 3303 <7> YL Huang Spring ‘14 © NCTU Cortex-M3 Pipeline ° ARM instructions ° Thumb instructions ° Thumb-2 instructions • a blend of 16- and 32-bit instructions UEE 3303 <8> YL Huang Spring ‘14 © NCTU
  • 46.
    3 Cortex-M4 °M3 + DSP + Floating Point Support: single precision Support event-driven microcontroller code UEE 3303 <9> YL Huang Spring ‘14 © NCTU In this class, we have ° PTK using Cortex-M3 ° K60D using Cortex-M4 UEE 3303 <10> YL Huang Spring ‘14 © NCTU
  • 47.
    1 UEE3303 Introductionto Embedded Systems Lecture 5 PTK YuLun Huang http://rtes.cn.nctu.edu.tw UEE 3303 <1> YL Huang Spring’14 © NCTU PTK ° Contains a PTK-BASE and a PTK-MCU • NOTE: LED2 & 3 are not workable in our target board UEE 3303 <2> YL Huang Spring’14 © NCTU (What we have?) Top side of PTK-BASE UEE 3303 <3> YL Huang Spring’14 © NCTU Hardware Installation ° PTK ° DC-12V ° JTAG (debugger) UEE 3303 <4> YL Huang Spring’14 © NCTU
  • 48.
    2 GPIO UEE3303 <5> YL Huang Spring’14 © NCTU LEDs (LED0 ~ LED3) UEE 3303 <6> YL Huang Spring’14 © NCTU 7-Segment (HEX1) UEE 3303 <7> YL Huang Spring’14 © NCTU Button (KEY0 ~ KEY3, RESET) UEE 3303 <8> YL Huang Spring’14 © NCTU
  • 49.
    3 DIP Switch(SW1) 1 DIP Switch with 4 bits connected to MCU for input UEE 3303 <9> YL Huang Spring’14 © NCTU Buzzer (SU1) • The only audible device in PTK-BASE • Should be connected to a clock signal for generating beep • You can change the tone of buzzer by changing the frequency of clock input UEE 3303 <10> YL Huang Spring’14 © NCTU Sensors ° Built-in Sensors • Potentiometer (VR1) • Light Sensor (U3) • Temperature Sensor (U5) • Infrared TX/RX ° Extended Sensor Modules • Follow the PTK-MEMS module design specification, you can design your own sensor modules UEE 3303 <11> YL Huang Spring’14 © NCTU I/O Map for Light Sensor (U3: ISL29023) ° Full-scale Range: 1000 lux~64000lux ° Human eye response ° 16-bit resolution ° Programmable upper and lower threshold interrupt ° The I2C device address is 0x44 • PTK-MCU uses I2C bus to link ISL29023 for setup and retrieving ambient light data UEE 3303 <12> YL Huang Spring’14 © NCTU
  • 50.
    4 Storage °EEPROM (U6) ° SD Socket (CN13) UEE 3303 <13> YL Huang Spring’14 © NCTU Communication ° Ethernet (CN16) ° USB (CN15) ° RS-485 & CAN (CN12, JP3) ° RS-232 (CN11) UEE 3303 <14> YL Huang Spring’14 © NCTU
  • 51.
    1 UEE3303 Introductionto Embedded Systems Lecture 6 Embedded System Development YuLun Huang http://rtes.cn.nctu.edu.tw UEE 3303 <1> YL Huang Spring‘14 © NCTU Hardware and Software Co-Design Model ° Hardware and software for an embedded system are developed in parallel • Software component can take advantage of special hardware features to gain performance • Hardware component can simplify module design if functionality can be achieved in software - Reduce overall hardware complexity and cost • Co-design model emphasized the fundamental characteristics of embedded systems: APPLICATION-SPECIFIC UEE 3303 <2> YL Huang Spring‘14 © NCTU Cross-Platform Development ° Platform: • Hardware (processor) • Operating System • Software Development tools ° Software for an embedded system is developed on one platform but runs on another. • Host system: where the software is developed • Target system: embedded system under development ° Cross-Compiler • Compiler that runs on one type of processor architecture but produces object code for a different type of processor architecture - Host: Intel (IA-32/IA64) - Target: ARM/MIPS UEE 3303 <3> YL Huang Spring‘14 © NCTU Cross-platform Host System Target System HEWLET PACKARD Serial Host Resident Software Target Resident ICE Ethernet JTAG Software Application API layer File system layer Logical block layer Device driver Hardware layer UEE 3303 <4> YL Huang Spring‘14 © NCTU
  • 52.
    2 Essential DevelopmentTools ° Host System offers: • Cross compiler • Linker • Source-level debugger ° Target Embedded System offers: • Linker loader • Monitor • Debug agent ° Connections between host and target system: • Serial Interface • ICE: JTAG (Xmit debug info b/w host debugger & target debug agent) ° Programs including: • System software • Real-time operating system (RTOS): Kernel • Application code ° Steps: • Compiled programs into object code • Linked together into an executable image UEE 3303 <5> YL Huang Spring‘14 © NCTU Development ° Native development: • Writing applications that execute in the same env as used for development • Do not need to be concerned with - How an executable image is loaded into memory and - How execution control is transferred to the application ° Cross-platform development: • Need to understand the target system fully: - How to store the program image on the target system - How and where to load the image during runtime - How to develop and debug the system iteratively - .. • These aspects impact how the code is developed, compiled and linked. UEE 3303 <6> YL Huang Spring‘14 © NCTU Product design process UEE 3303 <7> YL Huang Spring‘14 © NCTU IDE (Integrated Development Environment) ° Integrated • Editor • Compiler • Linker • Debugger… ° IAR ° CodeWarrior UEE 3303 <8> YL Huang Spring‘14 © NCTU
  • 53.
    3 IAR UEE3303 <9> YL Huang Spring‘14 © NCTU IAR Product offering ° IAR Embedded Workbench • Generic development platform, supports more than 35 different 8, 16 and 32 bit architectures • Includes C/Embedded C++ optimizing compiler, assembler, linker, librarian, editor, project manager and C-SPY debuggers IAR visualSTATE • Graphical design tool for embedded applications based on state machine models • Designing, testing and implementation real-time applications based on superior technology • Automatically generates consistent code for embedded systems IAR MakeApp • Device driver wizard. Master the complexity of an modern microcontroller more quicker and easier than ever before IAR’s products for Bluetooth • IAR Embedded Stack for Bluetooth, » Compact and easy configurable • PreQual • Starter kit UEE 3303 <10> YL Huang Spring‘14 © NCTU Complete suite of tools from IAR visualSTATE Design Embedded Workbench Verify, Validate, Implement IAR J-Link & IAR J-Trace IAR Development Kits Compile Debug Deploy Target applicati on Idea IAR RTOS & Middleware IAR PowerPac UEE 3303 <11> YL Huang Spring‘14 © NCTU Model State Chart / UML State Machine Modeling Tool User-Written Codes Middleware TCP/IP Stack USB Stack GUI RTOS Kernel BSP File System Compiler / Assembler Linker Debugger Code IDE Auto- Generated Code Project Manager Target System ARM SoC On-Chip Peripherals On-Chip Flash On-Chip RAM ARM Core Embedded ICE ETM Trace Port JTAG Port Emulator Trace Probe JTAG Probe UEE 3303 12 YL Huang Spring‘14 © NCTU
  • 54.
    4 ePBB Development UEE 3303 13 YL Huang Spring‘14 © NCTU IAR Workspace ° Manage multiple projects for a product • by right-clicking on the project and choosing ‘Set as Active’ to select the project V V V V V The workspace contains 5 projects: adc, alarm, lcd, pit, rtc UEE 3303 14 YL Huang Spring‘14 © NCTU IAR Project ° Manage multiple files/libraries for a project ° One example is creating a group to hold source files that is common between projects, and you only want one unique copy of these files. UEE 3303 15 YL Huang Spring‘14 © NCTU Create Project ° 1. Open IAR. Inside the startup window click the first button: “Create new project in current workspace.” UEE 3303 16 YL Huang Spring‘14 © NCTU
  • 55.
    5 ° 2.Select the “Empty project” Template, then click OK. UEE 3303 17 YL Huang Spring‘14 © NCTU ° 3. name your project and specify the desired directory. Click “OK.” Then your project should appear in the upper left-hand side of the screen. Right-click on it then choose “Options.” UEE 3303 18 YL Huang Spring‘14 © NCTU ° 4. Inside the options: choose the appropriate XXXXX device (STM32F207VG in this case). • If you want to be programming in ASM, also check the “Assembler -only project” box in the lower-right hand side of the screen. • If you are programming in C, please leave this box unchecked. UEE 3303 19 YL Huang Spring‘14 © NCTU ° 5. For C project please verify that the “Library Configurations” tab has “CLIB” chosen for the library. For assembly projects this option should be selected as “none.” UEE 3303 20 YL Huang Spring‘14 © NCTU
  • 56.
    6 ° 6.Next select the “Debugger” category on the left-side of the screen. • Choose “YYYY Debugger” under the “Driver” (J-Link in this case). • For C projects please make sure “Run to main” is checked. UEE 3303 21 YL Huang Spring‘14 © NCTU ° 7. Under the “YYYY Debugger” category, make sure the appropriate hardware programmer is selected under “Connection” and the appropriate JTAG protocol is selected under “Debug protocol.” • Click OK. These should be the only changes necessary to build a simple code and load it onto your target XXXXX. • NOTE: The Spy-Bi-Wire mode is not supported by the Parallel Programmer (e.g. MSP-FET430PIF), when LPTx is selected. UEE 3303 22 YL Huang Spring‘14 © NCTU ° 8. Now we are ready to load our code file onto your XXXXX. To do this, right-click on your project and go to Add - Add files. Browse to your code file with a “.c” C -file or “.s” assembly file. UEE 3303 23 YL Huang Spring‘14 © NCTU ° 9. Now your code should be added to your project. If you double-click on the newly added code file the text should appear in the main window. UEE 3303 24 YL Huang Spring‘14 © NCTU
  • 57.
    7 Configuration ofa Project ° By default when creating a new project, you automatically get two configurations: Release and Debug UEE 3303 25 YL Huang Spring‘14 © NCTU CODE WARRIOR UEE 3303 26 YL Huang Spring‘14 © NCTU
  • 58.
                                                                                                                                                                                                                                                                  
  • 59.
                                                                                                                                                                                                                                
  • 60.
                                                                                                                                                                                                                                            
  • 61.
                                                                                                                                                                                                                                                                                                               
  • 62.
                                                                                                                                                                                                                                                                                                                                    
  • 63.
                                                                                                                                                                                                                                                                                                                            
  • 64.
                                                                                                                                                                                              
  • 65.
    1 UEE3303 Introductionto Embedded Systems Lecture 7 uCOS/II YuLun Huang http://rtes.cn.nctu.edu.tw UEE 3303 1 YL Huang Spring‘14 © NCTU A computer is… ° Computer = App + OS + Hardware UEE 3303 2 YL Huang Spring‘14 © NCTU RTOS Overview UEE 3303 3 YL Huang Spring‘14 © NCTU Real Time OS ° Real-time OS (RTOS) is an intermediate layer between hardware devices and software programming ° “Real-time” means keeping deadlines, not speed ° Advantages of RTOS in SoC design • Shorter development time • Less porting efforts • Better reusability ° Disadvantages • More system resources needed • Future development confined to the chosen RTOS UEE 3303 4 YL Huang Spring‘14 © NCTU
  • 66.
    2 μC/OS-II °Written by Jean J. Labrosse in ANSI C ° A portable, ROMable, scalable, preemptive, real -time, multitasking kernel ° Used in hundreds of products since its introduction in 1992 ° Certified by the FAA for use in commercial aircraft ° Available in ARM Firmware Suite (AFS) ° Over 90 ports for free download ° http://www.ucos-ii.com UEE 3303 5 YL Huang Spring‘14 © NCTU μC/OS-II Features ! Portable 8-bit ~ 64 bit ! ROMable small memory footprint ! Scalable select features at compile time ! Multitasking preemptive scheduling, up to 64 tasks UEE 3303 6 YL Huang Spring‘14 © NCTU μC/OS-II vs. μHAL ° uHAL is shipped in ARM Firmware Suite ° uHAL is a basic library that enables simple application to run on a variety of ARM-based development systems ° uC/OS-II use uHAL to access ARM-based hardware uC/OS-II User application AFS Utilities C, C++ libraries uHAL routines Development board AFS support routines UEE 3303 7 YL Huang Spring‘14 © NCTU Kernel ! Basic jobs of uC/OS-II kernel • Task management • Interrupt handling • Inter-process communication UEE 3303 8 YL Huang Spring‘14 © NCTU
  • 67.
    3 Kernel API ° Service routines provided by uC/OS-II Kernel • Task management APIs • Time management APIs • Memory management APIs • Inter-process communication APIs • Synchronization APIs ° To make a System Call means to call Kernel API UEE 3303 9 YL Huang Spring‘14 © NCTU Task ! Task is an instance of program ! Task thinks that it has the CPU all to itself ! Task is assigned a unique priority ! Task has its own set of stack ! Task has its own set of CPU registers (backup in its stack) ! Task is the basic unit for scheduling ! Task status are stored in Task Control Block (TCB) UEE 3303 10 YL Huang Spring‘14 © NCTU Task Structure Task structure: ! An infinite loop ! An self-delete function Task with infinite loop structure void ExampleTask(void *pdata) { for(;;) { /* User Code */ /* System Call */ /* User Code */ } } Task that delete itself void ExampleTask(void *pdata) { /* User Code */ OSTaskDel(PRIO_SELF); } UEE 3303 11 YL Huang Spring‘14 © NCTU Task States Waiting Task Delete Task Create Task Gets Event Task Pending Events Highest Priority Task Interrupt Dormant Ready Running ISR Task Delete Task is Preempted Task Delete Int. Exit UEE 3303 12 YL Huang Spring‘14 © NCTU
  • 68.
    4 Task Priority ! Unique priority (also used as task identifiers) ! 64 priorities max (8 reserved) ! Always run the highest priority task that is READY ! Allow dynamically change priority UEE 3303 13 YL Huang Spring‘14 © NCTU Task Control Block uC/OS-II use TCB to keep record of each task States Stack Pointer Priority Misc … Link Pointer UEE 3303 14 YL Huang Spring‘14 © NCTU Task Control Block(cont.) UEE 3303 15 YL Huang Spring‘14 © NCTU Exchanging CPU Control Control returns from task to OS when Kernel API is called void ExampleTask(void *pdata) { for(;;) { /* User Code */ /*System Call */ /* User Code */ } } uC/OS-II Kernel API OSMboxPend(); OSQPend(); OSSemPend(); OSTaskSuspend(); OSTimeDly(); OSTimeDlyHMSM(); More… UEE 3303 16 YL Huang Spring‘14 © NCTU
  • 69.
    5 Exchanging CPUControl Only one of OS, Task, Interrupt Handler gets CPU control at a time A B B C A Interrupt Handler OS Task Time Scheduling System Call Interrupt Interrupt Exit UEE 3303 17 YL Huang Spring‘14 © NCTU Task Scheduling ° Non-preemptive Time ISR Low-priority Task ISR makes the high-priority task ready High-priority Task low-priority task Relinquishes the CPU UEE 3303 18 YL Huang Spring‘14 © NCTU Task Scheduling ° Preemptive ISR Low-priority Task ISR makes the high-priority task ready high-priority task Relinquishes the CPU uC/OS-II adopts preemptive scheduling Time High-priority Task UEE 3303 19 YL Huang Spring‘14 © NCTU Context Switching ! Context Switching • The process of swap in/out the context of tasks when scheduler choose a new task to run. ! Context • Usually means values in registers used by the task. ! Switching Steps 1. Save registers of current task to stack(curr) 2. Load new task’s SP into CPU 3. Restore registers of new task from stack(new) 4. Resume execution of new task UEE 3303 20 YL Huang Spring‘14 © NCTU
  • 70.
    6 Context Switching Time ISR Low-priority Task Context Switching High-priority Task ISR makes the high-priority task ready Context Switching high-priority task Relinquishes the CPU UEE 3303 21 YL Huang Spring‘14 © NCTU Critical Region ° Code need to be treated indivisibly ! Code have to be executed without interrupt creating task…etc ! Non-reentrant code accessing shared variable…etc UEE 3303 22 YL Huang Spring‘14 © NCTU Critical Region ! Protecting critical region • OS_ENTER_CRITICAL( ) temporarily disable interrupt • OS_EXIT_CRITICAL( ) re-enable interrupt UEE 3303 23 YL Huang Spring‘14 © NCTU Events ! A way for Synchronization and Communication • Pend (Wait for an event) • Post (Signal an event) ! Events in uC/OS-II • Semaphore • Counting Semaphore • Message Mailbox • Message Queues UEE 3303 24 YL Huang Spring‘14 © NCTU
  • 71.
    7 Semaphore !Semaphore serves as a key to the resource ! A flag represent the status of the resource ! Prevent re-entering Critical Region ! Can extent to counting Semaphore Task 1 Task 2 RS-232 Send data via RS232 Request/Release Semaphore Request/Release Send data via RS232 UEE 3303 25 YL Huang Spring‘14 © NCTU Semaphore Using Semaphore in uC/OS-II ! OSSemCreate() ! OSSemPend() ! OSSemPost() ! OSSemQuery() ! OSSemAccept() UEE 3303 26 YL Huang Spring‘14 © NCTU Message Mailbox ! Used for Inter-Process Communication (IPC) ! A pointer in MailBox points to the transmitted message Task ISR Task Post Mail Box Pend “message” Post UEE 3303 27 YL Huang Spring‘14 © NCTU Message Queues ! Array of MailBox ! FIFO FILO configuration Task ISR Task Post Mail Queues Pend “message” Post UEE 3303 28 YL Huang Spring‘14 © NCTU
  • 72.
    8 MailBox Queues Using MailBox in uC/OS-II ! OSMboxCreate() ! OSMboxPend() ! OSMboxPost() ! OSMboxQuery() ! OSMboxAccept() Using Queue in uC/OS-II ! OSQCreate() ! OSQPend() ! OSQPost() ! OSQPostFront() ! OSQQuery() ! OSQAccept() ! OSQFlush() UEE 3303 29 YL Huang Spring‘14 © NCTU Memory Management ! Semi-dynamic memory allocation ! Allocate statically and dispatch dynamically ! Explore memory requirements at design time dispatch dynamically Task 1 Task 2 Task 3 partition into memory blocks allocate statically OS Initializing OS running UEE 3303 30 YL Huang Spring‘14 © NCTU Memory Management Using Memory in uC/OS-II ! OSMemCreate() ! OSMemGet() ! OSSemPut() ! OSSemQuery() UEE 3303 31 YL Huang Spring‘14 © NCTU Interrupt ° Interrupt Controller • A device that accepts up to 22 interrupt sources from other pheripherals and signals ARM processor ° Interrupt Handler • A routine executed whenever an interrupt occurs. It determines the interrupt source and calls corresponding ISR. Usually provided by OS. ° Interrupt Service Routine (ISR) • Service routines specific to each interrupt source. This is usually provided by hardware manufacturer. UEE 3303 32 YL Huang Spring‘14 © NCTU
  • 73.
    9 Interrupt °Peripheral sends interrupt request to interrupt controller ° Interrupt controller sends masked request to ARM ° ARM executes interrupt handler to determine int. source Peripheral A Interrupt Controller Peripheral B ARM Processor bus UEE 3303 33 YL Huang Spring‘14 © NCTU Interrupt ! Default interrupt handler: uHALr_TrapIRQ() 1. Save all registers in APCS-compliant manner 2. Call StartIRQ(), if defined 3. Determine interrupt source, call the corresponding interrupt service routine (ISR) 4. Call FinishIRQ(), if defined 5. Return from interrupt UEE 3303 34 YL Huang Spring‘14 © NCTU Interrupt ! When an interrupt occurs, no further interrupt accepted ! To achieve real-time, the period of interrupt disabled should be as short as possible ! Do only necessary jobs in ISR, leave other jobs in a deferred Task UEE 3303 35 YL Huang Spring‘14 © NCTU Starting μC/OS-II Initialize hardware uC/OS-II ARMTargetInit(), OSInit() Allocate resources OSMemCreate(), OSMboxCreate(), …etc Create at least one task OSTaskCreate() Start Scheduler OSStart() UEE 3303 36 YL Huang Spring‘14 © NCTU
  • 74.
    10 Porting Application ° Necessary coding changes ! variables • use local variables for preemption • use semaphore to protect global variables (resources) ! data transfer • arguments = mailbox/queue ! memory allocation • malloc() = OSMemCreate() OSMemGet() UEE 3303 37 YL Huang Spring‘14 © NCTU Porting Application ° assign task priorities ! unique priority level in uC/OS-II • only 56 levels available • priority can be change dynamically ! call OSTimeDly() in infinite loop task • ensure lower priority task get a chance to run MUST: if lower priority task is pending data from higher priority task UEE 3303 38 YL Huang Spring‘14 © NCTU Driver ! What is a Driver • A named entity that support basic I/O of a device • A handler that manages interrupt from a device • A description to a device, registered and managed by OS • An abstraction layer for user application to access device easily UEE 3303 39 YL Huang Spring‘14 © NCTU Driver ° Original configuration of a System – No additional Hardware Application OS HAL Development Board UEE 3303 40 YL Huang Spring‘14 © NCTU
  • 75.
    11 Driver °New configuration of a System – additional Hardware added ° We must add driver into system to provide easy access of new hardware Application OS HAL Driver New Hardware Development Board UEE 3303 41 YL Huang Spring‘14 © NCTU Driver ! High-level API • Interactive with OS • Interface to Application ! Low-level Command • Direct access to hardware (usually written in assembly) ! Data • Private data to driver Application OS HAL API Data Command New Hardware Development Board UEE 3303 42 YL Huang Spring‘14 © NCTU Driver ! Command Layer • A set of functions/macros to manipulate hardware • Interrupt handler • Usually written in Assembly to get optimized speed • Keep essential commands only ! Common essential commands • Read, Write, Init, Enable, Disable UEE 3303 43 YL Huang Spring‘14 © NCTU Driver ! API layer • Interactive with OS to maintain resources • Interactive with OS to acknowledge interrupt and task scheduling • Provides unique interface to application to achieve device abstraction • Encapsulate driver internal data • Combine commands to provide various functionality ! Data • Driver Status • Data Buffer UEE 3303 44 YL Huang Spring‘14 © NCTU
  • 76.
    12 Driver °Why divide driver into two parts • Easy to replace underlying hardware • Unique interface to applications • Easy to adopt pre-written assembly code UEE 3303 45 YL Huang Spring‘14 © NCTU Driver ° API Example Available commands: • Read_Byte • Write_Byte • Init_Device • Enable_Device • Disable_Device Set_serial_baudrate(int baud) { OS_Request_Device(); Disable_Device(); Write_Byte(CONF_BASE, baud); Enable_Device(); OS_Release_Device(); } UEE 3303 46 YL Huang Spring‘14 © NCTU Driver ° API Example Send_serial(char data[], int len) { OS_Request_Device(); for(I=0;Ilen;I++) Write_Byte(IO_BASE, data[I]); OS_Release_Device(); } Available commands: • Read_Byte • Write_Byte • Init_Device • Enable_Device • Disable_Device UEE 3303 47 YL Huang Spring‘14 © NCTU Driver Design Flow start Decide I/O interface (I/O address, I/O method) Write Assembly code to control hardware Pack assembly code into commands Write interrupt handler Write API base on previously Developed commands Test Driver end Test assembly code UEE 3303 48 YL Huang Spring‘14 © NCTU
  • 77.
    1 UEE3303 Introductionto Embedded Systems Lecture 8 Freescale YuLun Huang http://rtes.cn.nctu.edu.tw UEE 3303 1 YL Huang Spring‘14 © NCTU KINETIS VS. K60D UEE 3303 2 YL Huang Spring‘14 © NCTU Vybrid Controller Solutions Rich Apps in Real Time. Real-time, highly integrated solutions with best-in-class 2D graphics to enable your system to control, interface, connect, secure and scale. i.MX Application Processors Your Interface to the World. Industry’s most versatile solutions for multimedia and display applications, with multicore scalability and market-leading power, performance integration. Kinetis Microcontrollers Design Potential. Realized Industry’s most scalable ultra-low-power, mixed -signal MCU solutions based on the ARM® Cortex™-M4 and ARM® Cortex™-M0+ architectures. QorIQ Processors built on Layerscape Architecture Accelerating the Network’s IQ Industry’s first software -aware, core-agnostic networking system architecture for the smarter, more capable networks of tomorrow – end to end. Consumer Automotive Industrial Consumer Industrial Consumer Automotive Industrial Networking Industrial Freescale has the industry’s broadest range of solutions built on ARM® technology for automotive, industrial, consumer and networking applications. Find your ideal solution at the price, performance and power level you desire, and leverage the extensive software and tool bundles available to speed and ease your design process. UEE 3303 3 YL Huang Spring‘14 © NCTU Kinetis Series • Kinetis Overview • K Series- 32-bit ARM Cortex M4 • L Series - 32-bit ARM Cortex M0+ • M Series – 32-bit ARM Cotex M0+ for Smart Metering • W Series - 32-bit ARM Cortex M0+ M4 for Wireless (IoT) UEE 3303 4 YL Huang Spring‘14 © NCTU
  • 78.
    2 Kinetis Portfolio Performance General Purpose Segment Focused Integration Coming 2013 Kinetis L Series Ultra-low power/cost ARM Cortex-M0+ MCU families from 48MHz / 8KB with mixed-signal, connectivity HMI features in low pin-count packages. Availability NOW! Kinetis K Series Industry-first ARM Cortex-M4 MCU families from 50MHz / 32KB with low power, FlexMemory, mixed-signal and broad connectivity, HMI security features. Availability NOW! Kinetis W Series Integrated wireless connectivity 5V ARM Cortex -M0+ ARM Cortex-M4 MCU families with class-leading sub-1 GHz and 2.4 GHz RF transceivers Kinetis M Series High accuracy metrology ARM Cortex-M0+ MCU families for single chip smart meter implementations. Coming 2013 (samples now) Leading Performance - Low Power - Scalability - Industrial-grade reliability temp Coming 2013 (samples now) Freescale Bundled IDE, RTOS Middleware - Rapid prototyping Platform - Broad ARM Ecosystem Support UEE 3303 5 YL Huang Spring‘14 © NCTU K Series: MCU Family Compatibility + Ethernet, Encryption, Tamper Detect, DRAM Controller I I I I I I I I K20 Family 50-120MHz 32KB-1MB 32-144pin I I I I I K60 Family 100-150MHz 256KB-1MB 100-256pin I I I I I I I I I I I I I I I I I I + Graphics LCD Entry Point + Analog Measurement Engine, I I I I I I I I K30 Family 72-100MHz 64-512KB 64-144pin + USB K10 Family 50-120MHz 32KB-1MB 32-144pin I I I I I I I I I I I I I I I I I I K70 Family 120-150MHz 512KB-1MB 196-256pin I I I I I I I I I I I I I I I I I I + Segment LCD K40 Family 72-100MHz 64-512KB 64-144pin I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I K50 Family 72-100MHz 128-512KB 64-144pin I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I + Segment LCD + USB Ethernet, Encryption UEE 3303 6 YL Huang Spring‘14 © NCTU Kinetis K60 Family Core Arm® Cortex™- M4 100/120/150 MHz Debug Interfaces DSP Interrupt Controller System Memories Clocks Internal and External Watchdogs Memory Protection Unit (MPU) DMA Low–Leakage Wake-Up Unit Program Flash (256 to 1 MB) FlexMemory (256 to 512KB) (4 to 16 KB EE) Serial Programming Interface (EZPort) SRAM (64 to 128 KB) External Bus Interface (FlexBus) Phase-Locked Loop Flequency -Locked Loop Low/High -Frequency Oscillators Internal Reference Clocks Float Point Unit (FPU) NAND Flash Controller Cache DDR Controller Security Analog Timers Communication HM I and Integrity Interfaces Cyclic Redundancy Check (CRC) 16-bit ADC PGA Analog Comparator with 6-bit DAC 12-bit DAC Voltage Reference I2S GPIO Secure Digital Host Controller (SDHC) I2C UART (ISO 7816) SPI CAN Xtrinsic Low -Power Touch –Sensing Interface Random Number Generator Cryptographic Acceleration Unit (CAU) Hardware Tamper Detection Unit FlexTimer Carrier Modulator Transmitter Programmable Delay Block Periodic Interrupt Timers Low-Power Timer Independent Real-Time Clock (RTC) IEEE® 1588 Timer Standard Feature Optional Feature USB On-the -Go (LS/FS) USB On-the -Go (HS) USB Device Charger Detect (DCD) USB Voltage Regulator IEEE 1588 Ethernet MAC UEE 3303 7 YL Huang Spring‘14 © NCTU Kinetis Part Numbering Scheme M K 20 D X 256 (Z) V LQ 10 (R) Qualification status Kinetis Family Core / Key Attribute FlexMemory Flash Size Tape and Reel (TR) Speed/10 Package Identifier Temperature range Reserved for Silicon Revision Number Memory Flash Size Silicon Rev Temperature Package Speed TR Options Description Options Description Options Description Options Description Options Description Options Description Options Description D M4 w/ DSP N Non-FlexMemory 8 8KB Z Initial Revision C -40 to 85C 16TSSOP 4 48MHz Blank Non TR F M4 w/ DSPFPU X Flexmemory 16 16KB 2nd Revision V -40 to 105C 24QFN 5 50MHz R TR 32 32KB A 3rd Revision M -40 to 125C 32CSP 7 72MHz 64 64KB B 4th Revision FM 32QFN 10 100MHz 96 96KB … … FT 48QFN 12 120MHz 128 128KB LF 48LQFP 15 150MHz 256 256KB 18 180MHz 512 512KB MP 64MAPBGA 1M0 1MB LH 64LQFP 1M5 1.5MB LK 80LQFP 2M0 2MB LL 100LQFP 2M5 2.5MB AB 120WLCSP … … MC 121MAPBGA AA 143WLCSP LQ 144LQFP MD 144MAPBGA MJ 256MAPBGA * 196MAPBGA package removed Key Attribute Options Attribute UEE 3303 8 YL Huang Spring‘14 © NCTU
  • 79.
    3 Kinetis K/LSeries: Packaging 32QFN 5 x 5 mm 0.5mm pitch (K10/20) (KL0/1/2) Common Packages Kinetis K Series Package Kinetis L Series Package 64MAPBGA 5 x 5 mm 0.5mm pitch (K10/20) (KL1*/2*/3*/4*) 48LQFP 7 x 7 mm 0.55mm pitch (K10/20) (KL0/1*/2*) 64LQFP 10 x 10 mm 0.5mm pitch (K10/20/30/40/50) (KL1/2/3/4) 80LQFP 12 x 12 mm 0.5mm pitch (K10/20/30/40/50) (KL1/2/3*/4*) 100LQFP 14 x 14 mm 0.5mm pitch (K10/20/30/40/50/60) (KL3/4) Kinetis L Series Only Kinetis K Series Only 90WLCSP 3.9x4.4x0.56 mm 0.4mm pitch (K10/20*) 144LQFP 20 x 20 mm 0.5mm pitch (K10/20/30/40/50/60) 48QFN 7 x 7 mm 0.5mm pitch (K10/20) (KL0/1*/2*) 110WLCSP 3.9x4.4x0.56 mm 0.4mm pitch (K10/20*) 144MAPBGA 13 x 13 mm 1.0mm pitch 120WLCSP 5.3x5.3x0.56 mm 0.4mm pitch (K10/20/60) (K10/20/30/40/50/60) 121MAPBGA 8 x 8 mm 0.65mm pitch (K10/20/30/40/50/60) (KL2/3/4) 143WLCSP 6.5x5.6x0.56 mm 0.4mm pitch (K61) 256MAPBGA 17 x 17 mm 1.0mm pitch (K60/70) 35WLCSP 2.55x3x0.56 mm 0.4mm pitch (KL1*/2*) 32LQFP 7 x 7 mm 0.8mm pitch (KL0) 25WLCSP 2.3x2.3x0.56 mm 0.4mm pitch (KL0*) 20WLCSP 2x2x0.56 mm 0.4mm pitch (KL0) 24QFN 4 x4x1 mm 0.5mm pitch (KL0x) 16QFN 3x3x1 mm 0.5mm pitch (KL02) UEE 3303 9 YL Huang Spring‘14 © NCTU *proposed (Development Tools) ENABLEMENT OVERVIEW UEE 3303 10 YL Huang Spring‘14 © NCTU Kinetis Tower System: Reusable, modular development platform www.freescale.com/tower www.towergeeks/org MCU Families Supported TWR Part Number Contents Price (SRP) K20 TWR-K20D50M 64 LQFP MCU module. USB communication supported without TWR-SER (recommended for UART) $99 TWR-K20D72M 100 LQFP MCU module. USB communication supported without TWR-SER $119 TWR-K21D50M 81 MAPBGA MCU module. Hardware security features supported. $119 K30/40 TWR-K40X256 TWR-K40D100M TWR-K40X256 Rev 1.0 (144MBGA), TWRPI-SLCD TWR-K40D100M Rev 2.0 Silicon (144MBGA) $69 TWR-K40X256-KIT TWR-K40X256 (144MBGA), TWRPI-SLCD TWR-SER, TWR-ELEV $139 K50 TWR-K53N512 TWR-K53N512 (144MBGA), TWRPI-SLCD $109 TWR-K53N512-KIT TWR-K53N512 (144MBGA), TWRPI-SLCD, TWR-SER, TWR-ELEV $179 K10/20/60 TWR-K60N512 TWR-K60D100M TWR-K60N512 Rev 1.0 Silicon (144MBGA) TWR-K60D100M Rev 2.0 Silicon (144MBGA) TWR-K60N512-KIT TWR-K60N512 (144MBGA), TWR-SER, TWR-ELEV $139 TWR-K60N512-IAR TWR-K60N512-KIT (144MBGA), TWR-PROTO, Segger J-Link Lite Debug Probe, IAR EWARM IDE (eval. version) NEW TWR-K60N512-KEIL TWR-K60N512-KIT (144MBGA), UNLINK-ME Debug Probe, KEIL MDK IDE (eval. version) • IDEs: FSL CodeWarrior, IAR Embedded Workbench, Keil MDK, • Freescale MQX RTOS • OSJTAG Debug circuitry – program debug with USB cable $69 $99 $239 $199 TWR-SENSOR -PAK TWR-LCD TWR-WIFI-RS2101 • Low power touch sensing plug-in socket for expansion: Sensors, Radio, etc… • Fully compatible with all Tower peripheral modules UEE 3303 12 YL Huang Spring‘14 © NCTU UEE 3303 11 YL Huang Spring‘14 © NCTU Kinetis IDE Support Availability 1. Freescale (CodeWarrior 10.1) [available now] - Includes MQX Task Aware Debug plug-in option - MCU v10.4 [available now] 2. IAR (Embedded Workbench) [available now] - EWARM: Supports all ARM7/9 and all Cortex Devices - EWARM-BaseLine (BL): All the features of EWARM but is limited in code space up to 256KB - EWARM-CM: Supports any Cortex-M series devices including (M4) - EWARM-CM-FSL: Supports any Kinetis Cortex-M4 series device – Will be re-sold via FSL Buy Direct program only. $2500 for 1 year license – Includes MQX Task Aware Debug plug-in option – http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=EWARM-CM-FSLfsrch=1sr=2 3. Keil (MDK) [available now] - MQX Task Aware Debug plug-in planned . 4. Greenhills (MULTI) [available now] 5. CodeSourcery (Sourcery G++) [available now] - MQX Task Aware Debug plug-in planned.
  • 80.
    4 NanoSSL™/ NanoSSH™Client for Freescale MQX Security options with significant cost savings ° Secure Shell (SSH) encrypts communications between hosts over an insecure network, and it’s great for logging into and executing commands on networked computers. It’s also useful for tunneling, port-forwarding and secure file transfers using the SFTP protocol. • Super-fast, super-small embedded SSH and SSL clients from Mocana • One-time “unlocking” fee of $199 to access source code with unlimited binary distribution • Available via Buy Direct www.freescale.com/embeddedcomponents ° Secure Sockets Layer/Transport Layer Security (SSL/TLS) - authenticates endpoints and encrypts channels to provide session privacy and security on the Internet. The standard operates at a higher level in the OSI stack than IPsec, and supports peer negotiation for algorithm selection, public key based exchange of secret session keys and X.509 certificates. » Ultra-small at less than one fifth the size of a typical SSL/SSH client. » Minimal impact on device performance » Minimal impact on flash ROM utilization Addition Upgrades: http://mocana.com/mqx/ Royalty-Free for MQX Users! ° Freescale’s super-fast, super-small embedded SSH/SSL client by Mocana • Kinetis NANOSSL, NANOSSH and CAU libraries due end May / start June • “How-to-use CAU Library” App Note is currently in development for Kinetis. Available Now UEE 3303 13 YL Huang Spring‘14 © NCTU PE Micro Universal Multilink (U-MULTILINK) http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=UMultilink Features • Easy-to-use debug and programming interface which allows the PC to communicate with a target processor through the USB port of the PC. • Controls the MCU/MPU by accessing the debug port of the target. • Can communicate with multiple MCUs using multiple headers - flip open the plastic case. Ribbon cables for the supported MCUs are conveniently included. • Supported by recent versions of CodeWarrior, current PE software applications, and Kinetis tool chains from IAR, Keil, and Mentor Graphics. • Draws power directly from the USB port – no external power supply needed • Multi-voltage support for targets ranging from 1.6 to 5.25 Volts • Multilink Universal FX: a high-speed version of the USB Multilink Universal with additional enhancements. Supports: Replaces: • Kinetis N/A • HCS08 USBMULTILINK08 • HC(S)12(X) USBMULTILINKBDM • ColdFire(+) V1 USBMULTILINKBDM • ColdFire V2-4 USBMLCF • Qorivva USBMLPPCNEXUS Freescale U-MULTILINK $119 PE USB-ML-UNIVERSAL $119 UEE 3303 14 YL Huang Spring‘14 © NCTU KINETIS KL25 UEE 3303 15 YL Huang Spring‘14 © NCTU Kinetis L Series: Enabling Differentiation in Entry-Level Products 32-bit 8-bit Energy-efficiency Class-leading Coremark/mW Scalability Integration Kinetis L to K Series (Cortex M0+ to M4) Enablement Freescale bundle + ARM ecosystem Ultra Low Static 1uA Low cost From $0.50 Ease-of-use Freedom Platform, Processor Expert MCU Solution Advisor Kinetis L Series The evolution of the entry-level MCU UEE 3303 16 YL Huang Spring‘14 © NCTU
  • 81.
    5 ARM Cortex-M0+Processor Fetch Decode Execute Fetch De code Exe Shorter Pipeline optimized for energy efficiency From Cortex-M3 Re-locatable Vector Table Memory Protection Unit (MPU) New Fast I/O Port Micro Trace Buffer (MTB) More Options Full ARMv6-M compatible UEE 3303 17 YL Huang Spring‘14 © NCTU ARM Cortex-M0+ Processor Energy-Efficiency • 2-stage pipeline – reduced cycles per instruction (CPI) enabling faster branch instruction and ISR entry • Program memory access on alternate cycles Single-Cycle I/O Port • 50% higher GPIO toggling frequency than standard I/O • Improves reaction time to external events allowing bit -banding and software protocol emulation • Save precious cycles, e.g. set faster peripherals for low-power access • Access GPIO/peripherals while processor fetches the next instruction Processing • Only 56 Instructions, mostly coded on 16-bit. Option for fast MUL 32x32 bit in 1 cycle • Cortex-M0/3/4 compatible • 1.77CM/MHz • Best-in-class code density vs. 8/16-bit architectures – reduced cost, power consumption and pin-count Micro Trace Buffer • Powerful, lightweight trace solution enabling fast debug • Non-intrusive – trace information stored in small area of MCU SRAM (size defined by programmer) • Trace read over Serial Wire /JTAG (CPU stopped) UEE 3303 18 YL Huang Spring‘14 © NCTU ARM Cortex-M0+ powering Kinetis L Series 90nm TFS Memory Bit Mani-pulation Engine RGPIO eDMA Crossbar Integration Flash Memory Controller Micro Trace Buffer sLCD USB Smart Evolution Instead of Revolution ⇒ Reduce # of Cycles ⇒ Reduce Overall Power Consumption ⇒ Comprehensive Compatibility ⇒ Improved Performance ⇒ Autonomous Precise Low Power Peripherals UEE 3303 19 YL Huang Spring‘14 © NCTU Kinetis L Series: Reduce cycles with parallelization and acceleration schemes ! Support concurrent access from DMA/Core to memory and peripherals – offload CPU ! Kinetis L-Series devices support DMA operation in low power modes Rapid GPIOs Master Slave Bit Manipulation Engine ARM® Cortex™-M0+ Direct Memory Access Flash Memory Controller Any operation involving a DMA channel follows the same three steps: 1. Channel initialization 2. Data transfer 3. Channel termination The FMC supports 8-bit, 16-bit, and 32-bit read operations from the program flash memory. In addition, the FMC provides two separate mechanisms for accelerating the interface between bus masters and program flash memory. A 32-bit speculation buffer can prefetch the next 32-bit flash memory location, and a 4-way, 4-set program flash memory cache. UEE 3303 20 YL Huang Spring‘14 © NCTU
  • 82.
    6 Moving from8/16-bit to 32-bit ARM Cortex-M0+ Benefits • Linear 4GB address space • Full-featured interrupt controller • Huge scalability • Huge ARM ecosystem • Micro Trace Buffer • 12-35kgates (similar to 8/16bit) • Excellent code density • 2x to 40x more than 8/16- bit, 9% more than Cortex- M0 • Fast 32-bit math processing • Fast single-cycle access to I/O • 2x CoreMark/mA than closest 8/16-bit MCU, +30% / CM0 Performance Ease-of- Development Energy- Low Cost Efficiency UEE 3303 21 YL Huang Spring‘14 © NCTU K L M W E X Kinetis L Series: Reduce cycles for optimized power efficiency ! Supported operations • Decorated Stores • Logical AND, OR, XOR • Bit field insert (BFI) ! Supported operations • Load-and-Clear 1 bit (LAC1) • Load-and-Set 1 bit (LAS1) • Unsigned Bit Field Extract (UBFX) Task Normal C Code Size BME Code Size Improvement Logical XOR operation 12Bytes 6Bytes 50% Bit Field Insert 24Bytes 6Bytes 75% GPIOA_PDOR ^= 0x02; // Logical XOR 0000005E 0x.... LDR R0,? ?DataTable6_5 ;; 0x400ff000 00000060 0x6800 LDR R0,[R0, #+0] 00000062 0x2102 MOVS R1,#+2 00000064 0x4041 EORS R1,R1,R0 00000066 0x.... LDR R0,? ?DataTable6_5 ;; 0x400ff000 00000068 0x6001 STR R1,[R0, #+0] Uses 12 Bytes // Macro used to generate hardcoded XOR address #define BME_XOR_ADDR(ADDR) (*(volatile uint32_t * )(((uint32_t)ADDR) | (326))) BME_XOR_ADDR(GPIOA_PDOR) = 0x02; 00000014 0x.... LDR R0,??DataTable6_6 ;; 0x4c0ff000 00000016 0x2102 MOVS R1,#+2 00000018 0x6001 STR R1,[R0, #+0] Uses 6 Bytes UEE 3303 22 YL Huang Spring‘14 © NCTU ARM Cortex-M0+ Processor: Fast I/O Port ARM Cortex-M0+ Fast IO Port ! Single access Processor ! Most suited to critical GPIO and Peripherals Advantages for the application ! Higher GPIO toggling frequency ! Bit-bang the I/O as on a 8-bit ! Save precious cycles, e.g. set faster peripherals for low -power ! “Harvard-like”: access GPIO /Peripheral while processor fetch the next instruction UEE 3303 23 YL Huang Spring‘14 © NCTU ARM Cortex-M0+ Processor: A faster route to a bug free application ARM Micro Trace Buffer (MTB) ! Lightweight Trace ! Trace stored in RAM ! Non intrusive ! Read over Serial Wire /JTAG Freescale extensions: ! Additional address (and optionally data) watch points ! Define specific memory references were the trace start and stop AHB MTB Controller RAM I/F store trace information SRAM Appl.Data + Trace Data read trace information UEE 3303 24 YL Huang Spring‘14 © NCTU
  • 83.
    7 Kinetis LSeries Energy Efficiency • ARM Cortex-M0+ Processor • 90nm low-power flash technology • Bit Manipulation Engine • 50uA/MHz, 3.8CM/mW • Peripheral Bridge Crossbar • Zero Wait State Flash Memory Controller Ultra-efficient processing • 90nm low-leakage flash technology • Multiple RUN, WAIT and STOP modes • 4us wake-up from deep sleep modes • Clock power gating, low-power boot options • 2uA Deep Sleep Idd with register retention, LVD active and 4.3us wake-up Ultra low-power modes • Smart peripherals function in deep sleep modes and can make intelligent decisions and process data without waking up the core – ADMA, UART, Timers, ADC, Segment LCD, Touch Sensing... Energy-saving peripherals Most Innovative Process Technology Kinetis ARM® Cortex-M4 MCUs UEE 3303 25 YL Huang Spring‘14 © NCTU Kinetis L Series vs. Kinetis K Series Category Kinetis L Series Kinetis K Series Core, Performance ARM Cortex-M0+ (48MHz) ARM Cortex-M4 (50-150MHz) Flash 8-256KB 32KB-1MB Features Mixed-Signal, USB, Seg. LCD FlexMemory, Mixed-Signal, USB, Seg. LCD, CAN, Ethernet, Gra. LCD, DRAM, Crypto, Tamper Detect, DRAM Pin-count 16-121pin 32-256pin Low Power ~40uA/MHz (VLPR) ~200uA/MHz (VLPR) Price From $0.49 (MKL02, 8KB, 16QFN) From $0.99 (MK10, 32KB, 32QFN) Target Applications 816-bit replacement Low/mid/high –end 32-bit UEE 3303 26 YL Huang Spring‘14 © NCTU + Ethernet, Encryption, Tamper Detect, DRAM Controller I I I I I I I I K20 Family 50-120MHz 32KB-1MB 32-144pin I I I I I K60 Family 100-150MHz 256KB-1MB 100-256pin I I I I I I I I I I I I I I I I I I KL2x Family I I I I I I I I I I 48MHz I I I I I I I I 32KB-256KB 32-121pin I I I I I I I I I I I I I I I I K30 Family 72-100MHz 64-512KB 64-144pin + USB K10 Family 50-120MHz 32KB-1MB 32-144pin I I I I I I I I I I I I I I I I I I K70 Family 120-150MHz 512KB-1MB 196-256pin I I I I I I I I I I I I I I I I I I + Segment LCD K40 Family 72-100MHz 64-512KB 64-144pin I I I I I KL4x Family I I I I I I I I I I I I I I I I I I KL3x Family ARM Cortex-M4 KL1x Family I I I I I I I I I I I I I I I 48MHz 64-256KB 64-121pin I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I 48MHz I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I + Graphics LCD K50 Family 72-100MHz 128-512KB 64-144pin I I I I I I I I I I I I I I I I I I I I I I I 48MHz 128-256KB 64-121pin I I I I I I I I I I I I I I I I I I I I I I I I I I I I I 32KB-256KB 32-80pin I I I I I I I I + Segment LCD I I I I I I I I + USB + Analog Measurement Engine, Ethernet, Encryption I I I I I I I I Entry Point 8-bit MCU Compatible ARM Cortex-M0+ I I I I I I I I KL0x Family I I I I I I I I I I 48MHz 8KB-32KB 24-48pin I I I I I I I I UEE 3303 27 YL Huang Spring‘14 © NCTU System ARM Cortex-M0+ Core Ultra-low power 48MHz bus freq. Flash 32-256K RAM 4-32K Analog Interfaces KL24/5/6 Family Block Diagram Clock Management LPO (1KH z) FLL Crystal Oscillator (low high range) PLL Peripheral Bus Energy Management Voltage Regulator Power On Reset Low Voltage Detector Unique ID COP RST DMA 4-ch Timers PIT 2ch, 32bit SRTC Debug (SWD) 16b LPTPM 6ch x1, 2ch x 2 Temp. Compensated LS Osc (32KHz) ULP Osc (4MHz) Connectivity Connectivity I/O Ports LPU ART x1 SPI x 2 USB FS/LS Transceiver USB Controller UAR Tx2 IIS x1 LPTMR Inpu t I2C x 2 ADC (SAR w/ DMA) 12/16-bit, up to 16ch 12-bit DAC HSCMP Up to 80 GPIO (4 High Dive) w/ 25 interrupt TSI x 16ch RST/ Operation in: Run Wait VLL S1 VLL S0 Stop/ VLPS VLL S3 V Regulator Packages: 32QFN, 48QFN, 64LQFP, 80LQFP, 100LQFP, 121MBGA UEE 3303 28 YL Huang Spring‘14 © NCTU
  • 84.
    8 Freescale EcoMAPS:Kinetis SW Dev Tools Customer Application HW and SW Engineering Services Application Specific • Freescale Motor Control Libs • Freescale Medical USB Stacks • Mocana Middleware • Freescale eGUI • Freescale TSS • Freescale PEG (Swell) • Arcturus Networks • ARM CMSIS Libs • IXAAT • Stonestreet one • CMX Systems • HCC Embedded • Quadros Systems • MapuSoft • Motomic Software • SEGGER Operating Systems • Freescale MQX™ • CMX Systems • Emcraft Systems • Embedded Access • ExpressLogic • FreeRTOS • Green Hills Software • Keil (ARM) • Micrium • Quadros Systems • SEGGER Processor/MCU/DSP Common Occasional IDH ODM SBC/SOM SSI • Novtech • Embedded Access MQX • App Notes • Demos Ref Designs More Standard More Custom • Freescale CodeWarrior • Freescale Freemaster • Atollic • Green Hills Software • Hitex • IAR Systems • Keil (ARM) • Rowley Associates HW Dev Tools • Freescale Tower System • Freescale KWIKSTIK • Green Hills Software • Hitex • IAR Systems • iSYSTEM • Keil (ARM) • Lauterbach • PE Micro Systems • SEGGER • Kinetis SBC: Single Board Computers IDH: Independent Design House BDM: Background Debug Module SOM: System on Modules ODM: Original Design Manufacturer Training Training Partners • Embedded Access MQX • AC6 • Hilf GmbH SSI: Software and Solution Integrators IDE: Integrated Development Environment JTAG: Joint Test Action Group UEE 3303 29 YL Huang Spring‘14 © NCTU Kinetis L Series: Entry-level Enablement Hardware IDE Code Generation Run-Time Software Freescale Freedom Platform FRDM-KL25Z New New www.freescale.com/FRDM-KL25Z ° Low -cost/power platform for entry-level developers ($12.95 / €10 SRP) ° Integrates a fully featured debugger, that works with all featured tool chains. Freescale Tower System TWR-KL25Z48M www.freescale.com/TWR-KL25Z48M ° Modular, open-source development platform with reusable peripheral modules offering connectivity, analog, graphics LCD and motor control functionality Product Selector Freescale MQX Lite RTOS www.freescale.com/mqx • Free, light-weight MQX kernel customised for small resource MCUs • Packaged as a Processor Expert component • Upwards compatible with MQX RTOS Solution Advisor www.freescale.com/sa • Web-based interactive MCU selector • Filters for operating characteristics, packaging, memory configuration peripherals. Verifies muxing compatibility • Save, download and print summary reports and pin muxing configurations Freescale 3rd party IDEs • Freescale CodeWarrior v10.3: free 64KB • Keil MDK: free 32KB • IAR EWARM: free 32KB • Atollic TrueStudio: free 8KB • GCC ARM Embedded via Launchpad.net • Additional tool support from Code Red and others in Q412 Freescale Processor Expert Code Generator • Free software generation tool for device drivers / start-up code • 7 steps from project creation to debug – dramatically reduces development time • Available within CodeWarrior or as a standalone plug-in for IAR/Keil/GNU IDEs GNU UEE 3303 30 YL Huang Spring‘14 © NCTU Kinetis L Series: Freedom Platform www.freescale.com/FRDM-KL25Z FRDM-KL25Z Features: ! MKL25Z128VLK4 MCU – 48MHz, 128KB Flash, 16KB SRAM, USB OTG (FS), 80LQFP ! Capacitive touch “slider”, MMA8451Q accelerometer, Tri-color LED ! Flexible power supply options – USB, coin cell battery, external source ! Easy access to MCU I/O ! Battery-ready, power-measurement access points ! Form factor compatible with Arduino platform ! New, sophisticated OpenSDA debug interface ! Mass storage device flash programming interface (default) – no tool installation required to evaluate demo apps ! PE Multilink interface provides run-control debugging and compatibility with IDE tools ! Open-source Data Logging application provides an example for customer, partner and enthusiast development on the OpenSDA circuit Packed with software: ! Processor Expert: stand-alone or IDE integrated ! MQX Lite RTOS (via Processor Expert) ! Ecosystem partner support: IAR, Keil, Atollic, Rowley, Free GNU command-line tools with GDB server FRDM-KL05Z ! MKL05Z32VFM4 MCU – 48MHz, 32KB Flash, 32QFN ! Available now GNU Available now $12.95 / €10 UEE 3303 31 YL Huang Spring‘14 © NCTU Kinetis L Series: Tower System www.freescale.com/TWR-KL25Z48M TWR-KL25Z48M Features ! MKL25Z128VLK4 MCU – 48MHz, 128KB Flash, 16KB SRAM, USB OTG (FS) ! New, sophisticated OpenSDA debug interface ! Mass storage device flash programming interface (default) – no tool installation required to evaluate demo apps ! PE Multilink interface provides run-control debugging and compatibility with IDE tools ! Open-source Data Logging application provides an example for customer, partner and enthusiast development on the OpenSDA circuit ! 4 user LEDs, 2 capacitive touch buttons ! Freescale MMA8451QR1 accelerometer ! Flexible power supply options ! USB connector, elevators, 3.3v or 1.8v ! Current input measurement jumper ! Compatible with most TWR peripheral board Packed with software: ! Processor Expert: stand-alone or IDE integrated ! MQX Lite RTOS (via Processor Expert) ! Ecosystem partner support: IAR, Keil, Atollic, Rowley, Free GNU command-line tools with GDB server ! TWR-ELEV TWR peripheral modules should be ordered separately if required. No –KIT version planned GNU Available now $99.00 UEE 3303 32 YL Huang Spring‘14 © NCTU
  • 85.
    9 Kinetis LSeries: SOFTWARE Development Platforms Tool Free Version Limits CodeWarrior 10.4 64KB code size No MQX TAD IAR EWARM 30-day free trial KickStart: 16KB Option to pre-build libraries that don’t count Keil uVision 30-day free trial MDK-Lite: 32KB Atollic TrueSTUDIO 30-day free trial 8KB code size UEE 3303 33 YL Huang Spring‘14 © NCTU Kinetis L Series Enablement: CodeWarrior for MCUs v10.4 ° Freescale's CodeWarrior for MCU's v10.4 integrates the development tools for the ColdFire, ColdFire+, DSC, Kinetis, Qorivva, RS08, S08 and S12Z architectures into a single product based on the Eclipse open development platform ° Special Edition – Free. The following limitations apply – - unlimited assembly code - up to 32KB of C code for HC(S)08/RS08 derivatives - up to 64KB of C code for V1 ColdFire/ColdFire+ Kinetis L derivatives - up to 128KB of C code for V2-V4 ColdFire and Kinetis K derivatives ° Adding GCC compiler for ARM Cortex-M Series (M0+, M4) - FSL will provide support for the gcc compiler integrated with CodeWarrior - No support will be provided for non-integrated gcc compilers - Continuing to provide FSL ARM compiler (M4 only) An application note will be provided to help customers migrate existing FSL ARM ompiler based projects to ARM gcc compiler. Free Compiler up to 64KB! UEE 3303 34 YL Huang Spring‘14 © NCTU Processor Expert: Key Components Project Panel Tree Components Library Component Inspector Target CPU View Problems View UEE 3303 35 YL Huang Spring‘14 © NCTU Processor Expert: Software Design in just 7 Steps www.processorexpert.com Create Project Configure Components • Use Inspector to set all component settings 5 Generate Code • Processor Expert generates components Software Development Timeline 3 2 4 Add Components • Add components to the project from Components Library Verify Settings • Verify no design-time errors in the project 1 7 Build Debug • Build the application • Debug the application Write Application Code • Write application code using code generated for components 6 UEE 3303 36 YL Huang Spring‘14 © NCTU
  • 86.
    10 Processor Expert:On-line Training CodeWarrior version Microcontroller Driver Suite UEE 3303 37 YL Huang Spring‘14 © NCTU New Freescale MQX Lite RTOS: Overview www.freescale.com/mqx ° Very light MQX kernel for resource-limited • Targeted at the Kinetis L family initially • Packaged as a Processor Expert ° I/O capability provided by Processor • USB via FSL bare-metal stack, also a • No POSIX-like drivers or file access ° Programming model allows upward code • A true subset of the full MQX RTOS • Code built with MQX Lite will move to full • Same task templates, same API – some ° Available as a component within the following Freescale s/ware offerings: • Processor Expert software, MCU driver suite – Supports IAR, Keil, and GCC compilers / build chains • CodeWarrior Development Studio V10.3 GNU Tools Processor Expert: Introduction (Driver Suite) Processor Expert: Working with Components (Driver Suite) Processor Expert: The Code Model (Driver Suite) Processor Expert: Creating an MQX Lite Project (Driver Suite) Processor Expert: An MQX Lite Example (Driver Suite) Processor Expert: Exporting and Importing Templates (Driver Suite) Processor Expert: Integrating with IAR Embedded Processor Expert: Integrating with Keil Microvision Processor Expert: Introduction (CodeWarrior) Processor Expert: Working with Components (CodeWarrior) Processor Expert: The Code Model (CodeWarrior) Processor Expert: Creating an MQX Lite Project (CodeWarrior) Processor Expert: An MQX Lite Example (CodeWarrior) Processor Expert: Exporting and Importing Templates (CodeWarrior) (Standalone / 3rd party version) View in slideshow mode to enable hyperlinks MCUs component Expert Processor Expert component migration MQX RTOS easily very minor differences Attribute MQX RTOS MQX Lite RTOS Delivery Mechanism Traditional installer with full source for Kernel, services and BSPs Processor Expert (PEx) Kernel and services component, configurable software generated by PEx I/O Drivers MQX POSIX compatible drivers with option for using PEx drivers PEx drivers only Configurability User selects needed services from full or lightweight versions Reduced services available; lightweight options only UEE 3303 38 YL Huang Spring‘14 © NCTU New Freescale MQX Lite RTOS: Benefits www.freescale.com/mqx Easy to configure Packaged as a Processor Expert component; with configurable options: set name of task function, priority, stack size (all the same parameters as an MQX task) Easy to add existing application Just drop in the MQX Lite RTOS component, and get started in minutes Very light-weight Minimal app (Hello task, idle task, interrupt stack) – less than 4 KB RAM; optimized for resource-limited MCUs like Kinetis L Series family I/O capability provided by Processor Expert software Take advantage of the broad spectrum of MCU logical device drivers; with access to libraries/stacks like USB Processor Expert component Real-time, priority-based pre-emptive task switching Threads execute in order of priority, allowing high-priority threads to meet their deadlines consistently, no matter how many other threads are competing for CPU time Programming model allows upward code migration MQX Lite RTOS is a true subset of the full MQX RTOS: code built with MQX Lite RTOS will easily move to the full MQX RTOS MQX Lite with CodeWarrior Processor Expert Processor Expert: Creating an MQX Lite Project (CodeWarrior) MQX Lite with Microcontroller Driver Suite Processor Expert Processor Expert: Creating an MQX Lite Project (Driver Suite) Processor Expert: An MQX Lite Example (CodeWarrior) Processor Expert: An MQX Lite Example (Driver Suite) UEE 3303 39 YL Huang Spring‘14 © NCTU
  • 87.
    1 UEE3303 Introductionto Embedded Systems Lecture 9 MQX YuLun Huang http://rtes.cn.nctu.edu.tw UEE 3303 1 YL Huang Spring‘14 © NCTU Objectives ° This session describes basic RTOS concepts using the MQX RTOS ° It will cover tasks, scheduling, semaphores and more with hands-on examples ° You’ll learn how to use a RTOS and the advantages that using one provides UEE 3303 2 YL Huang Spring‘14 © NCTU Module Agenda ° What is an RTOS ° MQX Basics: Tasks • Hands-on ° MQX Basics: Scheduling • Hands-on ° MQX Basics: Task Synchronization • Semaphores • Hands-on ° Additional Resources ° Review UEE 3303 3 YL Huang Spring‘14 © NCTU Module Agenda ° Recall: What is an RTOS? ° MQX Basics: Tasks • Hands-on ° MQX Basics: Scheduling • Hands-on ° MQX Basics: Task Synchronization • Semaphores • Hands-on ° Additional Resources ° Review UEE 3303 4 YL Huang Spring‘14 © NCTU
  • 88.
    2 Topic I:Operating Systems User Application Operating System HARDWARE ° The term “operating system” can be used to describe the collection of software that manages a system’s hardware resources ° This software might include a file system module, a GUI and other components ° Often times, a “kernel” is understood to be a subset of such a collection ° Characteristics ! Resource management ! Interface between application and hardware ! Library of functions for the application UEE 3303 5 YL Huang Spring‘14 © NCTU Embedded Operating Systems ► Fusion of the application and the OS to one unit User Operating System + Application HARDWARE ► Characteristics ! Resource management Primary internal resources ! Less overhead ! Code of the OS and the application mostly reside in ROM UEE 3303 6 YL Huang Spring‘14 © NCTU Real Time Operating Systems ° A real-time operating system (RTOS) manages the time of a microprocessor or microcontroller ° Features of an RTOS: ! Allows multi-tasking ! Scheduling of the tasks with priorities ! Synchronization of the resource access ! Inter-task communication ! Time predictable ! Interrupt handling UEE 3303 7 YL Huang Spring‘14 © NCTU Why use an RTOS? ° Plan to use drivers that are available with an RTOS ° Would like to spend your time developing application code and not creating or maintaining a scheduling system ° Multi-thread support with synchronization ° Portability of application code to other CPUs ° Resource handling ° Add new features without affecting higher priority functions ° Support for upper layer protocols such as: ! TCP/IP, USB, Flash Systems, Web Servers, ! CAN protocols, Embedded GUI, SSL, SNMP UEE 3303 8 YL Huang Spring‘14 © NCTU
  • 89.
    3 Freescale MQX ° We will be using Freescale MQX to demonstrate these RTOS concepts ° Freescale MQX Software can be downloaded: ! http://www.freescale.com/mqx ° Default Freescale MQX folder: ! C:Program FilesFreescaleFreescale MQX 3.5 UEE 3303 9 YL Huang Spring‘14 © NCTU MQX Directory Structure ° Described in the MQX Release Notes ° Folders are: ! config ! demo ! doc ! lib ! mqx ! tools ! And then the RTCS, USB, and MFS stacks UEE 3303 10 YL Huang Spring‘14 © NCTU MQX Directory Structure (Cont.) ° The “mqx” directory is heart of MQX ° Folders are: ! build ! examples ! source - bsp - io - psp - MQX API source UEE 3303 11 YL Huang Spring‘14 © NCTU Changing Configuration Options ° User configuration options are set in mqx_install/config/board/user_config.h ° Change the default serial port to UART1: #define BSP_DEFAULT_IO_CHANNEL ttyb: #define BSP_DEFAULT_IO_CHANNEL_DEFINED #define BSPCFG_ENABLE_TTYB 1 ° Always need to re-build all the libraries with this new configuration UEE 3303 12 YL Huang Spring‘14 © NCTU
  • 90.
    4 Topic II:MQX RTOS Tasks ° A system consists of multiple tasks ° Tasks take turns running ° Only one task is active (has the processor) at any given time ° MQX manages how the tasks share the processor (context switching) ° Task Context • Data structure stored for each task, including registers and a list of owned resources UEE 3303 13 YL Huang Spring‘14 © NCTU Typical Task Coding Structure UEE 3303 14 YL Huang Spring‘14 © NCTU Task States ° A task is in one of these logical states: ! blocked - the task is blocked and therefore not ready - it’s waiting for a condition to be true ! active - the task is ready and is running because it’s the highest -priority ready task ! ready - the task is ready, but it’s not running because it isn’t the highest-priority ready task ! terminated - the task has finished all its work, or was explicitly destroyed UEE 3303 15 YL Huang Spring‘14 © NCTU Active Context Switch Higher-priority Task becomes Ready Time Slice Expires Interrupt comes in Ready Blocking Call Blocked Object Available Timeout Expires Task States Task Finishes Explicit Termination Terminated Task Starts UEE 3303 16 YL Huang Spring‘14 © NCTU
  • 91.
    5 Topic III:MQX Scheduling (Priorities) ° Each task is assigned a priority • Higher number means lower priority • 0 is highest priority ° Used by scheduler to determine which task to run next ° User tasks should run at priority 8 or higher. UEE 3303 17 YL Huang Spring‘14 © NCTU Scheduler ° Common Scheduling Configurations: ! FIFO (also called priority-based preemptive) - The active task is the highest-priority task that has been ready the longest ! Round Robin - The active task is the highest-priority task that has been ready the longest without consuming its time slice UEE 3303 18 YL Huang Spring‘14 © NCTU Priority Based FIFO Scheduling high priority low FIFO list of ready tasks Ready CPU Scheduler processor time active UEE 3303 19 YL Huang Spring‘14 © NCTU Priority Based FIFO Scheduling high priority low FIFO list of ready tasks Ready CPU Scheduler processor time active UEE 3303 20 YL Huang Spring‘14 © NCTU
  • 92.
    6 Priority BasedFIFO Scheduling high priority low FIFO list of ready tasks Ready CPU Scheduler processor time active UEE 3303 21 YL Huang Spring‘14 © NCTU Round-Robin Scheduling 75ms Task 1 Task 2 50ms Same Priority Time Slice = 50ms Task 3 60ms Ready time Task1 Task2 Task3 Task1 Task3 T0 50ms 100ms 150ms 200ms time UEE 3303 22 YL Huang Spring‘14 © NCTU MQX Tasks ° Tasks can be automatically created when MQX Starts; also, any task can create another task by calling _task_create() or _task_create_blocked() ° The function _task_create() puts the child task in the ready state and the scheduler puts the higher priority task to run ° If _task_create_blocked is used the task is not ready until _task_ready() is called _task_abort _task_destroy Terminated _task_create Active Ready _task_block Blocked _task_ready UEE 3303 23 YL Huang Spring‘14 © NCTU Creating a Task ° When creating a task you have to: ! Make the task prototype and index definition #define INIT_TASK 5 extern void init_task(uint_32); ! Add the task in the Task Template List TASK_TEMPLATE_STRUCT MQX_template_list[] = { { TASK_INDEX, TASK, STACK, TASK_PRIORITY, TASK_NAME, TASK_ATTRIBUTES, CREATION_PARAMETER, TIME_SLICE} } Using the init_task example: TASK_TEMPLATE_STRUCT MQX_template_list[] = { {INIT_TASK, init_task, 1500, 9, init, MQX_AUTO_START_TASK, 0, 0}, } UEE 3303 24 YL Huang Spring‘14 © NCTU
  • 93.
    7 Creating aTask ° When creating a task you have to: ! Make the task definition void init_task(void) { /* Put the Task Code here */ } ! During execution time, create the task using task_create() (if it is not an autostart task) UEE 3303 25 YL Huang Spring‘14 © NCTU MQX_Template_List { WORLD_ID, world_task, 0x3000, 9, world_task, MQX_AUTO_START_TASK, 0L, 0}, { HELLO_ID, hello_task, 0x1000, 8, “hello_task, MQX_TIME_SLICE_TASK, 0L, 100}, { LED_ID, led_task, 0x2000, 10, “LED Task, MQX_AUTO_START_TASK | MQX_TIME_SLICE_TASK, 0L, 50}, UEE 3303 26 YL Huang Spring‘14 © NCTU MQX - Task Management Example void init_task(void) { _task_create(0,TASK_A,0); ... _task_ready(Task_B); ... } {INIT_TASK, init_task, 1500, 11, init, MQX_AUTO_START_TASK, 0, 0}, void Task_A(void) { ... _task_create_blocked(0,TASK_B,0); ... _task_abort(TASK_A); } void Task_B(void) { ... _task_abort(TASK_B); } init_task is created when MQX starts CPU Time {TASK_A, Task_A, 1500, 10, “Task A, 0, 0, 0}, {TASK_B, Task_B, 1500, 9, “Task B, 0, 0, 0}, UEE 3303 27 YL Huang Spring‘14 © NCTU Freescale MQX™ Documentation ° MQXUG User Guide ° MQXRM Reference Manual ° MQXUSBHOSTAPIRM USB Host API Reference Manual ° MQXUSBDEVAPI USB Device API Reference ° MQXUSBHOSTUG USB Host User Guide ° MQXRTCSUG RTCS User Guide ° MQXMFSUG File System User Guide ° MQXIOUG I/O Drivers User Guide ° MQXFS Software Solutions Fact Sheets UEE 3303 28 YL Huang Spring‘14 © NCTU
  • 94.
    8 Further Readingand Training ° TWR-MCF51CN-KIT Lab Document ° MCF5225x – Lab Document ° MQX Release Notes ° MQX User’s Guide ° Writing First MQX Application (AN3905) ° Using MQX: RTCS, USB, and MFS (AN3907) ° How to Develop I/O Drivers for MQX (AN3902) UEE 3303 29 YL Huang Spring‘14 © NCTU Further Reading and Training (Cont.) ° Videos: www.freescale.com/mqx ! MCF5225x Freescale MQX introduction ! Getting started with MCF5225x and Freescale MQX Lab Demos ! And more ° vFTF technical session videos www.freescale.com/vftf ! Introducing a modular system, Serial-to-Ethernet V1 ColdFire® MCU and Complimentary MQX™ RTOS ! Writing First MQX Application ! Implementing Ethernet Connectivity with the complimentary Freescale MQX™ RTOS UEE 3303 30 YL Huang Spring‘14 © NCTU In Summary By now, you should be able to: ° Understand what an RTOS is and how they can be used ° Create tasks and schedule them using MQX ° Create your own MQX applications UEE 3303 31 YL Huang Spring‘14 © NCTU 31