This document contains Sharath Kulal's resume. It summarizes his objective to obtain a position in hardware design and verification. It lists his education qualifications including a post graduation diploma in VLSI from CDAC ACTS in 2013 and a BE in Electronics from Pune University in 2011. It details his professional experience working on hardware testing, digital design, design verification, and as an IC design engineer. It lists his skills in languages, hardware design tools, protocols, and operating systems. It provides details of projects he has worked on including TCAM compiler and processor verification, hardware design kits, implementing an AMBA AHB bus protocol, and single error correction with double error detection.

1. SHARATH KULAL
B-432, Sector-2, Airoli(w), Navi Mumbai- 400708.
Email: kulalsharath@gmail.com
Mobile: +91-9773395371
Objective:
To procure a challenging position in the field of hardware design and verification.
Education:
Post Graduation Diploma (VLSI) February 2013.
CDAC ACTS (ATC), TICA, Mumbai.
BE Electronics May, 2011.
Pune University, PREC, Loni.
Diploma in Industrial Electronics June, 2005.
MSBTE, Shreeram Polytechnic, Airoli.
Professional Experience:
Kitek Technologies Pvt. Ltd.,
Designation: Hardware Testing Engineer ( August 2009 - August 2012)
* Quality control and Testing of microprocessor 8086 & 8051 kits.
* Testing and suggested possible improvement required to remove bugs in hardware of VLSI
starter’s kits(Spartan 3 and xc9500cpld), Analog & Data communication trainer kits, protocol
trainer kits and instrumentation & control lab trainer kits.
Designation: Digital Designer (FPGA) (May 2013 - February 2014)
* RTL Designing, Verification, Emulation of hardware Designed.
Amboseli Professional Associates Pvt. Ltd. (contractor at Broadcom, Mumbai)
Desgination: Design Verification Trainee (April 2014 - April 2015)
* Worked on functional verification of TCAM memories of Processor by writing Testcases and
modifying testbench using verilog and sytemverilog.
* Equivalence checking of circuit vs verilog using ESPCV tool of synopsys for 28nm TCAM
using GV flow.
Broadcom Communication Pvt. Ltd / Broadcom Limited.
Designation: Engineer, IC Design (March 2015 - present)
* Worked on functional verification of TCAM memories of Processor by writing Testcases and
modifying testbench using verilog and sytemverilog.
* Equivalence checking of circuit vs verilog using ESPCV tool of synopsys for 28nm and 16nm
TCAM using GV/TCL flow.
Skills:
Languages: C, C++, Intel 8085/8051 Assembly Language, vhdl, verilog, systemverilog.
Hardware design tools: Xilinx project navigator 14.2, mentor graphic hdl designer,
modelsim and questasim , espcv synopsys, vcs compiler, verdi waveform viewer.
Protocols worked :
* Communication: ASK, PSK, FSK, QAM, QPSK.
* Memories: TCAM, PDP(SRAM).
Operating System:
Microsoft Windows, UNIX.
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2. SHARATH KULAL
B-432, Sector-2, Airoli(w), Navi Mumbai- 400708.
Email: kulalsharath@gmail.com
Mobile: +91-9773395371
Significant coursework:
Advanced digital design, System Architecture, vhdl/ Verilog logic synthesis,
Cmos VLSI design.
Project Details
TCAM compiler and processor: (duration: ongoing , no. of Engineers:-5)
* Developed a testplan and setup the testbench and the environment.
* Filed bug reports, verified rtl fixes, analyzed test results and performed coverage analysis.
* Wrote test cases using verilog and systemverilog to test the functionality of the modules.
* Debugged rtl using simulators like Synopsys VCS.
* Performed the ESPCV verification for various test Scenarios for 28nm and 16nm compilers
using GV/TCL flows.
* Involved in writing and modifying Perl scripts.
KITEK ACT-XX, VLS-08, IC-33, : (duration:-9 months, no. of Engineers:-3)
* Worked on modules for performing various digital communication processes.
* Successfully designed dual counter with debouncing logic on trigger and decoder module on
cpld.
* Successfully designed the module for HyperTerminal communication, Keyboard interface
and VGA Interface.
.
AMBA AHB BUS: (duration:-6months, no. of engineers:-5)
* Worked to implement a bus using AMBA AHB protocol with 1 masters and 2 slaves, arbiter
and decoder.
SECDED
(Single error correction double error detection): (duration:-3months, no. of
engineers:-3)
* Designed a Verilog module for single bit error correction and double error detection by
hamming coding and decoding technique.
Extracurricular activities and achievements
* Participated in interschool level Athletics Competition.
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