This document summarizes the topics covered in Session 13 of the CS304PC course on Computer Organization and Architecture. It discusses various addressing modes including implied, immediate, register, autoincrement, autodecrement, direct, indirect, relative, indexing, and base register addressing modes. For each mode, it provides an explanation of how the effective address is computed. It also previews that the next session will cover data transfer and manipulation instructions.
Direct and Indirect Address, addressing modes; Arithmetic Logic Units control and data path, data path components, design of ALU and data path, Stack Organization, discussions about RISC versus CISC architectures, controller design; Hardwired and Micro programmed Control
Direct and Indirect Address, addressing modes; Arithmetic Logic Units control and data path, data path components, design of ALU and data path, Stack Organization, discussions about RISC versus CISC architectures, controller design; Hardwired and Micro programmed Control
A computer instruction is a binary code that specifies a sequence of micro operations for the computer.
Instruction codes together with data are stored in memory.
The computer reads each instruction from memory and places it in a control register.
The control unit then interprets the binary code of the instruction and proceeds to execute it by issuing a sequence of micro operations.
CCS335 _ Neural Networks and Deep Learning Laboratory_Lab Complete RecordAsst.prof M.Gokilavani
LIST OF EXPERIMENTS:
1. Implement simple vector addition in Tensor Flow.
2. Implement a regression model in Keras.
3. Implement a perception in TensorFlow/Keras Environment.
4. Implement a Feed Forward Network in TensorFlow/Keras.
5. Implement an image classifier using CNN in TensorFlow/Keras.
6. Improve the deep Learning model by fine tuning hyper parameters.
7. Implement a Transfer Learning concept in image classification.
8. Using a pre trained model on Keras for transfer learning.
9. Perform Sentimental Analysis using RNN.
10. Implement an LSTM based Auto encoding inTensorflow/Keras.
11. Image generation using GAN.
ADDITIONAL EXPERIMENTS
12. Train a deep Learning model to classify a given image using pre trained model.
13. Recommendation system from sales data using Deep Learning.
14. Implement Object detection using CNN.
15. Implement any simple Reinforcement Algorithm for an NLP problem.
A computer instruction is a binary code that specifies a sequence of micro operations for the computer.
Instruction codes together with data are stored in memory.
The computer reads each instruction from memory and places it in a control register.
The control unit then interprets the binary code of the instruction and proceeds to execute it by issuing a sequence of micro operations.
CCS335 _ Neural Networks and Deep Learning Laboratory_Lab Complete RecordAsst.prof M.Gokilavani
LIST OF EXPERIMENTS:
1. Implement simple vector addition in Tensor Flow.
2. Implement a regression model in Keras.
3. Implement a perception in TensorFlow/Keras Environment.
4. Implement a Feed Forward Network in TensorFlow/Keras.
5. Implement an image classifier using CNN in TensorFlow/Keras.
6. Improve the deep Learning model by fine tuning hyper parameters.
7. Implement a Transfer Learning concept in image classification.
8. Using a pre trained model on Keras for transfer learning.
9. Perform Sentimental Analysis using RNN.
10. Implement an LSTM based Auto encoding inTensorflow/Keras.
11. Image generation using GAN.
ADDITIONAL EXPERIMENTS
12. Train a deep Learning model to classify a given image using pre trained model.
13. Recommendation system from sales data using Deep Learning.
14. Implement Object detection using CNN.
15. Implement any simple Reinforcement Algorithm for an NLP problem.
CCS355 Neural Networks & Deep Learning Unit 1 PDF notes with Question bank .pdfAsst.prof M.Gokilavani
UNIT I INTRODUCTION
Neural Networks-Application Scope of Neural Networks-Artificial Neural Network: An IntroductionEvolution of Neural Networks-Basic Models of Artificial Neural Network- Important Terminologies of
ANNs-Supervised Learning Network.
Online aptitude test management system project report.pdfKamal Acharya
The purpose of on-line aptitude test system is to take online test in an efficient manner and no time wasting for checking the paper. The main objective of on-line aptitude test system is to efficiently evaluate the candidate thoroughly through a fully automated system that not only saves lot of time but also gives fast results. For students they give papers according to their convenience and time and there is no need of using extra thing like paper, pen etc. This can be used in educational institutions as well as in corporate world. Can be used anywhere any time as it is a web based application (user Location doesn’t matter). No restriction that examiner has to be present when the candidate takes the test.
Every time when lecturers/professors need to conduct examinations they have to sit down think about the questions and then create a whole new set of questions for each and every exam. In some cases the professor may want to give an open book online exam that is the student can take the exam any time anywhere, but the student might have to answer the questions in a limited time period. The professor may want to change the sequence of questions for every student. The problem that a student has is whenever a date for the exam is declared the student has to take it and there is no way he can take it at some other time. This project will create an interface for the examiner to create and store questions in a repository. It will also create an interface for the student to take examinations at his convenience and the questions and/or exams may be timed. Thereby creating an application which can be used by examiners and examinee’s simultaneously.
Examination System is very useful for Teachers/Professors. As in the teaching profession, you are responsible for writing question papers. In the conventional method, you write the question paper on paper, keep question papers separate from answers and all this information you have to keep in a locker to avoid unauthorized access. Using the Examination System you can create a question paper and everything will be written to a single exam file in encrypted format. You can set the General and Administrator password to avoid unauthorized access to your question paper. Every time you start the examination, the program shuffles all the questions and selects them randomly from the database, which reduces the chances of memorizing the questions.
Literature Review Basics and Understanding Reference Management.pptxDr Ramhari Poudyal
Three-day training on academic research focuses on analytical tools at United Technical College, supported by the University Grant Commission, Nepal. 24-26 May 2024
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Low power architecture of logic gates using adiabatic techniquesnooriasukmaningtyas
The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips of very high density, has recently led to rapid and inventive progresses in low-power design. The most effective technique is adiabatic logic circuit design in energy-efficient hardware. This paper presents two adiabatic approaches for the design of low power circuits, modified positive feedback adiabatic logic (modified PFAL) and the other is direct current diode based positive feedback adiabatic logic (DC-DB PFAL). Logic gates are the preliminary components in any digital circuit design. By improving the performance of basic gates, one can improvise the whole system performance. In this paper proposed circuit design of the low power architecture of OR/NOR, AND/NAND, and XOR/XNOR gates are presented using the said approaches and their results are analyzed for powerdissipation, delay, power-delay-product and rise time and compared with the other adiabatic techniques along with the conventional complementary metal oxide semiconductor (CMOS) designs reported in the literature. It has been found that the designs with DC-DB PFAL technique outperform with the percentage improvement of 65% for NOR gate and 7% for NAND gate and 34% for XNOR gate over the modified PFAL techniques at 10 MHz respectively.
Understanding Inductive Bias in Machine LearningSUTEJAS
This presentation explores the concept of inductive bias in machine learning. It explains how algorithms come with built-in assumptions and preferences that guide the learning process. You'll learn about the different types of inductive bias and how they can impact the performance and generalizability of machine learning models.
The presentation also covers the positive and negative aspects of inductive bias, along with strategies for mitigating potential drawbacks. We'll explore examples of how bias manifests in algorithms like neural networks and decision trees.
By understanding inductive bias, you can gain valuable insights into how machine learning models work and make informed decisions when building and deploying them.
Water billing management system project report.pdfKamal Acharya
Our project entitled “Water Billing Management System” aims is to generate Water bill with all the charges and penalty. Manual system that is employed is extremely laborious and quite inadequate. It only makes the process more difficult and hard.
The aim of our project is to develop a system that is meant to partially computerize the work performed in the Water Board like generating monthly Water bill, record of consuming unit of water, store record of the customer and previous unpaid record.
We used HTML/PHP as front end and MYSQL as back end for developing our project. HTML is primarily a visual design environment. We can create a android application by designing the form and that make up the user interface. Adding android application code to the form and the objects such as buttons and text boxes on them and adding any required support code in additional modular.
MySQL is free open source database that facilitates the effective management of the databases by connecting them to the software. It is a stable ,reliable and the powerful solution with the advanced features and advantages which are as follows: Data Security.MySQL is free open source database that facilitates the effective management of the databases by connecting them to the software.
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesChristina Lin
Traditionally, dealing with real-time data pipelines has involved significant overhead, even for straightforward tasks like data transformation or masking. However, in this talk, we’ll venture into the dynamic realm of WebAssembly (WASM) and discover how it can revolutionize the creation of stateless streaming pipelines within a Kafka (Redpanda) broker. These pipelines are adept at managing low-latency, high-data-volume scenarios.
CS304PC:Computer Organization and Architecture Session 13 Addressing modes.pptx
1. CS304PC:Computer Organization
and Architecture (R18 II(I sem))
Department of computer science and engineering
(AI/ML)
Session 13
by
Asst.Prof.M.Gokilavani
VITS
1/12/2023 Department of CSE (AI/ML) 1
2. TEXTBOOK:
• 1. Computer System Architecture – M. Moris Mano, Third Edition,
Pearson/PHI.
REFERENCES:
• Computer Organization – Car Hamacher, Zvonks Vranesic, Safea
Zaky, Vth Edition, McGraw Hill.
• Computer Organization and Architecture – William Stallings Sixth
Edition, Pearson/PHI.
• Structured Computer Organization – Andrew S. Tanenbaum, 4th
Edition, PHI/Pearson.
1/12/2023 Department of CSE (AI/ML) 2
3. Unit II
Microprogrammed Control: Control memory, Address sequencing,
micro program example, Design of Control unit .
Central Processing Unit : General Register Organization, Stack
organization, Instruction formats, Addressing modes, Data Transfer and
Manipulation, Program Control.
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4. Topics covered in session 13
1/12/2023 Department of CSE (AI/ML) 4
• General Register Organization
• Instruction formats
• Addressing modes
• Data Transfer and Manipulation
• Program Control.
5. Addressing modes
The addressing mode specifies a rule for interpreting or modifying the address
field of the instruction before the operand is referenced.
Computers use addressing mode techniques for the purpose of
accommodating one or both of the following provisions:
1. To give programming versatility to the user by providing such facilities as
pointers to memory, counters for loop control, indexing of data, and
program relocation.
2. To reduce the number of bits in the addressing field of the instruction.
The control unit of a computer is designed to go through an instruction cycle
that is divided into three major phases:
1.Fetch the instruction from memory.
2.Decode the instruction.
3.Execute the instruction.
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6. Types of Address Modes
• Implied mode
• Immediate mode
• Register mode
• Autoincrement and Autodecrement mode
• Direct Address mode
• Indirect Address mode
• Relative address mode
• Indexing addressing mode
• Base register Addressing mode
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7. Types of Address Modes
i. Implied mode:
• In this mode the operands are specified implicitly in the definition of the
instruction. For example, the instruction "complement accumulator" is an
implied-mode instruction because the operand in the accumulator register is
implied in the definition of the instruction.
• In fact, all register reference instructions that use an accumulator are implied-
mode instructions.
• Zero address instructions in a stack-organized computer are implied-mode
instructions since the operands are implied to be on top of the stack.
1/12/2023 Department of CSE (AI/ML) 7
8. ii. Immediate mode: An immediate mode instruction has an operand
field rather than an address field.
• The operand field contains the actual operand to be used in
conjunction with the operation specified in the instruction.
• Immediate-mode instructions are useful for initializing registers to a
constant value.
iii. Register Mode: In this mode the operands are in registers that reside
within the CPU. The particular register is selected from a register field in the
instruction. A k - bit field can specify any one of 2^k registers.
• Register Indirect Mode: In this mode the instruction specifies a register in the
CPU whose contents give the address of the operand in memory.
• The advantage of a register indirect mode instruction is that the address
field of the instruction uses fewer bits to select a register than would have been
required to specify a memory address directly.
1/12/2023 Department of CSE (AI/ML) 8
9. iv. Autoincrement and Autodecrement: This is similar to the register
indirect mode except that the register is incremented or decremented after
(or before) its value is used to access memory.
• When the address stored in the register refers to a table of data in
memory, it is necessary to increment or decrement the register after every
access to the table.
• The address field of an instruction is used by the control unit in the CPU
to obtain the operand from memory.
• The effective address is defined to be the memory address obtained from
the computation dictated by the given addressing mode.
• The effective address is the address of the operand in a computational-
type instruction. It is the address where control branches in response to a
branch-type instruction.
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10. v. Direct Address mode: In this mode the effective address is equal to the
address part of the instruction.
• The operand resides in memory and its address is given directly by the
address field of the instruction.
• In a branch-type instruction the address field specifies the actual branch
address.
vi. Indirect address mode: In this mode the address field of the
instruction gives the address where the effective address is stored in
memory. Control fetches the instruction from memory and uses its address
part to access memory again to read the effective address.
• The effective address in these modes is obtained from the following
computation: effective address = address part of instruction + content of
CPU register.
1/12/2023 Department of CSE (AI/ML) 10
11. vii. Relative address mode: In this mode the content of the program counter
is added to the address part of the instruction in order to obtain the effective
address.
• The address part of the instruction is usually a signed number (in 2's
complement representation) which can be either positive or negative.
• When this number is added to the content of the program counter, the result
produces an effective address whose position in memory is relative to the
address of the next instruction.
• Example: Assume that the program counter contains the number 825, and
the address part of the instruction contains the number 24. The instruction at
location 825 is read from memory during the fetch phase and the program
counter is then incremented by one to 826. The effective address
computation for the relative address mode is 826 + 24 = 850.
1/12/2023 Department of CSE (AI/ML) 11
12. viii. Indexing addressing mode:
In this mode the content of an index register is added to the address part of
the instruction to obtain the effective address.
The index register is a special CPU register that contains an index value.
The address field of the instruction defines the beginning address of a data
array in memory.
Each operand in the array is stored in memory relative to the beginning
address.
The distance between the beginning address and the address of the
operand is the index value stored in the index register.
Any operand in the array can be accessed with the same instruction
provided that the index register contains the correct index value. The
index register can be incremented to facilitate access to consecutive
operands.
1/12/2023 Department of CSE (AI/ML) 12
13. ix. Base Register addressing mode:
• In this mode the content of a base register is added to the address part of the
instruction to obtain the effective address.
• This is similar to the indexed addressing mode except that the register is now
called a base register instead of an index register. The difference between the
two modes is in the way they are used rather than in the way that they are
computed.
• An index register is assumed to hold an index number that is relative to the
address part of the instruction.
• A base register is assumed to hold a base address and the address field of the
instruction gives a displacement relative to this base address.
• With a base register, the displacement values of instructions do not have to
change. Only the value of the base register requires updating to reflect the
beginning of a new memory segment.
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14. Topics to be covered in next session 14
• Data transfer and Manipulation
1/12/2023 Department of CSE (AI/ML) 14
Thank you!!!