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Nikhil Sharma
M.Tech in VLSI Design, Mobile: +91-9023882653
Vill. Dhanoa, PO Dhaneta, Teh Nadaun Email: sankhyan.info@gmail.com
Distt. Hamirpur(H.P.) – 177041.
Seeking a position with an organization where I can contribute my skills for organization’s success
and synchronize with new technology while being resourceful, innovative and flexible.
 EDA Tools : Mentor Graphics, Multisim,, KEIL
Tanner Tools.
 Hardware Description Languages : VHDL, Verilog.
 Software Skills : C, C++.
 Platforms : UNIX, Windows.
 Architectures : µP 8085, µC 8051.
 Assembly Programming : µP 8085, µC 8051.
 Hardware Expertise : Sparten 6 FPGA Board (Processor Based System Design)
 Mathematical Tools : MATLAB.
Digital Design, Microprocessors, Microcontrollers & Interfacing, Embedded Systems, Computer
Organization & Architecture, FPGA Based System Design, Low Power CMOS VLSI Design,
Microelectronics, VLSI Digital Signal Processing Systems.
Degree Board / University Year CGPA / Percentage
M.Tech [VLSI Design]
Thapar University
Patiala (PB)
2013 -
2015
6.67/10
Till Now
B.Tech [ECE] PTU Jalandher (PB) 2006 -
2010
69.93 %
12th HP Board
Dharamsala
2006 63.7%
10th HP Board
Dharamsala
2004 69.7%
Objective
Skill Set
Technical Expertise
Academic Profile
 Secured Score of 436 with 9608th rank among 2,50,000 aspirants in GATE’ 2013.
 Currently working on Residue Number System Based Processor under Ms Sakshi at Thapar
University Patiala.
M.Tech Project
1) Title: Residue Number System Scaler.
Abstract: Scaling in RNS has always been conceived as a performance bottleneck similar to
the residue-to-binary conversion problem due to the inefficient intermodulo operation. In this
project, a simple and fast scaling algorithm for the three-moduli set {2n
- 1, 2n
, 2n
+ 1} RNS
is designed. The complexity of intermodulo operation has been resolved by a new
formulation of scaling an integer in RNS domain by one of its moduli.
Team Size: 1
B.Tech. Major Project
1) Title: Automatic Car Parking System using Microcontroller Team Size: 4
2) Title: Automatic Car Parking System without microcontroller Team Size:4
B.Tech. Mini Project
1) Title: Transistor Identifier Team Size:1
2) Title: Voltage Regulator
 One year work experience in “SURYA TELECOM PVT. LTD. Panchkula” as an
Assistant Engineer (1st
May,2011-12th
May, 2012 )
Profile: Testing Engineer
 Hard working and good at team work.
 Rapid at learning things.
 Represent Thapar University in Inter Engineering Vollyball Championship
Ms Sakshi
Assistant Professor
Electronics and Communication Engineering Department
Thapar University Patiala
Achievements
Current status
Projects
Work Experience
Personal Strengths
extra curricular activities
Reference
Phone: 91-9915155583 E-mail: sakshi.bajaj@thapar.edu

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resume

  • 1. Nikhil Sharma M.Tech in VLSI Design, Mobile: +91-9023882653 Vill. Dhanoa, PO Dhaneta, Teh Nadaun Email: sankhyan.info@gmail.com Distt. Hamirpur(H.P.) – 177041. Seeking a position with an organization where I can contribute my skills for organization’s success and synchronize with new technology while being resourceful, innovative and flexible.  EDA Tools : Mentor Graphics, Multisim,, KEIL Tanner Tools.  Hardware Description Languages : VHDL, Verilog.  Software Skills : C, C++.  Platforms : UNIX, Windows.  Architectures : µP 8085, µC 8051.  Assembly Programming : µP 8085, µC 8051.  Hardware Expertise : Sparten 6 FPGA Board (Processor Based System Design)  Mathematical Tools : MATLAB. Digital Design, Microprocessors, Microcontrollers & Interfacing, Embedded Systems, Computer Organization & Architecture, FPGA Based System Design, Low Power CMOS VLSI Design, Microelectronics, VLSI Digital Signal Processing Systems. Degree Board / University Year CGPA / Percentage M.Tech [VLSI Design] Thapar University Patiala (PB) 2013 - 2015 6.67/10 Till Now B.Tech [ECE] PTU Jalandher (PB) 2006 - 2010 69.93 % 12th HP Board Dharamsala 2006 63.7% 10th HP Board Dharamsala 2004 69.7% Objective Skill Set Technical Expertise Academic Profile
  • 2.  Secured Score of 436 with 9608th rank among 2,50,000 aspirants in GATE’ 2013.  Currently working on Residue Number System Based Processor under Ms Sakshi at Thapar University Patiala. M.Tech Project 1) Title: Residue Number System Scaler. Abstract: Scaling in RNS has always been conceived as a performance bottleneck similar to the residue-to-binary conversion problem due to the inefficient intermodulo operation. In this project, a simple and fast scaling algorithm for the three-moduli set {2n - 1, 2n , 2n + 1} RNS is designed. The complexity of intermodulo operation has been resolved by a new formulation of scaling an integer in RNS domain by one of its moduli. Team Size: 1 B.Tech. Major Project 1) Title: Automatic Car Parking System using Microcontroller Team Size: 4 2) Title: Automatic Car Parking System without microcontroller Team Size:4 B.Tech. Mini Project 1) Title: Transistor Identifier Team Size:1 2) Title: Voltage Regulator  One year work experience in “SURYA TELECOM PVT. LTD. Panchkula” as an Assistant Engineer (1st May,2011-12th May, 2012 ) Profile: Testing Engineer  Hard working and good at team work.  Rapid at learning things.  Represent Thapar University in Inter Engineering Vollyball Championship Ms Sakshi Assistant Professor Electronics and Communication Engineering Department Thapar University Patiala Achievements Current status Projects Work Experience Personal Strengths extra curricular activities Reference
  • 3. Phone: 91-9915155583 E-mail: sakshi.bajaj@thapar.edu