Most spurs were below the noise floor of the spectrum analyzer (span = 1 kHz; RBW = 6.1 Hz). Only noise was measured at these frequencies. Fixed PFD frequency (unoptimized) is shown for comparison. Spur at 5162.75 MHz is simulated but doesn’t appear in measurement. This is because the simulator calculates worst case spurs.
6000 output frequencies. Only a very narrow range of output frequencies have spurs above -90 dBc. This range is ≈2 MHz wide around 2 × master clock. Recommended solutions in Analysis section. Most frequencies have spurs below -100 dBc! Typical requirement ≈ -70 – -80 dBc.
“ADF4355/5355 broadband devices offering phase control features cover sub-13GHz 5G and MIMO channels and when combined with ADIsimFrequencyPlanner offer excellent spectral spur performance”
Can also implement with PLLVCO in int-N mode as source.
ADIsimFrequencyPlanner can simulate and optimize a wide frequency range system in seconds. Manually, this can take days or even weeks. ADIsimFrequencyPlanner optimization makes more channels in a range usable – this increases value for money in expensive frequency spectrums. ADIsimFrequencyPlanner results are very close to measured results. ADIsimFrequencyPlanner is a free, small (<1 MB) application which runs on all Windows machines.
PLL frequency planning for spurious signal elimination
► A PLL (Phase Locked Loop) and VCO (Voltage Controlled Oscillator) outputs an RF signal
at a certain frequency. Ideally, there is only one signal present. In reality, there are
unwanted spurious signals and phase noise at the output.
► The problem:
High spurs → Unusable channels → Wasted money and lower efficiency
► The solution:
Frequency planning → All channels usable → Better value for money and better efficiency
Introduction to integer boundary spurs
► All PLLVCOs exhibit integer boundary spurs.
Integer boundary spurs (IBS) occur at frequencies related to integer multiples of the Phase Frequency
Detector (PFD) frequency.
IBS are stronger when the output frequency is near an integer boundary frequency.
In the PLL loop below, there will be an IBS at ±1 MHz offset from the RF output.
Varying the PFD comparison frequency
► Changing PFD comparison frequency changes where integer boundary spurs occur
► Optimum PFD frequency is the frequency whose integer multiple is furthest from the desired
► For each output frequency, use the optimum PFD frequency
► A range of PFD frequencies can be generated by:
1. Varying the reference frequency
2. Varying the R divider
3. Combining both 1 and 2
How to vary the PFD frequency
► Option 1: Programmable reference source (clock
distribution chip with programmable output dividers)
► Option 2: PLLVCO in integer mode (no integer
• Varying the R divider
fREF = 491.52 MHz
User specifies the desired output range and channel steps
At every step, ADIsimFrequencyPlanner selects the optimum PFD frequency and
then simulates the worst case 1st and 2nd order integer boundary spur powers
ADIsimFrequencyPlanner returns the optimum reference source and PLLVCO
configuration for each output frequency
The charge pump current is also set to maintain a constant loop bandwidth across the frequency range.
ADIsimFrequencyPlanner generates a series of plots to show what is happening
Settings are output for each channel step
Assuming clock generator master clock = 2949.12 MHz
• For RFOUT = 4818.25 MHz, set:
• Clock generator output divider (M) to 14.
• PLLVCO reference divider (R) to 3.
• Charge pump current to 1.68 mA to maintain
constant loop bandwidth.
Max possible spur power at each output frequency
6000 output frequencies shown 4800 - 6300 MHz
Plot shows the worst IBS at each output frequency step.
Phase noise at 5898.25 MHz with worst spur
Single frequency phase noise view: worst spur at
-55.3 dBc is shown at 10 kHz offset from the carrier.
• Carrier: 5898.25 MHz = 61.44 MHz × 96.00016276
• IBS = 61.44 MHz × 96 = 5898.24 MHz → 10 kHz offset
►Using ADIsimFrequencyPlanner, combined with Analog Devices clocking
devices and PLL synthesizers, can virtually eliminate all problematic spurs.
Over 4.8 GHz to 6.3 GHz, in 250 kHz steps (6000 channels), there can be almost no
integer boundary spur.
This translates to higher spectral efficiency and better value for money.
►To implement a similar system, consider using:
HMC7044: 3.2 GHz 14 output clock generation device.
ADF4355: 54 MHz – 6.8 GHz PLLVCO with output phase control.
ADF5355: 54 MHz – 13.6 GHz PLLVCO with output phase control.
Free download: www.analog.com/adisimfrequencyplanner
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• VCO: produces high frequency signal.
• N divider: divides down VCO output signal.
• R divider: divides down reference signal to generate PFD clock.
• PFD: compares phase of R divider output and N divider output.
• Charge pump: pumps up or down depending on PFD comparison result.
• Loop filter: smoothes charge pump current to produce VCO control voltage.
Charge pump current vs. frequency for constant loop bandwidth
►The PLLVCO was the HMC704 (PLL) and ADF5355 (VCO).
►Process for each step:
ADF5355 locks to desired frequency using internal PLL.
ADF5355 internal PLL is disabled.
HMC704 then locks the ADF5355 VCO.
HMC704 has lower phase noise and lower spurs.
Isolating the PLL and VCO (separate chips) improves spurs.
►Loop bandwidth ≈ 17 kHz.
►Phase margin ≈ 49°.
Results – zoomed in on only high IBS region
5898.5, -74 5898.75, -77.2
5895 5895.5 5896 5896.5 5897 5897.5 5898 5898.5 5899 5899.5 5900 5900.5 5901
Output frequency (MHz)
HMC7044 + ADF5355 + HMC704
Measured (worst of 1st and 2nd order IBS)
Simulated (optimized PFD freq).
• At an output frequency of 5898.25 MHz, the worst IBS is -54.9 dBc.
• At an output frequency of 5898.50 MHz, the worst IBS is -74.0 dBc.
• At an output frequency of 5898.75 MHz, the worst IBS is -77.2 dBc…
►Over 4.8 GHz to 6.3 GHz, in 250 kHz steps (6000 channels), there can be almost
no integer boundary spur.
►There is only one very narrow range of frequencies where optimizing the PFD
frequency doesn’t improve the IBS performance. This frequency range is twice the
system master clock frequency (2949.12 MHz × 2 = 5898.24 MHz).
At this frequency, it is recommended to shift the carrier frequency to nearby cleaner frequency
and then, shift the baseband frequency in digital (NCO) to compensate.
An alternate scheme, would change the master clock frequency (if possible in the system) by
some amount to result in a clean output frequency.