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Ims2016 micro apps_robertbrennan_pll_frequencyplanning_v2

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PLL Frequency Planning for Spurious Signal Elimination: IMS2016 Presentation

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Ims2016 micro apps_robertbrennan_pll_frequencyplanning_v2

  1. 1. IMS2016 MicroApps PLL frequency planning for spurious signal elimination Robert Brennan Analog Devices  10:20
  2. 2. Introduction ► A PLL (Phase Locked Loop) and VCO (Voltage Controlled Oscillator) outputs an RF signal at a certain frequency. Ideally, there is only one signal present. In reality, there are unwanted spurious signals and phase noise at the output. ► The problem:  High spurs → Unusable channels → Wasted money and lower efficiency ► The solution:  Frequency planning → All channels usable → Better value for money and better efficiency 2
  3. 3. Introduction to integer boundary spurs ► All PLLVCOs exhibit integer boundary spurs.  Integer boundary spurs (IBS) occur at frequencies related to integer multiples of the Phase Frequency Detector (PFD) frequency.  IBS are stronger when the output frequency is near an integer boundary frequency.  In the PLL loop below, there will be an IBS at ±1 MHz offset from the RF output. 3
  4. 4. Integer boundary spur at 1 MHz offset 4
  5. 5. Integer boundary spur at 10 MHz offset 5  10:25
  6. 6. Varying the PFD comparison frequency ► Changing PFD comparison frequency changes where integer boundary spurs occur ► Optimum PFD frequency is the frequency whose integer multiple is furthest from the desired signal ► For each output frequency, use the optimum PFD frequency ► A range of PFD frequencies can be generated by: 1. Varying the reference frequency 2. Varying the R divider 3. Combining both 1 and 2 6
  7. 7. How to vary the PFD frequency ► Option 1: Programmable reference source (clock distribution chip with programmable output dividers) ► Option 2: PLLVCO in integer mode (no integer boundary spurs) 7 • Varying the R divider fREF = 491.52 MHz fPFD = [98.304, 81.92, 70.217, 61.44, 54.613] MHz
  8. 8. ADIsimFrequencyPlanner 8
  9. 9. ADIsimFrequencyPlanner flowchart 9 User specifies the desired output range and channel steps At every step, ADIsimFrequencyPlanner selects the optimum PFD frequency and then simulates the worst case 1st and 2nd order integer boundary spur powers ADIsimFrequencyPlanner returns the optimum reference source and PLLVCO configuration for each output frequency The charge pump current is also set to maintain a constant loop bandwidth across the frequency range. ADIsimFrequencyPlanner generates a series of plots to show what is happening
  10. 10. Settings are output for each channel step 10 Assuming clock generator master clock = 2949.12 MHz • For RFOUT = 4818.25 MHz, set: • Clock generator output divider (M) to 14. • PLLVCO reference divider (R) to 3. • Charge pump current to 1.68 mA to maintain constant loop bandwidth.
  11. 11. Max possible spur power at each output frequency 6000 output frequencies shown 4800 - 6300 MHz 11 Plot shows the worst IBS at each output frequency step.  10:30
  12. 12. [ Phase noise at 5898.25 MHz with worst spur 12 Single frequency phase noise view: worst spur at -55.3 dBc is shown at 10 kHz offset from the carrier. • Carrier: 5898.25 MHz = 61.44 MHz × 96.00016276 • IBS = 61.44 MHz × 96 = 5898.24 MHz → 10 kHz offset
  13. 13. Sweep results – measured worst spur power 13 -140 -120 -100 -80 -60 -40 -20 0 4800 4900 5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000 6100 6200 6300 Spurpower(dBc) Output frequency (MHz) HMC7044 + ADF5355 + HMC704 Measured (worst of 1st and 2nd order IBS) Simulated (optimized PFD freq). Simulated (fixed PFD freq.)
  14. 14. Reference and PFD settings vs VCO output frequency 14 Optimum reference and PFD frequency is shown for each output step. Reference frequency PFD frequency
  15. 15. Example implementation ►HMC7044 – Clock Generator  14 programmable outputs  JESD204B compliant  44 fs (12 kHz - 20 MHz) at 2457.6 MHz ►ADF4355 – integrated PLLVCO  54 – 6800 MHz  Phase noise comparable to discrete VCOs  Fully phase controllable
  16. 16. Conclusion ►Using ADIsimFrequencyPlanner, combined with Analog Devices clocking devices and PLL synthesizers, can virtually eliminate all problematic spurs.  Over 4.8 GHz to 6.3 GHz, in 250 kHz steps (6000 channels), there can be almost no integer boundary spur.  This translates to higher spectral efficiency and better value for money. ►To implement a similar system, consider using:  HMC7044: 3.2 GHz 14 output clock generation device.  ADF4355: 54 MHz – 6.8 GHz PLLVCO with output phase control.  ADF5355: 54 MHz – 13.6 GHz PLLVCO with output phase control.  Free download: www.analog.com/adisimfrequencyplanner 16  10:35
  17. 17. Question time Visit Analog Devices at Booth 1519 Robert Brennan RF Applications and Marketing
  18. 18. Appendix 18
  19. 19. PLL architecture 19 • VCO: produces high frequency signal. • N divider: divides down VCO output signal. • R divider: divides down reference signal to generate PFD clock. • PFD: compares phase of R divider output and N divider output. • Charge pump: pumps up or down depending on PFD comparison result. • Loop filter: smoothes charge pump current to produce VCO control voltage.
  20. 20. Charge pump current vs. frequency for constant loop bandwidth 20
  21. 21. R, M and VCO output divider settings 21
  22. 22. Comparing simulation with measured - setup
  23. 23. PLLVCO ►The PLLVCO was the HMC704 (PLL) and ADF5355 (VCO). ►Process for each step:  ADF5355 locks to desired frequency using internal PLL.  ADF5355 internal PLL is disabled.  HMC704 then locks the ADF5355 VCO.  HMC704 has lower phase noise and lower spurs.  Isolating the PLL and VCO (separate chips) improves spurs. ►Loop bandwidth ≈ 17 kHz. ►Phase margin ≈ 49°. 23
  24. 24. Results – zoomed in on only high IBS region 24 5898.25, -54.9 5898.5, -74 5898.75, -77.2 5899, -83.6 5899.25, -86.7 5899.5, -84.8 5899.75, -89.8 5900, -89.6 5900.25, -92.5 -140 -120 -100 -80 -60 -40 -20 0 5895 5895.5 5896 5896.5 5897 5897.5 5898 5898.5 5899 5899.5 5900 5900.5 5901 Spurpower(dBc) Output frequency (MHz) HMC7044 + ADF5355 + HMC704 Measured (worst of 1st and 2nd order IBS) Simulated (optimized PFD freq). • At an output frequency of 5898.25 MHz, the worst IBS is -54.9 dBc. • At an output frequency of 5898.50 MHz, the worst IBS is -74.0 dBc. • At an output frequency of 5898.75 MHz, the worst IBS is -77.2 dBc…
  25. 25. Analysis ►Over 4.8 GHz to 6.3 GHz, in 250 kHz steps (6000 channels), there can be almost no integer boundary spur. ►There is only one very narrow range of frequencies where optimizing the PFD frequency doesn’t improve the IBS performance. This frequency range is twice the system master clock frequency (2949.12 MHz × 2 = 5898.24 MHz).  At this frequency, it is recommended to shift the carrier frequency to nearby cleaner frequency and then, shift the baseband frequency in digital (NCO) to compensate.  An alternate scheme, would change the master clock frequency (if possible in the system) by some amount to result in a clean output frequency. 25
  26. 26. Cascaded mode – range of reference frequencies ► fPFD_1 = 61.44 MHz ► fREF_2 = [251.904, 253.44, 256, 258.048, 261.12, 264.192, 266.24, 268.8, 270.336, 276.48, 282.624, 284.16, 286.72, 288.768, 291.84, 294.912, 296.96, 299.52, 307.2, 314.88, 317.44, 322.56, 327.68, 330.24, 337.92, 345.6, 348.16] MHz 26

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