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Phase noise transfer functions,
ring vco, ring vco layout
Input to o/p transfer function VCO to o/p transfer function
VCO to o/p transfer function ICP
Loop filter noise (R) Power supply noise on VCO
Crystal oscillators have good phase noise
Ring based
oscillators
Power of a ring oscillator
For same frequency, total power independent of N
Refer to noise equation in above slide
Phase noise due to divider
Razavi LC vco design example !!
Noise due to cross coupled, tail current
source flicker noise for lc vco is not given
in razavi
Red are oscn and blue are oscp
capbank
varactors
Gm cell
Delay cell
Layout of vco • 4,1,3,2 are drawn and capacitively matched
• 8 wires are present vertically
• Pmos small is on the left and nmos (larger) on the right
• All vgnd and vssa connections are symmetric
• Sufficient distance so that wires can run vertically
• Capacitively matched until ac caps
Big cap layout • No clock signals on it
• Reference signals ok
• Strong grid
• Have to meet density rules
• Star connection to all important cells
• Ldi/dt not an issue since difference for delay
cells
• What about loop filter capacitor node ?
One more arrangement of ring oscillator
Our ring oscillator looked better
Effect of ground bounce
Variation is due to supply bounce

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Phase noise transfer functions.pptx

  • 1. Phase noise transfer functions, ring vco, ring vco layout
  • 2. Input to o/p transfer function VCO to o/p transfer function
  • 3. VCO to o/p transfer function ICP
  • 4. Loop filter noise (R) Power supply noise on VCO
  • 5. Crystal oscillators have good phase noise
  • 7. Power of a ring oscillator For same frequency, total power independent of N Refer to noise equation in above slide
  • 8. Phase noise due to divider
  • 9. Razavi LC vco design example !! Noise due to cross coupled, tail current source flicker noise for lc vco is not given in razavi
  • 10.
  • 11.
  • 12.
  • 13.
  • 14. Red are oscn and blue are oscp capbank varactors Gm cell
  • 16. Layout of vco • 4,1,3,2 are drawn and capacitively matched • 8 wires are present vertically • Pmos small is on the left and nmos (larger) on the right • All vgnd and vssa connections are symmetric • Sufficient distance so that wires can run vertically • Capacitively matched until ac caps
  • 17. Big cap layout • No clock signals on it • Reference signals ok • Strong grid • Have to meet density rules • Star connection to all important cells • Ldi/dt not an issue since difference for delay cells • What about loop filter capacitor node ?
  • 18. One more arrangement of ring oscillator Our ring oscillator looked better Effect of ground bounce
  • 19.
  • 20. Variation is due to supply bounce