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1. On-Chip Interconnect Analysis and
Evaluation of Delay, Power, and
Bandwidth Metrics under Different
Design Goals

2. Introduction
• Interconnect strategy, or interconnect planning has
become a critical part of chip design:
• the growing significance of wire delay relative to gate delay .
• increasing power consumption of wires: could be up to 50% of the total
dynamic power.
• Influences the ASIC design methodology

3. Our work
• Try to revamp the on-chip local interconnect
configuration for multi-objective optimization:
– Compare different objective functions.
– Formulate various matrics to measure the wire performance.
– Identify the optimal wire configurations.

4. Evaluation Approach and Models
• objective functions:
– is the wire-length normalized delay.
– is the wire-length-normalized power.
n
delay n n
delay power
 2
n n
delay power

n
delay
n
power

5. Evaluation Approach and Models
• Metrics
– is amount of data that can be transferred per unit
area per unit time.
n
delay n
power bandwidth /
bandwidth power
 
1/ n
bandwidth delay pitch
 

6. Evaluation Approach and Models
• Models
– Elmore delay model:
– Power model:
– Leakage factor:
0 0
(1 )(1 )
(1 )
stage nmos w
n w w inv w nmos inv
inv inv inv
d b g f r c br c
delay ar c l b g r c s
l l s
 
     
2
(1.1 )(1 )(1 )
stage leak nmos inv
n w dd
inv inv
p f g c s
power c v
l l

 
  
  
 
 

7. Minimum Delay
• Optimum repeater interval and size:
• Optimum delay and power

8. Experimental results:
wire configuration
0 0.2 0.4 0.6 0.8 1 1.2
x 10
-6
0
20
40
60
80
100
120
140
min-d
min-ddp
min-dp
pitch(m)
inverter
size
180nm
130nm
100nm
70nm
0 0.2 0.4 0.6 0.8 1 1.2
x 10
-6
0
1
2
3
4
5
6
7
8
9
x 10
-7
min-d
min-ddp
min-dp
pitch(m)
width(m)
180nm
130nm
100nm
70nm
Optimal inverter sizes
Optimal widths

9. 0 0.2 0.4 0.6 0.8 1 1.2
x 10
-6
0
0.5
1
1.5
2
2.5
x 10
-3
pitch(m)
inverter
distance(m)
180nm
130nm
100nm
70nm
0 0.2 0.4 0.6 0.8 1 1.2
x 10
-6
0
0.5
1
1.5
2
2.5
3
x 10
-3
pitch(m)
inverter
distance(m)
180nm
130nm
100nm
70nm
0 0.2 0.4 0.6 0.8 1 1.2
x 10
-6
0
0.5
1
1.5
2
2.5
3
x 10
-3
pitch(m)
inverter
distance(m)
180nm
130nm
100nm
70nm
Optimal inverter distances in the min-dp procedure
Optimal inverter distances in the min-ddp procedure
Optimal inverter distances in the min-d procedure

10. Experimental results:
metric evaluation
50
100
150
200
0
0.5
1
1.5
x 10
-6
0
0.5
1
1.5
2
x 10
-7
technode
pitch(m)
delay
n
(s/m)
min-d
min-ddp
min-dp
50
100
150
200
0
1
2
x 10
-6
0
1
2
3
4
5
6
x 10
-10
technode
pitch(m)
power(J/m)
min-d
min-ddp
min-dp
n
delay n
power

11. 50
100
150
200
0
0.5
1
1.5
x 10
-6
1
2
3
4
5
x 10
13
technode
pitch(m)
bandwidth(bits/s)
min-d
min-ddp
min-dp
50
100
150
200
0
0.5
1
1.5
x 10
-6
0
1
2
3
4
5
x 10
23
technode
pitch(m)
bandwidth/power(m/Js)
min-d
min-ddp
min-dp
Experimental results:
metric evaluation
bandwidth /
bandwidth power