This document contains a supplementary exam for a Switching Theory & Logic Design course. It lists 8 questions covering various topics in digital logic design including number system conversions, Boolean algebra, minimization techniques, encoders/decoders, programmable logic devices, latches, flip-flops, finite state machines and asynchronous sequential machines. Students are instructed to answer any 5 of the 8 questions, with each question carrying equal marks.

1. Code: R7210204
B.Tech II Year I Semester (R07) Supplementary Examinations June 2015
SWITCHING THEORY & LOGIC DESIGN
(Common to EEE, EIE, E.Con.E & ECC)
Time: 3 hours Max. Marks: 80
Answer any FIVE questions
All questions carry equal marks
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1 (a) Complete the following conversions between the number systems.
(i) (42)5=( )7 (ii) (1001100100)2 =( )8
(iii) (7E2C)16=( )2 (iv) (38.65)10=( )2
(b) Use 1’s complement arithmetic to subtract:
(i) (54)10 (231)10 (ii) ( 27)10 (87)10
2 (a) Convert the following expressions into their respective canonical forms.
(i) wy+w’xz+wyz’ (ii) (w+x+y’)(w+z)
(b) (i) Explain the properties of EX-OR gate.
(ii) Implement EX-OR gate using only NAND gate.
3 (a) Determine the minimal sum of product form of:
(i)
(ii)
(b) Use tabulation method and simplify the following function
4 (a) What is an encoder? Design octal to binary encoder?
(b) Explain how decoder acts as a demultiplexer.
5 Implement the following function using PROM
(i)
(ii)
6 (a) Draw the logic diagram and write functional table of an SR latch using NAND gates. Explain the
operation.
(b) How is race around condition satisfied by master-slave flip-flops?
7 (a) Discuss mealy and Moore machine models of sequential machines.
(b) Explain the minimization procedure for determining the set of equivalent state of a specified
machine M.
8 (a) Explain in detail the ASM chart.
(b) Design the state table of control and ASM control for an example of multiplexer by the method of
one flip flop per state.
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R07