1. Intel’s 45nm logic technology with high‐k+metal gate
transistors: an overview in recent breakthrough,
methodology
Peter Sinko, X138, University of California-Berkeley Extension
ABSTRACT
The current 45nm technology with the
introduction of high-k+metal gate transistors
demonstrated unprecedented performance,
recording best ever drive currents. A new process
flow included strain-inducing steps to improve
hole mobility by a factor of 1.5. Mitigation
efforts through optimized process flow resulted in
matched or better device characteristics in
variation and reliability. Certification of new
process on optimized X6 platform include
development data as well as critical design
optimization.
INTRODUCTION
IC technological advances are driven by Gordon
Moore's observation in 1965 namely that the
number of transistors in a chip increase
exponentially over time. Moore's law is possible
because the transistor size decreases every two
years. Today Moore's observation is the driving
principle behind aggressive scaling efforts in the
45nm and future 22nm technologies.
Approaching the current 45nm technology from
the previous 65nm technology necessitated using
alternate materials to overcome new problems
present at such dimensions.
High-K+Metal Gate transistor technology
One of the ways of scaling transistor sizes has
been to scale the gate oxide thickness. This
improved the control of the gate electrode over
the channel, and shorter channel lengths and
higher performance were possible. This
methodology came with new challenges however
with increased gate leakage. In order to
overcome high gate leakage, a new gate dielectric
with a higher dielectric constant k has been
chosen.
The new high-k dielectric presented the problem
of interacting with the existing polysilicon gates,
creating high trap densities at the interface that
pinned the Vt to undesirable values. Also a
degradation of the channel mobility due to poly
depletion effects led to lower drive currents. In
addition poor reliability of the dielectrics was an
issue. Therefore the chosen high-k dielectric had
to be compatible with new dual-band edge
workfunction metals, and a CMOS process flow
was needed that matched the channel mobility of
SiO2. To satisfy these requirements a Hafnium-
based high-k dielectric has been chosen, a revised
transistor process flow with new uniaxial strain-
inducing steps added, along with the selection of
gate electrode metal with the right work function
that was compatible with the high-k dielectric. As
a result the Vt pinning at the dielectric/poly
interface and the dielectric/poly depletion effects
were significantly reduced. The resulting
technology enabled a 0.7x reduction in Tox and a
reduction of gate leakage of 1000x for PMOS and
25x for NMOS transistors compared to previous-
generation [1, pp. 77-79].
1

2. Before gate removal After gate removal
Figure 1: simulation of stress enhancement in the channel of PMOS transistor
before and after removal of dummy poly gate
Transistor process flow
The standard CMOS process flow has two ways
of adding metal-gate to a transistor: gate-first or
gate-last process. Techniques for implementing
strain in transistors include embedded SiGe in the
PMOS S/D and stress memorization for the
NMOS. For the 45nm technology high-k
first/metal gate-last flow has been utilized with
SiGe increased to 30% from 23% in previous-
generation; this flow allowed for the additional
benefit of removal of dummy poly gate that
otherwise would have counteracted the induced
stresses, thus increasing compressive stresses by
50%, and only then depositing gate metal
[1, pp. 77-79]. Figure 1 is the image of a high-
k/metal gate PMOS transistor with embedded
SiGe S/D strain layer, simulating stress
enhancement in the channel before and after
removal of dummy poly gate.
For NMOS stress memorization the two methods
commonly used are memorization of stress in S/D
(by introduction of trench contacts) and
memorization in the poly gate. The metal-gate-
last flow is compatible with the memorization in
S/D but not compatible with memorization in
poly gate, therefore this technology replaces the
poly gate component by Metal Gate Stress
(introducing a metal-gate fill material) thus
inducing stress in the channel, all combining to a
1.5x increase in hole mobility [1, pp. 81-82].
Transistor results
The 45nm transistor is a marked improvement
over the previous-generation 65nm device. The
new high-k dielectric delivers a gate leakage
reduction of 25x for NMOS and 1000x for
PMOS.
A scaled down Tox, use of optimal workfunction
metal, enhanced strain-inducing steps in process
flow resulted in 51% improvement in drive
current for PMOS at 1.07 mA/um, and 12%
improvement for NMOS at 1.36mA/um. These
drive currents are best linear and saturated drive
currents ever.
Gains in performance benchmarked using ring
oscillator data show a total of 23% reduction in
gate delay vs. previous-generation. Component
variables measured are saturated and linear drive
currents (PMOS: 13%, 18% corresp.), gate and
junction capacitances, and voltage scaling (at
much smaller %). Therefore the large
improvements in PMOS performance accounted
for the majority of the gains achieved in the 45nm
technology CMOS [1, pp. 80-81].
Variation
Process variation has had an increasingly
significant effect in sub-micron CMOS
technologies, it is not however seen as a
limitation in the pursuit of Moore's law but
merely a new challenge to overcome.
Sources of variation in the 45nm technology are
well documented and include highly random
effects, variations in gate dielectric, patterning
proximity effects, variations associated with
polish, strain, and implants and anneals.
2

3. Random Dopant Fluctuation caused by the
decreased number of dopant atoms in the channel
(from thousands to less than 100) contributes to
adjacent device mismatch in Vt. Another random
variation is Line-Edge and Line-Width Roughness
(LER and LWR) associated with poly-gate
patterning, affecting Vt and causing increases in
sub-threshold current. Experiments showed that
optimizing process variables such as type of resist
material, focus and etch-time will result in
significant control of LER /LWR effects,
specifically the significant increase in sub-
threshold current beyond the 85nm gate length
studied [2, p. 95].
Variations in the Gate Dielectric include factors of
oxide thickness, fixed charge, and interface traps,
affecting drive current, gate tunneling current, and
threshold voltage. Simulations show that
fluctuations in Vt due to local oxide thickness
variations become comparable to voltage
fluctuations for conventional MOS devices at or
below 30nm. Similar experiments concluded that
under certain conditions the gate-tunnel leakage
current causes significant fluctuations in Vt when
the gate oxide tunnel resistance becomes
comparable to the gate poly-Si resistance.
Further causes of Vt fluctuations are due to the
fixed charge present in the high-k layer affecting
uniformity of threshold voltages, and fast
charging in electron traps (due to defects in
dielectric) that affect mobility and causing Vt
instability [2, p. 96]. Among Patterning
Proximity effects Optical Proximity Correction
(OPC) proves to be the most powerful technique
in reducing variation, which uses specific
algorithms to pre-distort mask data to achieve the
desired pattern on wafer. Process strain
introduces both random and systematic variation
to threshold, and analytical models have been
developed to predict Vt fluctuation as a function
of Ge fraction, Tox, channel length and doping
profile.
Variations due to implant and anneal arise from
implant tool conditions: device sensitivity to
implant parameters such as accuracy and purity of
dose, anneal peak temperature, ramp-up and cool-
down rates is significant. Additional variation is
related to the poly-crystalline nature of
conventional gates. The randomly oriented and
rotated poly-Si gate grains affect carrier profiles
and by optimizing grain boundaries a 26%
reduction in threshold voltage variation has been
achieved [2, 98].
Mitigation efforts include pure process
techniques, process-and-design combined
techniques, and pure design techniques. The
introduction of high-k+metal gate was a pure
process technique that mitigated the impact of
gate-leakage at the time of transitioning to 45nm
technology. Subsequent process improvements
reduced the impact of traps in the dielectric and
their associated effects on variations of threshold
voltage. Advanced patterning techniques further
reduced Line-Edge Roughness and associated
random variation. A specific process/design
mitigation strategy was to change SRAM
topology from “tall” design to “wide” design that
resulted in aligning the poly in one direction thus
eliminating diffusion corners. Pure design
mitigation example was the reduced impact of
mismatch due to random variation in the SRAM
by incorporating of dynamic forward body bias, a
technique of partially discharging the PMOS
Nwell 1 cycle before the word-line pulse. The
Nwell at such lower bias minimizes switching
power. Good layout techniques are utilized in
minimizing systematic variation: matched
devices are layed out to have the same centroid
(or center of gravity) so that any effect systematic
across the layout will impact all matched devices
equally [2, pp. 99-102].
Characterization of variation is a way of
measuring the success of mitigation efforts using
different types of measurements. In-fab
measurement of Critical Dimension (CD) is used
as critical parameter for assessing and controlling
variations between generations in order to
maintain the required 0.7x scaling. DC electrical
measurement of Matched Transistor Pairs is used
to extract random variation from 65nm to 45nm
generations. Ring oscillators strategically placed
in all designs provided within-die and within-
wafer variation data that revealed a constant
within-wafer systematic variation across the last
four generations, and a 50% improvement in
random variation from last to current generation.
A particular note was the improvement of
systematic within-die variation of Vt, 45% for
3

4. NMOS and 22% for PMOS [2, pp. 102-104].
Reliability
Reliability characterization of the 45nm transistor
fall into two categories: Time-Dependent
Dielectric Breakdown TDDB, and Bias Temp
Instability BTI.
Time-Dependent Dielectric Breakdown TDDB
measures the integrity of the transistor dielectric
that manifests in premature and/or abrupt failure
of the dielectric. Characterization conditions are
elevated temperatures and voltages until failure
occurs, sometimes lasting over several months.
Measurement is taken with either constant voltage
or constant current on transistors and capacitors.
Causes of dielectric failure are attributed in large
to charge injection and conduction due to “traps”
or electrical defects. These traps affect the
already high operating electric fields along the
dielectric interface causing elevated leakage
currents. With the accumulation of such traps over
time the gate currents gradually increase until a
“chain” of conductive traps is established that will
result in a large increase of current flow referred
to as breakdown current. This phenomenon is
known as Stress Induced Leakage Current SILC
degradation, and is a major concern in high-k
dielectrics.
Another source of dielectric breakdown is In-
Process-Charging or the degradation of transistor
parametric characteristics during process and
plasma fabrication. Charge accumulated on gate
interconnect can result in sufficient stress to cause
damage to the device. To reduce such charge
accumulation, diodes and transistors are used
specifically as discharge mechanisms
[3, pp. 134-135].
Bias Temp Instability BTI is a measure of
progressive degradation of the dielectric, affecting
Intel-critical SRAM device parameters such as
maximum operating Frequency and Vt-mismatch-
sensitive Static Noise Margin (SNM) which affect
cell and array size scaling. Operating under bias
the transistor characteristics such as Vt, drive
current and transconductance change over time.
These changes show voltage and temperature
dependency and measurement is complicated by
the fact that these dependencies are only present
during operation as they disappear upon the
removal of bias. Such dependencies can only be
characterized during the presence of bias, and
methods such as On-The-Fly measurements,
Ultra-fast and Pulse-IV measurements have been
utilized in attempt to characterize them
[3, pp. 133-134].
Extensive experimental data has been collected to
assess TDDB and BTI related dielectric integrity.
Overall data show the transition to high k+ mg
technology yields transistor dielectric lifetimes
similar to previous generation in spite of 30%
higher electric fields and largest ever drive
currents. TDDB test results show that optimized
HK+mg dual workfunction metal matches SiON
dielectric lifetime. Reduction of correlating trap
densities within the dielectric due to optimized
HK process flow resulted in SILC degradation
levels similar to conventional SiO2 [3, pp. 136-
137]. BTI related degradation in Vt and
correlating Gm shifts are also similar to those
observed on SiON. Results show similar time-
dependencies of transistor degradation for
HK+mg process to Poly/SiON. Rapid shifting in
transistor thresholds due to charge trapping when
applying bias have been shown to have only
moderate effects since the optimized 45nm
process has negligible fast trapping. Hot carrier
injection degradation of Vt and Gm has been
shown to be limited from previous 65nm
generation although the conduction band offset is
lower for Hf based dielectric and Si substrate.
Data show an improvement rather of HK+mg
transistor lifetimes over previous Poly/SiON
transistors. In addition In-Process-Charging
degradation has proved insignificant due to
measures taken to manage accumulated charge
[3, pp. 137-140]. TDDB and BTI related
reliability factors correlating to the potential for
high trap densities within the HK dielectric have
been controlled by optimized process, and yield
similar or better characteristics than the previous
generation Poly/SiON technology [3, pp. 140-
141].
Testing and certification
Every generation of process technology at Intel
has been developed, tested and certified on the
SRAM-based X-series test and development
platforms. X6 being the latest, it has been
4

5. optimized for the current 45nm high-k/metal gate
technology. The SRAM memory playing a major
role in all Intel IC products, it has always been
sensitive to a variety of process defects due to its
large area coverage and granularity (fine
addressability), and is ideal for defect detection,
isolation of location and analysis. The
architecture of the X6 includes memory circuit
technology developments like Dynamic Sleep
Control and Dynamic Forward Body Bias, test
features such as Error Correction Code,
Programmable built-in self-test, Test Access Port
tap scan-chain controller using ring oscillators for
tracking process variation. It also includes critical
analog circuits like new programmable fuse (used
in repairing defective memory bits), phase lock
loop, digital thermal sensors, and I/O circuits.
The X6 has become not only a process
development platform but also a critical design
optimization test bed. Future generation high-
speed CPU circuitry incorporated serve as early
silicon-based learning as they are strongly
dependent on technology and process. High-
speed serial I/Os, differential transceivers, Delay
Locked Loops, duty cycle correction and low-
jitter PLL are some examples [4].
CONCLUSION
Moore's law driven IC technological advances
resulted in the current 45nm technology, featuring
a new HK+mg transistor with highest
performance ever recorded. At largest drive
currents, transistor characteristics have been
matched or exceeded to those of the previous
65nm generation. Scaling presented challenges
have been successfully mitigated in
characterization and reliability.
Exciting new developments in future 22nm
technology include the introduction of
revolutionary 3 dimensional Tri-Gate transistors,
featuring conducting channels on three sides of
vertical fin structures to increase total drive
strength for higher performance.
References
[1] C. Auth, et al., “45nm High-k+Metal Gate
Strain-Enhanced Transistors” Intel Technology
Journal, Vol. 12, Issue 02, June 2008.
[2] K. Kuhn, et al., “Managing Process Variation
in Intel's 45nm CMOS Technology” Intel
Technology Journal, Vol. 12, Issue 02, June 2008.
[3] J. Hicks, et al., “45nm Transistor Reliability”
Intel Technology Journal, Vol. 12, Issue 02,
June 2008.
[4] U. Bhattacharya, et al, “45nm SRAM
Technology Development and Technology Lead
Vehicle” Intel Technology Journal, Vol. 12, Issue
02, June 2008.
June 17, 2012
5