1. Methods of Reducing Errors Associated with
Charge Injection and Clock Feedthrough
in S/H Circuits
Peter Sinko, X140: Fundamentals of Analog Integrated-Circuit Design Technique
UC Berkeley Extension
Abstract - Modern techniques to reduce S/H output
errors are discussed, and the associated proposed
topologies presented. Charge injection and clock
feedthrough associated errors have been
significantly reduced using pinched-off channels in
MOS switches, techniques of current cancellation,
charge cancellation and delayed clocking, Miller
effect in cascode feedback amplifier, an application
of a differential capacitance transducer, and
bottom-plate technique using a bootstrapped
switch. All proposed architectures reported
significant reduction in output errors by simulation
and in-silicon measurements.
INTRODUCTION
Sample-and-hold S/H circuits are very important
building blocks in modern signal processing and
communication systems, employed extensively in
data acquisition interfaces such as analog-to-
digital A/D converters. From the very simple S/H
circuit consisting of a single MOS transistor and a
hold capacitor to more sophisticated circuitry,
they suffer from two major problems that cause
significant errors in the held output signal, namely
charge injection and clock feedthrough.
Numerous techniques have been developed to
address these problems that resulted in significant
reduction of associated errors. This paper
discusses the origins of these errors and presents
several modern circuits in detail to illustrate
concepts, strategies and design techniques.
PRIMARY SOURCES OF ERROR
The first primary source of error in S/H circuits is
charge injection, originating from the presence
of charge held in the channel of a MOS transistor
after it is turned off. In this
parallel sampling circuit when the
MOS switch is on, it operates in the
triode region and its drain-to-source
voltage is approximately zero.
During this time the transistor holds
mobile charges in its channel and the output
signal tracks the input. Once the transistor is
turned off, a certain amount of these mobile
charges are still present and will flow out of the
channel region into the drain and source
junctions. Some portion of the channel charge is
released back to the input while the rest of the
charge is transferred to the hold capacitor
resulting in erroneous output signal levels. Since
these mobile charges are due to the input signal,
the amount of charges held depend on the signal
level, which is not a constant, and charge
injection is said to be signal-dependent [1, p.60].
The second primary source of error in S/H circuits
is clock feedthrough, due to the parasitic gate-to-
source/drain overlap capacitance of the MOS
transistor. When this series-sampling circuit is
in sample mode, switches S2 and S3
are on and S1 is off. Then S2 is
turned off first which makes Vout
equal to Vcc and the voltage drop
across Ch will be Vcc-Vin. Next S3
is turned off and S1 is turned on simultaneously.
At this point Vout is equal to Vcc-Vin (with
respect to ground) and the voltage difference from
Vcc to Vout [Vcc-(Vcc-Vin)=Vin] is equal to the
instantaneous value of the input. This is an
inverting S/H circuit and the output requires
inverting [1, p.61].
The amount of charge injected into Vout upon
turning S2 off is constant since Vgs of S2 is a
constant and the error introduced can be treated as

2. offset that can be removed by differential
operation. Therefore the error introduced by
clock feedthrough is signal-independent. Also,
there is no signal-dependent charge injection in
this circuit since S2 is turned off before S3.
On the other hand, this circuit suffers from the
non-linearity of parasitic capacitance at node Y.
This parasitic capacitance introduces distortion to
the held value, requiring the holding capacitor to
be much larger than the parasitic capacitance.
Another disadvantage of the series sampling
circuit is the longer settling time during hold
mode, because the value of Vout is reset to Vcc
for every sample of the input [1, p.61].
Such simplicity entailing erroneous results,
elaborate circuitry have become a necessity for
modern systems demanding speed and accuracy.
MODERN S/H ARCHITECTURES
The Switched Op-Amp S/H circuit proposed by
Dai et al. [2] is based on
parallel sampling and
takes advantage of the
channel pinch-off of a
MOS transistor in saturation. A pinched-off
channel being disconnected from the drain, the
hold capacitor connected to the drain will not be
affected by charge injection. Instead, charge will
flow entirely to the source junction.
During sample mode the output follows the value
of the input. During hold mode the MOS
transistors at the output node of the SOP are
turned off while they are still operating in
saturation, thus preventing any channel charge
from flowing into the output of the SOP. In
addition, the output of the SOP is held at high
impedance to preserve the charge on the holding
capacitor throughout the hold mode. Meanwhile,
the output buffer is always operational and
provides the voltage on holding capacitor Ch to
the output Vout [2, p.110].
The block diagram is a
pseudodifferential circuit
using a switched folded
cascode op-amp with
two independent signal
paths Vin+ and Vin-.
The output currents of
the operational transconductance pair Gm are
converted into voltages, which control the gates
of M1 and M2. When the two clock-controlled
current sources Ib and switches S1 and S2 are on,
the circuit is in sample mode. When the clock
goes low, both Ib are off, leaving the drains of the
transistors M1,2 at high impedance. At this point
the circuit is in hold mode, and the hold
capacitors retain the sampled value and transfer it
to the output via the unity gain buffers.
Transient analysis using
HSPICE show linearity
for a complete cycle of
sample-and-held
waveform [2, p.110].
The implementation is
shown in Fig. 1 where
transistors M1 through
M13 form the folded cascode op-amp, while M14
and M15 make up the unity-gain buffer.
Transistors M16 to M19 have been added to turn
the SOP off at the end of the sample mode.
Because of the pinched-off channels in hold
mode, charge injection no longer exists in this
S/H circuit. Delayed clocking at nodes 3 and
pbias with respect to ncas and pcas solve the
potential charge sharing of nodes 1 and 2 with
capacitor Ch when the op-amp turns off. The
only source of error is clock feedthrough caused
by the overlap capacitance of M9 and M11. To
minimize this error the channel widths of the
transistors M8 through M11 are kept at a
minimum. Clock feedthrough being a signal-
independent error, it is treated as offset and
eliminated by the differential technique of the
design [2, p.111].
The time-domain
measurements are in
agreement with
simulation results.
Another technique applies current cancellation
to minimize existent leakage currents in MOS
switches. The circuit by Wong et al. [3] has been
designed for medical implant devices where low
power consumption is required for many years of

3. continuous battery powered operation. Such
systems use low supply voltage and operate at
very low frequencies (~0.1Hz) where often very
long hold times (order of ms) are required. The
specifically designed low-threshold sub-micron
devices exhibit significantly increased leakage
currents that have been identified as junction
leakage to Vdd and Vss, and channel leakage.
The sum of these leakage currents is in the order
of pA that in the case of a 1pF holding capacitor
will cause a 0.1V drift by the end of the long
holding period. This striking voltage drift is best
seen in this simulation
where the held output
drifts to Vdd, Vss, or is
mostly lost, mandating
that the performance of
these circuits has to be
regained [3, p.311].
The proposed leakage current cancellation
technique utilizes a self-adjusting current source
in a feedback loop to
cancel the leakage
currents seen by the
holding capacitor.
This current source
injects a canceling
current into the
holding node that is
opposite in phase to the leakage current, reducing
the effective leakage currents in the node to
almost zero. The circuit is realized in Fig. 2 using
an op-amp A1, a replica of the MOS switch, and a
network of transistors M1-M8 in a feedback loop.
The concept of operation is based on amplifying
the voltage difference at the inputs of op-amp A1
and exciting the push-pull output stage of
constant current source to generate the canceling
current of opposite phase and inject it into the
holding node.

4. To ensure that a voltage difference always exists
at the inputs of the opamp, the replica holding
capacitor Crep is much smaller than the actual
holding capacitor Chold. Also, the sizes of
transistors in the push-pull network are much
larger than the switch transistors in order to
generate higher currents. In quiescent mode the
holding voltage Vhold and Vrep will not drift
further as the feedback network continuously
monitors and adjusts the voltage difference and
adjusts the generated canceling currents
[3, p.312].
Simulation results show a 20x improvement in
voltage drift as compared
to an uncompensated
circuit. The compensated
S/H circuit produced a
9.5mV/sec voltage drift,
whereas an uncompensated
circuit had 200mV/sec
voltage drift.
For bench measurements a first-order switched-
capacitor low-pass filter has been fabricated in a
0.5um test chip. Measurements are in agreement
with simulation and show the improvement in
waveforms from uncompensated to the
compensated circuits [3, p.314].
The proposed circuitry will cancel all leakage
currents assuming perfectly matched transistors
and an ideal opamp. Leakage currents due to
mismatches can be minimized by careful layout,
using high open-loop gain amplifiers, and finding
optimal values for the holding capacitors Chold
and Crep to avoid clock injection.
A circuit solution by Gatti et al. [4] is based on
the conventional closed-loop architecture and is
capable of obtaining a S/H function with a held
step error of less than 0.2mV. Fig. 3 shows the
circuit with associated clock signals.
First, switches S1 and S2 are closed and the input
signal charges capacitor Cs. When S1 and S2 are
turned off, the input signal is sampled. Next,
switches S4 and S5 are closed thus connecting the
bottom plate of sampling capacitor Cs to the
output in a feedback loop, and the input signal
appears at the output. During this phase the
capacitor Ch performs Miller pole-splitting
compensation. After opening S4 and S5, the
holding capacitor Ch holds the output voltage.
During sampling when S1 and S2 are closed, ϕ1
also closes switch S3 and buffer A1 charges Cof
to its offset voltage. This operation with capacitor
Cof in a feedback loop to A1 becomes the offset
compensation. At the same time Cof receives
injected charge that is matched to Cs upon turning
off the matched switches S2 and S3 [4, p.120].
Moreover, with the same operation the clock
feedthrough of S2 and S3 are matched in both
capacitors if these four components are matched.
Utilizing delayed clocking, turning off S2 before
S1 and leaving the associated node floating, the

5. signal-dependent charge injection into Cs from
switch S1 is avoided. In order to address
subsequent charge injection effects in the second
gain stage, an additional loop using capacitor Cx
and unity-gain buffer B1 is employed [4, p.121].
The accuracy of the S/H circuit is dependent upon
matching the charges injected by S5 and S6. By
turning S6 off delay τ before S5, capacitor Cx is
precharged to an amount of charge that will match
the injected charge from S5 at the next stage.
When S5 is closed and its charge is injected into
node X, compensation charges are injected by
closing S7. The compensation is very accurate if
the rise time of the clocks is very small, and
results in the reported accuracy of the circuit.
Measurements result in the output value of a
10kHz, 0.5V input signal staying within 0.2mV
accuracy during hold time, and in the time
response to a 100kHz, 2V input at 1MHz
sampling frequency.
The S/H circuit introduced by Xu et al. [5] uses
Miller feedback capacitance to reduce charge
sharing effects due to the parasitic capacitance of
the sampling switch. To this open-loop S/H circuit
a high-gain Miller feedback
amplifier has been added to
reduce both effects.
A previously investigated circuit
featured a simple high-gain
inverter with large input capacitance,
resulting in moderate improvement. The
proposed circuit replaces this inverter with
a cascode inverter amplifier specifically to
reduce this input capacitance. The inverter
is designed with minimum size input
transistors M5 and M6, while the large
cascode transistors M5a and M6a are sized
for gain [5, p.94]. Using this cascode
amplifier, the proposed circuit is in Fig. 4.
The Miller hold capacitance is split into two
capacitors Csh1 and Csh2, while Ci and Cp2 are
the parasitic capacitances at the input and output
of the inverting amplifier. During ϕ1 high the
input is sampled onto capacitors Csh1 and Csh2
in parallel, and the parasitic capacitor Cp is
charged to a reference voltage Vref. During
transition from sample to hold phase the charges
are redistributed among these four capacitors
producing the error due to charge sharing.
During hold mode transistors M1 and M7 turn off
and M2 turns on, and charge injects onto nodes x
and y [5, p.94]. This charge induced noise can be
expressed as (Vref-Vin)Cp/ACsh2, that by
inspection can be reduced by increasing Csh2
[5, p.95].

6. At the same time clock feedthrough charge
injected onto node y is fixed, therefore its error is
independent of the input and is a constant. In this
configuration the two holding capacitors will
separate the error effects: increasing Csh2 reduces
charge sharing error, reducing Csh1 reduces clock
feedthrough error.
Simulation results plot the output error as a
function of input signal.
For equally sized
holding capacitors
Csh1=Csh2=500fF, in
case of small parasitic
capacitance Cp the total
errors are similar for
both circuits with and
without Miller feedback. However in the case of
large parasitic capacitance the effects of the
Miller feedback become significant with
increasing Cp: without Miller capacitance the
error has an increasingly aggressive function,
whereas with Miller capacitance the error curve is
almost flat, staying nearly constant for an input
range. For Cp=80fF the slope of the curve is
reduced from 0.11 to 0.01, a 10 times reduction in
error [5, p.95].
The effects of charge sharing and clock
feedthrough are separated by simulating for
alternating size-combinations of capacitors Csh1
and Csh2. For the case
Csh1=300fFCsh2=700fF
the slope of the error
function is 0.03, and for
Csh1=700fFCsh2=300fF
the slope is 0.13 [5, p.96].
This result confirms
previous inspection of the error expression that
charge sharing error is inversely proportional to
Csh2. It also reveals that charge sharing has more
profound effect on total error than clock
feedthrough.
The final simulation compares the use of the
cascode amplifier instead
of a simple inverter in the
Miller feedback.
The proposed S/H circuit
with cascode feedback
amplifier has smaller
slope and lower error due
to the higher gain and smaller Ci of the designed
cascode amplifier. In agreement with previous
simulations, this is most evident at higher
parasitic capacitances.
An application of switched-capacitor SC S/H
circuits is the Differential Capacitance
Transducer [6] used in the detection of physical
quantities such as pressure difference, linear
displacement, acceleration, and rotational angle.
The differential capacitance transducer consists of
two capacitors whose capacitance change with the
measured variable. In rotational angle detection
the capacitance changes linearly with measured
angle, in pressure transducers the capacitance
change hyperbolically with the applied pressure.
The ratiometric operation of dividing the
capacitance difference by its sum has been
implemented by several methods in the past, that
included feedback control methods, integration
and differentiation methods, and SC A/D
conversion. The CMOS interface proposed by
Ogawa et al. [6] is a switched-capacitor S/H
circuit using a unity-gain buffer. The transducer
is realized by the specified switching sequence of
the circuit in Fig. 5. In the first ϕ1=ϕ2=ϕ3=1
phase capacitor Ca is charged to voltage Vr and
Cb is discharged. In the next ϕ1=ϕ2=ϕ3=0 phase
the capacitors are connected in parallel to produce
that is sampled by S/H1.
The next two clock phases are the complementary
operations of the previous two: Cb is charged to
Vr and Ca discharged, then the two capacitors are
connected in parallel to result in
which is then sampled by S/H2.
Taking the difference Vo1-Vo2 produces
which is the ratiometric operation expected of a
differential capacitance transducer for any
measurand x, and is simulated by HSPICE
for an ideal unity
gain buffer as a
straight line
[6, p.354].

7. The sources of error are clock feedthrough, offset
voltage, gain error and parasitic capacitances.
The error due to clock feedthrough from switches
is solved by delayed
clocking and thus the
associated charges of
opposite polarity canceling.
By ϕ3 turning off S4 a
delay τ1 before S1, the
charge from S4 is injected to Cb; then turning S1
off its charge is injected to Ca. If S4 and S1 are
matched MOS transistors, their injected charges
will be equal in magnitude and of opposite
polarity. In the following ϕ1=0 phase these
charges cancel each other and will have no effect
on Vo1. Subsequently the same delayed clocking
is applied to obtain Vo2. The offset voltages
present in Vo1 and Vo2 are subtracted during the
final difference operation Vo1-Vo2 [6, p.354].
The results of the modified clocking are
illustrated by plotting the error values from ideal.
The average slope of the modified switching error
curve is considerably smaller than the slope of the
basic switched error curve, confirming that
modified switching technique results in less error
therefore higher accuracy.
Bench measurements of the interface using a
wide-swing CMOS unity gain buffer in place of
the ideal buffer show some deviations from the
ideal values mainly due to gain errors, that are
again reduced with delayed clocking. In-silicon
measurements confirm the ratiometric operation
by a straight line with smaller non-zero slope,
while the plot of residual non-linear error reveals
the modified clocking results and the desired
accuracy in the order of a few mV [6, p.355].

8. The bottom-plate technique in conjunction with
the use of a double-side bootstrapped switch
has been proposed by Xubin et al. [7] for the
fully-differential flip-around S/H circuit.
This technique
proves effective in
making the charge
injection signal-
independent of the
input signal, while
the bootstrapped switch improves precision by
reducing the non-linearity of the switch on-
resistance.
The circuit has been implemented using a folded
cascode configuration with gain-boosted
operational transconductance amplifiers and
complementary high-swing regulation, as shown
in Fig. 6. The amplifiers are constructed with
minimum size transistors and operate with very
low bias currents to retain Gain Bandwidth
[7, p.055011-2].
The architecture features a double-side
bootstrapped switch for sampling,
shown in closed position, to
reduce distortion due to the non-
linearity of the switch on-
resistance. This non-linearity occurs because of
the dependency of the Gate-Source voltage on the
input signal, and is reduced symmetrically on
both Source and Drain sides of the main switch.
Due to its functionality, the double-side
bootstrapped switch deserves detailed analysis, as
implemented in Fig. 7.
When the switch is OFF, the gate of the main
switch MS is connected to Vss through M5 and
M6, and capacitors C1a and C1b are charged to
Vdd through M2a,b and M3a,b. When the switch
turns ON, the precharged capacitors C1a,b are
connected simultaneously across both terminals
GS and GD of the main switch MS, thus making
the terminal voltages Vgs and Vgd equal.
Thereby the Ron linearity of the main switch MS
is improved. The introduced clock feedthrough
error is minimized by using a replica of MS in a
dummy switch configuration connected across G
and Vout terminals of MS, that in hold mode will
exactly compensate input-dependent clock
feedthrough. The resulting input-independent
clock feedthrough is constant and can be canceled
out by differential operation [7, p.055011-3].
The high-bandwidth and good linearity of the
proposed S/H circuit is demonstrated in the output
spectrum of a 2.5MHz input sinewave at 50MHz
sampling rate:

9. CONCLUSION
Several papers have been presented to illustrate
concepts, modern strategies and design techniques
that resulted in significant reduction of output
errors associated with charge injection and clock
feedthrough in S/H circuits. The concept of
utilizing pinched-off channels in MOS switches
has been demonstrated, current and charge
cancellation techniques with delayed clocking, the
Miller effect in cascode feedback amplifier, the
application of a SC differential capacitance
transducer, and bottom-plate technique using a
double-side bootstrapped switch have been
presented.
All proposed architectures achieved significant
results in improved linearity and voltage drift,
reduced output error, desired accuracy and high
bandwidth, by consistent simulation and in-silicon
measurements.
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November 4, 2013