Here are the key steps to design an LNA: 1. Calculate the minimum achievable noise figure NFmin using the noise parameter Fmin. This depends on device parameters like transconductance gm, output resistance ro, bias current density Jc, etc. 2. Choose an optimal value for Jc that minimizes NFmin. This Jc-opt depends on device capacitances, bias voltage, and frequency of operation. 3. Design the input matching network to transform the source impedance (usually 50 ohms) to the optimal impedance looking into the transistor for minimum noise. This involves choosing component values for the matching network. 4. Design the biasing circuitry to provide stable bias point

1. A Graduation project on
Wireless RF Transceiver
Presented by
Ain Sham Univer sit y
s
Ahmad Ibrahim
Facul t y Of Engineer ing Hazem Mohammad
Graduation Project 2001 Mohammad Atef
Mohammad Khalifa
Sherif Sobhi
Presented to
Dr. Khaled Sharaf

2. ‫شكر‬
‫نتقدم بخالص الشكر و التقدير‬
‫للدكتور/ خالد شرف لما بذله معنا من‬
‫جهد ووقت كان فيهما خير قدوة فى‬
‫الدب و العلم و نحسبه على خير‬
‫ول نزكي على ال أحدا‬

3. Introduction
• Tx transmits at a centre frequency of
950MHz with a 20MHz B.W.
• Rx receives at a centre frequency of
1GHz with a 20MHz B.W.

4. Tx
GFSK Transmitter

5. Rx
• Single conversion superheterodyne receiver.

6. Heterodyne vs. homodyne
• Heterodyne receiver is preferred over
homodyne Rx by its superior selectivity &
sensitivity.
• Heterodyne requires off-chip filters.
• Heterodyne requires greater area & so cost.
• However it is still used it is too much easier to
design.(no oscillator isolation problem)

7. Some related terms

8. Oscillators
• General considerations
- Output frequency
- Frequency stability
- Power output

9. Basic Oscillator Topologies
- Hartley Oscillator
- Colpitts Oscillator
- Clapp Oscillator
- Crystal Oscillator
- Negative Oscillator

10. Frequency Stability
• How to improve frequency stability ?
- Reduce noise
- Follow the oscillator with a buffer
- Thermally isolate the oscillator
- Use crystal to control the frequency

11. Voltage controlled oscillator
• If the output frequency can be adjusted by a
voltage, then we have a VCO.
• The tank capacitance can be replaced by a
reverse-biased diode (varactor)

12. Oscillator’s Parameters
• Phase Noise in LC circuits
- It may affect both the frequency and
amplitude of the output signal.
- The higher the Q of the tank, the lower the
phase noise.

13. Oscillator’s Parameters
• Phase Noise in VCO
Depends on the path into which the noise is
injected.
- Noise in signal path
- Noise in control path
• Another source of noise is generated by the
active device.

14. Oscillator’s parameters
• Oscillator Pulling
- Coupling from the power amplifier
- The desired signal is accompanied by a
large interferer
- The load pulling
• Oscillator Pushing

15. Receiver VCO
• Simplified VCO Schematic

16. Receiver VCO
• VCO design

17. Receiver VCO
• Negative Resistance
Gm
Negative Re sis tan ce ≈ 2
ω Cbe C1
• Oscillating Frequency
1 1 1
ωo L − − − ≈0
ωo CV ωo Cbe ωo C1

18. Receiver VCO
• Output Waveforms
1.0V
394mV
0V
0V
-394mV
-1.0V -777mV
0s 0.2us 0.4us 0.6us 0.8us 1.0us 991.46ns 992.00ns 993.00ns 994.00ns 994.68ns
V(out+) V(out-) V(out+) V(out-)
Time
Time

19. Receiver VCO
• Output Waveforms
400mV
394mV
300mV
200mV 200mV
100mV
0V 0V
0Hz 5GHz 10GHz 15GHz 20GHz 25GHz 30GHz 35GHz 0.966GHz 1.000GHz 1.040GHz 1.080GHz 1.120GHz 1.160GHz 1.200GHz
V(out+) V(out-) V(out+) V(out-)
Frequency Frequency

20. Receiver VCO
• Output Waveforms
5KV
0V
-5KV
-10KV
103MHz 300MHz 1.0GHz 3.0GHz 10GHz
Vr(I12:-,C306:2)
Frequency

21. Receiver VCO
• Tuning Range

22. Driver
• Driver design
0 0
0
0 0
0
0 0

23. Driver
• Waveforms
1 0 0 mV
0V
- 1 0 0 mV
- 1 5 4 mV
150. 00ns 152. 00ns 154. 00ns 156. 00ns 158. 00ns 159. 65ns
V( C4 : 1 , R2 3 : 1 ) V( R2 7 : 2 , L 3 1 : 2 )
T i me

24. Driver
• S_parameters
- S21 13.69 dB
200
0
- 200
- 400
1 0 Hz 1 0 0 Hz 1 0 KHz 1 . 0 MHz 1 0 0 MHz 1 0 GHz
s 21
Fr e q u e n c y

25. Driver
• S_parameters
- S11 -34.059 dB
0
- 10
- 20
- 30
- 39
1 3 . 2 MHz 3 0 . 0 MHz 1 0 0 . 0 MHz 3 0 0 . 0 MHz 1 . 0 0 GHz 2 . 6 6 GHz
s 11
Fr e q u e n c y

26. Driver
• S_parameters
- S22 -14.751 dB
20
0
- 20
- 40
1 0 Hz 1 0 0 Hz 1 0 KHz 1 . 0 MHz 1 0 0 MHz 1 0 GHz
s 22
Fr e q u e n c y

27. Driver
• S_parameters
- S12 -15.821 dB
0
- 250
- 500
1 0 Hz 1 0 0 Hz 1 0 KHz 1 . 0 MHz 1 0 0 MHz 1 0 GHz
s12
Fr e q u e n c y

28. Transmitter VCO
• VCO Topology
- Negative Resistance
• VCO Blocks
- Negative Resistance Cell
- Tank Circuit
- Output Buffer

29. Transmitter VCO
• VCO Schematic

30. Transmitter VCO
• Negative Resistance Cell
- Uses active feedback network
-2(1/gm +RE)
instead of passive Vcc
network used in other Q4 Q3
topologies Q1 Q2
RE RE
{
Q5 Q6 Q7
CURRENT SOURCE Vcs
R4 R5 R3
0 0 0 0
-R cell

31. Transmitter VCO
• Verification of –R cell by Simulation
-0.016KV 200V
N N
e e
g g
a a
t -0.250KV t
i (950M,-66.844) i
v v 0V
e e
R -0.500KV R
e e
s s
i i
s s -200V
t t
-0.750KV (954M,-320.383)
a a
n n
c c
e e
-1.000KV -400V
1.5MHz 10MHz 100MHz 1.0GHz 10GHz 100GHz 30.6MHz 100.0MHz 1.00GHz 10.0GHz 28.6GHz
VR(Q21:c,Q23:c) Vr(Q23:c,Q22:b)
Frequency Frequency
Without tank With tank

32. Transmitter VCO
• The Tank Circuit
- Used to select the frequency
- Used to change the frequency
• The Output Buffer
- Acts as an isolation stage

33. Transmitter VCO
• Simulation Results
3 4 9 mV 5 0 mV
A
M
P
L
I
T
2 0 0 mV
U
D
E
0V
0V
- 5 0 mV
- 1 4 9 mV
0s 0. 5us 1. 0us 1. 5us 2. 0us 2. 5us 3. 0us 3. 00802us 3. 01000us 3. 01200us 3. 01400us 3. 01600us
V( C9 : 2 ) V( R4 0 : 1 )
T i me T i me
4 0 mV
A
M
P
L
I
T
U
D
E
2 0 mV
0V
9 5 5 . 0 5 MHz 9 6 0 . 0 0 MHz 9 6 5 . 0 0 MHz 9 6 9 . 6 0 MHz
V( R4 0 : 1 )
Fr e q u e n c y

34. Transmitter VCO
• Tuning Range
- The tuning range of the VCO is 20MHz
while Vcontrol is from 0 to 2.7v

35. Transmitter VCO
• Loading Effect

36. Transmitter Section
• Transmitter As GFSK Modulator
- GFSK  FSK+ Gaussian low pass filter
• Its advantage
- Increases spectral efficiency ( BW )
• It consists of
- Gaussian Filter as gaussian
shaping
- VCO as FSK modulator
- Driver

37. Transmitter Section
• Gaussian Filter
R1 L1 L2 L3 L4 L5
Vpulse R2
C1 C2 C3 C4 C5
0 0 0 0 0 0 0
• Simulation Results
3. 0V
i nput dat a
2. 0V
out put dat a
1. 0V
0V
1. 51us 2. 00us 3. 00us 4. 00us 5. 00us 6. 00us
V( R1 : 1 ) V( R2 : 2 )
T i me

38. Transmitter Section
• Output Signal
4 2 1 mV
2 5 0 mV
0V
- 2 5 0 mV
- 4 9 5 mV
732. 00ns 733. 00ns 734. 00ns 735. 00ns 736. 00ns 736. 84ns
V( L 3 0 : 1 , MNMN) V( R2 3 : 2 , C3 : 2 )
T i me

39. Transmitter Section
• Output Signal
3 0 0 mV
2 0 0 mV
1 0 0 mV
0V
9 4 6 . 0 0 MHz 9 4 8 . 0 0 MHz 9 5 0 . 0 0 MHz 9 5 2 . 0 0 MHz 9 5 3 . 9 8 MHz
V( L 3 0 : 1 , MNMN) V( R2 3 : 2 , C3 : 2 )
Fr e q u e n c y

40. LNA
• LNA main charactaristics
- Noise figure
- Gain
- linearity
- S-parameters
- Power consumption

41. LNA input stage topologies
Vcc Vcc
Zc
Rb Zc
Output
Output
Vb Input
Input
Rs
bias Ze
Common base Common emitter
-better isolation 0 -poor isolation 0
-high unavoidable (Miller capacitance)
noise for 50Ohm -lower NF
input match((gm) -1 = 50)

42. Cascode amplifier
Vcc
Zc
-Better isolation than CE Output
o/p
(no Miller) Vb match.
-Less components than cascade
-Easily converted to differential
Input
i/p
match.
Ze
&
bias
0

43. Input Matching networks
Input
Input
Input
Zin 0
Zin
Zin
0 0 0 0
Input
Input Input
Zin Zin
Zin
i/p
M.N.
0 0 Chosen one 0
0

44. Cascode Differential
Vcc
Zc Zc
output- ouput+
o/p o/p
match. match.
Advantages
Vb Vb
-Immunity to external noise
-Increased dynamic range,
Input+ Input-
-Easier use in integrated circuits i/p i/p
match. match.
-Reduced second order harmonics.
Ze Ze
bias
0

45. Designing an LNA
1/ 2
n  2Jc  f2 1  n2 
NFmin ( J c ) = 1 + +  (re + rb )u  2 + + 
β DC  VT f β DC  β 
  T  DC 
J c − opt ≈ 2π (C je + C jc )u VT β DC f
   J fT
2
n 2 fT 
2 0.5

   C (r + r ) (1 + )+  
  2VT e b u β DC f 4 β DC f 2  
 1  f T 2
2
 ( n VT /(2 J C ) + (re + rb ) u ) × 
  
RS −opt ( M ) ≅  
 MN  f  JC fT
2
n2 fT
2

 (re + rb ) u (1 + )+ (1 + )
  2VT β DC f 2 4 β DC f 2 

  
RS − opt ( M ) = 50 = 9855.4 /( MN )
∴ MN ≈ 200

46. Input match & Le choice
1
Z in ≅ ωT Le + j (ϖLe + ωLb − )
ωCπ Input
thus for Z in = Rs = 50
Zin
∴ ωT Le ≅ Rs
& ω 2 ( Le + Lb )Cπ = 1
0
5.0 40 200
1 2 3
(300.000p,2.5642)
2.5 20 100
>>
0 0 0
0 0.5n 1.0n 1.5n 2.0n
1 YatX(NF,1G) 2 YatX(Gain,1G) 3 YatX(Zin,1G)
Le

47. Other parameters
• Area of CB is 55
20 40
1 2 (55.000,23.011)
10 0
(55.000,2.5642)
>>
0 -40
1 20 40 60 70
1 YatX(NF,1g) 2 YatX(Gain,1g)
area2
ωL
• Lc = 9nh & Rs = 11Ohm thus Q= ≈5
R

48. Full circuit diagram
3V
9nH 9nH
Q ~ 5
~ Q ~ 5
~ 0
11 11
OUT- Vbias2
1.85p
AREA = 55 AREA = 55
0
OUT+
1.85p
AREA = 70 AREA = 70
IN+
4p 22.2nH 22.2nH 4p
Rbias
0.3nH 0.3nH
Vbias1
0
IN-
3V
0
AREA = 1
AREA = 1
0

49. Simulation results
20 40 1.2K
1 2 3
20 0.8K
10
0 0.4K
>>
0 -20 0
1 20 40 60 70
1 YatX(nf,1g) 2 YatX(Gain,1g) 3 YatX(Zin,1g)
area
30
(1.0000G,23.111)
20
10
(1.0000G,2.5583)
0
696.40MH 1.000GHz 1.367GHz
z NF Gain
Frequency

50. S-parameters
20.0
(1.0000G,22.850)
0
-20.0 (1.0000G,-27.460)
-33.7
526.54MH 1.000GHz 1.995GHz
z S11 S21
Frequency
-0.0
(1.0000G,-24.762)
-20.0
(1.0000G,-46.103)
-40.0
-60.0
-71.6
332.2MH 1.00GHz 2.43GHz
z S12 S22
Frequency

51. Aplac outputs (linearity& NF)

52. MWO outputs(linearity &
S-parameters)
Pout vs Pin
0
-50
IM1_SP[PORT_2,1] (dBm)
Schematic 1
-100 IM3_SP[PORT_2,1] (dBm)
Schematic 1
-150
-60 -50 -40 -30 -20
Power (dBm)
s-parameters
Swp Max
1.0
s param
0.8
1.1GHz
30
6
0.
0
2.
4
0.
0
3.
S[1,1]
0 Schematic 1 4.
0
5.0
0.2 S[2,1]
Schematic 1
10.0
DB(|S[1,1]|) S[1,2]
-30 Schematic 1
Schematic 1
10.0
0.2
0.4
0.6
0.8
1.0
2.0
3.0
4.0
5.0
0
S[2,2]
DB(|S[2,1]|) Schematic 1
Schematic 1 -10.0
-60 2
-0.
DB(|S[1,2]|) 0
-5.
Schematic 1
0 .
-4
.0
-3
.4
-90 DB(|S[2,2]|) -0
Schematic 1
.0
0.9 0.95 1 1.05 1.1
-2
6.
-0
Frequency (GHz)
-0.8
Swp Min
-1.0
0.9GHz

53. Final aspects
• NF = 2.56 db
• Gain = 23 db
• IIP3 = -19 dbm
• IRL = -27.4 db
• ORL = -24.6db
• Reverse isolation = -46.1db

54. Preselect filter

55. Mixer
• Mixer parameters:
- Gain
- Linearity
- Noise figure
- Port isolation

56. Mixer topologies
• Passive mixer
- Microwave frequency
- No conversion gain
- high power consumption
- Transformer coupling
- Good linearity

57. Mixer topologies
Active mixer: Vcc
LO
LO
- Provides conversion gain
- Low power from LO port RF
- Excellent isolation Vbias
- No matching problem

58. Single balanced vs double
balanced
Vcc Vcc
LO
LO
LO LO
RF RF RF
Vbias Vbias Vbias
0
-Poor port to port isolation -perfect isolation
-Less noise contribution -higher noise contribution

59. Mixer of choice
Active mixer
Double balanced Gilbert cell
Switching mixer

60. Common emitter
• Consists of:
- Driver stage
- Switcher stage
- Load
Driver stage have the main effect in the mixer
linearity and noise figure

61. Gain
18
18
16
16
14 14
12 12
Gain
Gain
10 10
8 8
6 6
4 4
2 2
1 2 3 4 5 6 7 8 9 0 5 10 15 20 25 30 35
Idc
driverarea
Gain with biasing current gain with driver area

62. Noise figure
12 10.5
10
11
9.5
10
9
9
NF(dB)
8.5
NF(DB)
8 8
7 7.5
7
6
6.5
5
0 5 10 15 20 25 30
6
driver area 1 2 3 4 5 6 7 8 9 10
switch area
NF against driver area NF against switches area

63. Shot noise
11
10.5
10
9.5
9
NF(dB)
8.5
8
7.5
7
6.5
6
1 2 3 4 5 6 7 8 9 10
bias current
NF against bias current
Base noise will be more effected at high bias current

64. Linearity
Linearity techniques:
- Emitter resistance degeneration
- Capacitance degeneration
- Inductance degeneration
- Multitanh techniques

65. Gain vs Pin
18.5 12.5
18 12.4
12.3
17.5
12.2
17
12.1
Gain(db)
Gain(db)
16.5
12
16 11.9
15.5 11.8
11.7
15
11.6
14.5
-36 -34 -32 -30 -28 -26 -24 -22 -20 -18
11.5
input power -40 -35 -30 -25 -20 -15 -10
input power
Without degeneration With degeneration

66. Noise degradation
200
100
( 1 0 0 . 0 0 0 M, 1 0 . 2 2 2 )
NF=14db 0
1 . 0 KHz 1 0 KHz 1 . 0 MHz 1 0 0 MHz 1 0 GHz
Inductance degeneration nf
Fr e q u e n c y
200
( 1 0 0 . 0 0 0 M, 1 3 . 3 5 7 )
100
NF=17db
Resistive degeneration 0
1 . 0 KHz 1 0 KHz 1 . 0 MHz 1 0 0 MHz 1 0 GHz
nf
Fr e q u e n c y

67. Final results
Gain=12db
ICP= -17.3dbm
NF=14db
Voltage gain=18db

68. Simulation result
1 . 0 mV
I F s i gnal
0V
RF s i g n a l
- 1 . 0 mV
152. 5ns 156. 0ns 160. 0ns 164. 0ns 168. 0ns 172. 0ns
V( R1 9 : 1 , OUT 2 ) V( N1 0 1 9 8 3 , N1 0 6 9 0 8 )
T i me
1 . 0 mV
out put I F c o mp o n e n t
( 1 0 0 . 0 0 0 M, 8 2 2 . 4 6 4 u )
I nput RF c o mp o n e n t
( 1 . 0 0 0 0 G, 1 0 3 . 1 6 7 u )
100uV
10uV
1 0 MHz 3 0 MHz 1 0 0 MHz 3 0 0 MHz 1 . 0 GHz 3 . 0 GHz
V( R1 9 : 1 , OUT 2 ) V( N1 0 1 9 8 3 , N1 0 6 9 0 8 )
Fr e q u e n c y

69. Intermediate Frequency
(IF)
Super heterodyne Receiver

70. Why IF ?
Selecting a
narrow channel
at RF , means
very high Q for
f0
the filters , so a
down shift in Q=
frequency is ∆f
needed to relax
the channel
select filter’s Q .

71. IF STAGE FOR FM RECEIVERS

72. Automatic Gain Control
(AGC)
AGC means high gain for weak signals ,
and lower gain for relatively strong
signals , in order to maintain a near
constant output level, and to To buffer
the receiver electronics from change in
input signal strength .

73. AGC TECHNIQUES
Digitally controlled

74. AGC TECHNIQUES (2)
Analog controlled

75. RSSI
Received Signal Strength Indicator :
Used to indicate
the changes in
the received signal
level , to control
the gain of the VGA

76. Variable Gain Amplifier

77. Gilbert cell
Maximum gain occurs
at negative V AGC ,
,which causes
the emitter followers
to be off.

78. Second stage
*Area = 5
*Bias current
= 2 mA

79. Simulation Results
Variable Gain of the wide band VGA

80. Simulation Results (2)
Linear response of the VGA with VAGC

81. Simulation Results (3)
Noise Figure and Gain Vs. VAGC

82. Simulation Results (4)
Gain Vs. Area

83. RSSI Circuit
Peak Detector
Differential amplifier in large signal , acts as
a rectifier at its emitter .

84. Simulation Results
Signals at different points

85. Simulation Results (2)
DC o/p for sweep on IF amplitude

86. Simulation Results (3)
DC o/p Vs. i/p strength
( received signal strength indicator )

87. FSK Demodulator
Quadrature detector :
• Most common for IC applications.
• Used for non I-Q Reception.
• Converts the FM signal to a PM signal ,then
detected by a PM detector .

88. FSK Demodulator
Quadrature detector

89. Quadrature Theory

90. Phase Network
900 phase at the center frequency
± 900 at 2 FSK frequencies

91. The multiplier
Gilbert Multiplier

92. Simulation Results
o/p spectrum of the multiplier

93. Simulation Results (2)
The DC output of the LPF , after
the multiplier

94. Receiver Section
Receiver Noise figure
NF(calc.) = 2.9 db & NF(sim.) = 3.1db

95. Receiver Section
Front end wave form
1 4 . 3 mV
1 0 . 0 mV
0V
- 1 0 . 0 mV
- 1 6 . 0 mV
568. 1ns 572. 0ns 576. 0ns 580. 0ns 584. 0ns 588. 0ns 592. 0ns
V( L 6 : 1 , R7 3 4 2 6 : 2 ) V( F RONT , F RONT 1 ) V( I F 1 , I F 2 )
T i me
Gain(calc.) = 41db Gain(sim.) =44db

96. Receiver section
• AGC Action
1 5 . 9 mV
1 0 . 0 mV
0V
- 1 0 . 0 mV
- 1 5 . 2 mV
213. 0ns 220. 0ns 230. 0ns 240. 0ns 247. 8ns
V( I F 1 , I F 2 ) V( C2 0 7 , Q2 0 8 : c )
T i me