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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 10 Chapter 10 Input/Output Organization Input/Output Organization
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter Outline Chapter Outline • Asynchronous data transfers Asynchronous data transfers • Programmed I/O Programmed I/O • Interrupts Interrupts • Direct Memory Access Direct Memory Access • I/O Processors I/O Processors • Serial Communication Serial Communication • Serial Communication Standards Serial Communication Standards
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Data Transfers Asynchronous Data Transfers
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Source-initiated Data Transfer Source-initiated Data Transfer
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Destination-initiated Data Destination-initiated Data Transfer Transfer
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Source-initiated Data Transfer Source-initiated Data Transfer with Handshaking with Handshaking
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Destination-initiated Data Destination-initiated Data Transfer with Handshaking Transfer with Handshaking
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Programmed I/O Programmed I/O
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example Example
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example Example
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example Example
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example Example
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example Example
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 New Instructions New Instructions
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 New Control Signals New Control Signals • IO differentiates I/O and memory IO differentiates I/O and memory accesses accesses – IO = 1 for I/O access IO = 1 for I/O access – IO = 0 for memory access IO = 0 for memory access
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 New States and RTL Code New States and RTL Code
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications CPU Modifications • Modify register section Modify register section
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications CPU Modifications • Modify register section Modify register section • Modify ALU Modify ALU
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications CPU Modifications • Modify register section Modify register section • Modify ALU Modify ALU • Modify control unit (hard-wired) Modify control unit (hard-wired)
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications CPU Modifications • Modify register section Modify register section • Modify ALU Modify ALU • Modify control unit (hard-wired) Modify control unit (hard-wired) • Register and ALU sections unchanged Register and ALU sections unchanged
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications CPU Modifications • Modify register section Modify register section • Modify ALU Modify ALU • Modify control unit (hard-wired) Modify control unit (hard-wired) • Register and ALU sections unchanged Register and ALU sections unchanged • One new micro-operation: DR One new micro-operation: DR   Input Input Port Port
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Changes Control Unit Changes
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Changes - INC Control Unit Changes - INC and CLR signals and CLR signals
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Changes - INC Control Unit Changes - INC and CLR signals and CLR signals
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Changes - Control Unit Changes - Memory Read Signal Memory Read Signal • Memory Read = READ ^ Memory Read = READ ^ IO IO’ ’
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Interrupts Interrupts • Polling Polling
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Interrupts Interrupts • IRQ - Interrupt Request IRQ - Interrupt Request • IACK - Interrupt Acknowledge IACK - Interrupt Acknowledge
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Types of Interrupts Types of Interrupts • External External
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Types of Interrupts Types of Interrupts • External External • Internal Internal
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Types of Interrupts Types of Interrupts • External External • Internal Internal • Software Software
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Processing Interrupts Processing Interrupts • Do nothing (until the current instruction Do nothing (until the current instruction has been executed) has been executed)
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Processing Interrupts Processing Interrupts • Do nothing (until the current instruction Do nothing (until the current instruction has been executed) has been executed) • Get handler address (vectored) Get handler address (vectored)
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Processing Interrupts Processing Interrupts • Do nothing (until the current instruction Do nothing (until the current instruction has been executed) has been executed) • Get handler address (vectored) Get handler address (vectored) • Invoke handler routine Invoke handler routine
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Vectored Interrupt Hardware Vectored Interrupt Hardware
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Non-vectored Interrupt Non-vectored Interrupt Hardware Hardware
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Multiple Non-vectored Multiple Non-vectored Interrupts Interrupts
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Daisy Chaining Daisy Chaining
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 IACK IACKin in and IACK and IACKout out
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Parallel Priority Interrupts Parallel Priority Interrupts
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications CPU Modifications
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications CPU Modifications
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Interrupt States Interrupt States
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Direct Memory Access Direct Memory Access
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 DMA Controller DMA Controller
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 DMA Transfer Modes DMA Transfer Modes • Block/Burst Mode Block/Burst Mode
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 DMA Transfer Modes DMA Transfer Modes • Block/Burst Mode Block/Burst Mode • Cycle Stealing Mode Cycle Stealing Mode
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 DMA Transfer Modes DMA Transfer Modes • Block/Burst Mode Block/Burst Mode • Cycle Stealing Mode Cycle Stealing Mode • Transparent Mode Transparent Mode
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications - Micro- CPU Modifications - Micro- operations operations
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications - Micro- CPU Modifications - Micro- operations operations
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications CPU Modifications
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications CPU Modifications
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Processors I/O Processors
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Processors - operations I/O Processors - operations • Block transfer commands Block transfer commands
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Processors - operations I/O Processors - operations • Block transfer commands Block transfer commands • ALU operations ALU operations
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Processors - operations I/O Processors - operations • Block transfer commands Block transfer commands • ALU operations ALU operations • Control commands Control commands
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Asynchronous Serial Communication Communication • bps - Bits Per Second (baud rate) bps - Bits Per Second (baud rate)
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Asynchronous Serial Communication Communication • bps - Bits Per Second (baud rate) bps - Bits Per Second (baud rate) • start bit start bit
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Asynchronous Serial Communication Communication • bps - Bits Per Second (baud rate) bps - Bits Per Second (baud rate) • start bit start bit • parity bit parity bit
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Asynchronous Serial Communication Communication • bps - Bits Per Second (baud rate) bps - Bits Per Second (baud rate) • start bit start bit • parity bit parity bit • stop bit(s) stop bit(s)
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Asynchronous Serial Communication Communication • bps - Bits Per Second (baud rate) bps - Bits Per Second (baud rate) • start bit start bit • parity bit parity bit • stop bit(s) stop bit(s) • bit time bit time
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Asynchronous Serial Communication Communication
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Synchronous Serial Synchronous Serial Communication - HDLC Communication - HDLC
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Universal Asynchronous Universal Asynchronous Receiver/Transmitters Receiver/Transmitters
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 UART Internal Configuration UART Internal Configuration
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 • Request To Send Request To Send • Clear To Send Clear To Send • Transmission Data Transmission Data • Data Terminal Ready Data Terminal Ready • Data Set Ready Data Set Ready • Received Data Received Data • Data Carrier Detect Data Carrier Detect • Ring Indicator Ring Indicator • Ground Ground RS 232C Standard - Signals RS 232C Standard - Signals
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - RS 232C Standard - Connection Connection • Use RTS, CTS, DTR, and DSR to verify Use RTS, CTS, DTR, and DSR to verify that both devices are active that both devices are active
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - RS 232C Standard - Connection Connection • Use RTS, CTS, DTR, and DSR to verify Use RTS, CTS, DTR, and DSR to verify that both devices are active that both devices are active • Use RI to indicate call status Use RI to indicate call status
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - RS 232C Standard - Connection Connection • Use RTS, CTS, DTR, and DSR to verify Use RTS, CTS, DTR, and DSR to verify that both devices are active that both devices are active • Use RI to indicate call status Use RI to indicate call status • Use DCD to establish connectivity Use DCD to establish connectivity
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - RS 232C Standard - Connection Connection • Use RTS, CTS, DTR, and DSR to verify Use RTS, CTS, DTR, and DSR to verify that both devices are active that both devices are active • Use RI to indicate call status Use RI to indicate call status • Use DCD to establish connectivity Use DCD to establish connectivity • Use TD and RD to transfer data, and Use TD and RD to transfer data, and RTS and CTS to coordinate transfers RTS and CTS to coordinate transfers
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 422 Standard - Signals RS 422 Standard - Signals
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Universal Serial Bus Standard Universal Serial Bus Standard • Connects one port to several devices Connects one port to several devices
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Universal Serial Bus Standard Universal Serial Bus Standard • Connects one port to several devices Connects one port to several devices • Transfers data in packets Transfers data in packets – Token packets Token packets – Data packets Data packets – Handshake packets Handshake packets – Special Packets Special Packets
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 USB Packet Formats USB Packet Formats
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Summary Summary • Asynchronous data transfers Asynchronous data transfers • Programmed I/O Programmed I/O • Interrupts Interrupts • Direct Memory Access Direct Memory Access • I/O Processors I/O Processors • Serial Communication Serial Communication • Serial Communication Standards Serial Communication Standards

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Presentation for the swing demo computer science

  • 1.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 10 Chapter 10 Input/Output Organization Input/Output Organization
  • 2.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter Outline Chapter Outline • Asynchronous data transfers Asynchronous data transfers • Programmed I/O Programmed I/O • Interrupts Interrupts • Direct Memory Access Direct Memory Access • I/O Processors I/O Processors • Serial Communication Serial Communication • Serial Communication Standards Serial Communication Standards
  • 3.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Data Transfers Asynchronous Data Transfers
  • 4.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Source-initiated Data Transfer Source-initiated Data Transfer
  • 5.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Destination-initiated Data Destination-initiated Data Transfer Transfer
  • 6.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Source-initiated Data Transfer Source-initiated Data Transfer with Handshaking with Handshaking
  • 7.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Destination-initiated Data Destination-initiated Data Transfer with Handshaking Transfer with Handshaking
  • 8.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Programmed I/O Programmed I/O
  • 9.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example Example
  • 10.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example Example
  • 11.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example Example
  • 12.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example Example
  • 13.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example Example
  • 14.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 New Instructions New Instructions
  • 15.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 New Control Signals New Control Signals • IO differentiates I/O and memory IO differentiates I/O and memory accesses accesses – IO = 1 for I/O access IO = 1 for I/O access – IO = 0 for memory access IO = 0 for memory access
  • 16.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 New States and RTL Code New States and RTL Code
  • 17.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications CPU Modifications • Modify register section Modify register section
  • 18.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications CPU Modifications • Modify register section Modify register section • Modify ALU Modify ALU
  • 19.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications CPU Modifications • Modify register section Modify register section • Modify ALU Modify ALU • Modify control unit (hard-wired) Modify control unit (hard-wired)
  • 20.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications CPU Modifications • Modify register section Modify register section • Modify ALU Modify ALU • Modify control unit (hard-wired) Modify control unit (hard-wired) • Register and ALU sections unchanged Register and ALU sections unchanged
  • 21.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications CPU Modifications • Modify register section Modify register section • Modify ALU Modify ALU • Modify control unit (hard-wired) Modify control unit (hard-wired) • Register and ALU sections unchanged Register and ALU sections unchanged • One new micro-operation: DR One new micro-operation: DR   Input Input Port Port
  • 22.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Changes Control Unit Changes
  • 23.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Changes - INC Control Unit Changes - INC and CLR signals and CLR signals
  • 24.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Changes - INC Control Unit Changes - INC and CLR signals and CLR signals
  • 25.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Changes - Control Unit Changes - Memory Read Signal Memory Read Signal • Memory Read = READ ^ Memory Read = READ ^ IO IO’ ’
  • 26.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Interrupts Interrupts • Polling Polling
  • 27.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Interrupts Interrupts • IRQ - Interrupt Request IRQ - Interrupt Request • IACK - Interrupt Acknowledge IACK - Interrupt Acknowledge
  • 28.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Types of Interrupts Types of Interrupts • External External
  • 29.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Types of Interrupts Types of Interrupts • External External • Internal Internal
  • 30.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Types of Interrupts Types of Interrupts • External External • Internal Internal • Software Software
  • 31.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Processing Interrupts Processing Interrupts • Do nothing (until the current instruction Do nothing (until the current instruction has been executed) has been executed)
  • 32.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Processing Interrupts Processing Interrupts • Do nothing (until the current instruction Do nothing (until the current instruction has been executed) has been executed) • Get handler address (vectored) Get handler address (vectored)
  • 33.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Processing Interrupts Processing Interrupts • Do nothing (until the current instruction Do nothing (until the current instruction has been executed) has been executed) • Get handler address (vectored) Get handler address (vectored) • Invoke handler routine Invoke handler routine
  • 34.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Vectored Interrupt Hardware Vectored Interrupt Hardware
  • 35.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Non-vectored Interrupt Non-vectored Interrupt Hardware Hardware
  • 36.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Multiple Non-vectored Multiple Non-vectored Interrupts Interrupts
  • 37.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Daisy Chaining Daisy Chaining
  • 38.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 IACK IACKin in and IACK and IACKout out
  • 39.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Parallel Priority Interrupts Parallel Priority Interrupts
  • 40.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications CPU Modifications
  • 41.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications CPU Modifications
  • 42.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Interrupt States Interrupt States
  • 43.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Direct Memory Access Direct Memory Access
  • 44.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 DMA Controller DMA Controller
  • 45.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 DMA Transfer Modes DMA Transfer Modes • Block/Burst Mode Block/Burst Mode
  • 46.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 DMA Transfer Modes DMA Transfer Modes • Block/Burst Mode Block/Burst Mode • Cycle Stealing Mode Cycle Stealing Mode
  • 47.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 DMA Transfer Modes DMA Transfer Modes • Block/Burst Mode Block/Burst Mode • Cycle Stealing Mode Cycle Stealing Mode • Transparent Mode Transparent Mode
  • 48.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications - Micro- CPU Modifications - Micro- operations operations
  • 49.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications - Micro- CPU Modifications - Micro- operations operations
  • 50.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications CPU Modifications
  • 51.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications CPU Modifications
  • 52.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Processors I/O Processors
  • 53.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Processors - operations I/O Processors - operations • Block transfer commands Block transfer commands
  • 54.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Processors - operations I/O Processors - operations • Block transfer commands Block transfer commands • ALU operations ALU operations
  • 55.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Processors - operations I/O Processors - operations • Block transfer commands Block transfer commands • ALU operations ALU operations • Control commands Control commands
  • 56.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Asynchronous Serial Communication Communication • bps - Bits Per Second (baud rate) bps - Bits Per Second (baud rate)
  • 57.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Asynchronous Serial Communication Communication • bps - Bits Per Second (baud rate) bps - Bits Per Second (baud rate) • start bit start bit
  • 58.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Asynchronous Serial Communication Communication • bps - Bits Per Second (baud rate) bps - Bits Per Second (baud rate) • start bit start bit • parity bit parity bit
  • 59.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Asynchronous Serial Communication Communication • bps - Bits Per Second (baud rate) bps - Bits Per Second (baud rate) • start bit start bit • parity bit parity bit • stop bit(s) stop bit(s)
  • 60.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Asynchronous Serial Communication Communication • bps - Bits Per Second (baud rate) bps - Bits Per Second (baud rate) • start bit start bit • parity bit parity bit • stop bit(s) stop bit(s) • bit time bit time
  • 61.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Asynchronous Serial Communication Communication
  • 62.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Synchronous Serial Synchronous Serial Communication - HDLC Communication - HDLC
  • 63.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Universal Asynchronous Universal Asynchronous Receiver/Transmitters Receiver/Transmitters
  • 64.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 UART Internal Configuration UART Internal Configuration
  • 65.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 • Request To Send Request To Send • Clear To Send Clear To Send • Transmission Data Transmission Data • Data Terminal Ready Data Terminal Ready • Data Set Ready Data Set Ready • Received Data Received Data • Data Carrier Detect Data Carrier Detect • Ring Indicator Ring Indicator • Ground Ground RS 232C Standard - Signals RS 232C Standard - Signals
  • 66.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - RS 232C Standard - Connection Connection • Use RTS, CTS, DTR, and DSR to verify Use RTS, CTS, DTR, and DSR to verify that both devices are active that both devices are active
  • 67.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - RS 232C Standard - Connection Connection • Use RTS, CTS, DTR, and DSR to verify Use RTS, CTS, DTR, and DSR to verify that both devices are active that both devices are active • Use RI to indicate call status Use RI to indicate call status
  • 68.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - RS 232C Standard - Connection Connection • Use RTS, CTS, DTR, and DSR to verify Use RTS, CTS, DTR, and DSR to verify that both devices are active that both devices are active • Use RI to indicate call status Use RI to indicate call status • Use DCD to establish connectivity Use DCD to establish connectivity
  • 69.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - RS 232C Standard - Connection Connection • Use RTS, CTS, DTR, and DSR to verify Use RTS, CTS, DTR, and DSR to verify that both devices are active that both devices are active • Use RI to indicate call status Use RI to indicate call status • Use DCD to establish connectivity Use DCD to establish connectivity • Use TD and RD to transfer data, and Use TD and RD to transfer data, and RTS and CTS to coordinate transfers RTS and CTS to coordinate transfers
  • 70.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 422 Standard - Signals RS 422 Standard - Signals
  • 71.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Universal Serial Bus Standard Universal Serial Bus Standard • Connects one port to several devices Connects one port to several devices
  • 72.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Universal Serial Bus Standard Universal Serial Bus Standard • Connects one port to several devices Connects one port to several devices • Transfers data in packets Transfers data in packets – Token packets Token packets – Data packets Data packets – Handshake packets Handshake packets – Special Packets Special Packets
  • 73.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 USB Packet Formats USB Packet Formats
  • 74.
    Images courtesy ofAddison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Summary Summary • Asynchronous data transfers Asynchronous data transfers • Programmed I/O Programmed I/O • Interrupts Interrupts • Direct Memory Access Direct Memory Access • I/O Processors I/O Processors • Serial Communication Serial Communication • Serial Communication Standards Serial Communication Standards